CN103176766A - Binary system adder-subtractor based on enhancement-type LUT (look up table) 5 structure - Google Patents
Binary system adder-subtractor based on enhancement-type LUT (look up table) 5 structure Download PDFInfo
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Abstract
The invention relates to a binary system adder-subtractor, and discloses a binary system adder-subtractor based on an enhancement-type LUT (look up table) 5 structure. According to the invention, the binary system adder-subtractor comprises an enhancement-type 5 input LUT structure, a carry chain structure and a standard xor structure; addition and subtraction logic of two digits is realized for the LUT5 structure by utilizing a LUT 4 with two 3 input share; the port resource utilization ratio achieves 4/5; when controllable addition and subtraction logic (with addition and subtraction control signal input) is realized, the port resource utilization ratio even achieves 5/5=100%; compared with the existing individual 4 input LUT, one digit addition and subtraction is realized, the port utilization ratio is increased by 30%, and the area utilization ratio is improved greatly. Additionally, the carry chain structure comprises two carry look ahead structures; two carry chain logic delays are lowered from two traditional selectors to delay time of a tristate phase inverter; the digit transmission delay is reduced; and the working frequency of the adder-subtractor is improved.
Description
Technical field
The present invention relates to the binary add subtracter, particularly based on the binary add subtracter of enhancement mode LUT5 structure.
Background technology
In programmable logic device (PLD), usually realize random logic function and the sequential logic of user in designing by programmable logic cells.For field programmable logic array (FPLA) (FPGA), most programmable logic cells inside is all look-up table (the look up table by some, abbreviation " LUT ") structure and timing unit (edging trigger type register or level-type latch) form, and a N input look-up table configuration is to realize any one N input combinational logic function, utilizes 2 in look-up table configuration
NMemory array preserve N and input corresponding functional value.Metal line and gate-controlled switch (programmable interconnect) by customization in advance between programmable logic cells link together.
All can use a large amount of plus-minus method logics in the design that great majority need FPGA to realize, its bit wide is also along with application requirements is more and more higher.Carry chain (carry chain) is a kind of chain type mode that realizes carry transmission in multidigit plus-minus method logic.Each plus-minus method logic all is decomposed into one's own department or unit and function and carry function.One's own department or unit and function are the net result output at one's own department or unit, and the carry function is given the plus-minus method logic of next bit.The carry function cascaded of each interdigit has consisted of carry chain.Determined the arithmetic speed of multidigit adder-subtractor the time delay of carry chain.
Increase carry chain logic and other logics realize that the method for large bit wide ripple carry adder-subtractor is adopting in a lot of field programmable logic array (FPLA) devices in programmable logic cells.Its principle adds/improvement of subtract logic based on ripple carry.
For a n position binary addition logic x+y, mathematic(al) representation is: s[n:0]=x[n-1:0]+y[n-1:0]+cin[0], s[n] and be the most significant digit carry, cin[0]=0;
For a n position binary subtraction logic x-y, mathematic(al) representation is: s[n:0]=x[n-1:0]+(/y[n-1:0])+cin[0], s[n] and be the most significant digit borrow, cin[0]=1;
Top expression formula can resolve into the combination of n 1 binary add subtract logic, and is as follows:
sum[n]=x[n]^y[n]^cin[n-1]；
co[n]=(x[n]^y[n])*cin[n-1]|/(x[n]^y[n])*k[n]；（n=0～n-1）
Adder logic: cin[0]=0, x[n]=x[n], y[n]=y[n], k[n]=x[n] or y[n];
Subtract logic: cin[0]=1, x[n]=x[n], y[n]=/y[n], k[n]=x[n] or/y[n];
It should be noted that symbol "/" representative " anti-phase ", symbol " ^ " represents distance, symbol " * " representative " with ", symbol " | " represents "or", x^ in binary logic (/y) be equivalent to/(x^y) or (/x) ^y.
1 binary addition logic realization as shown in Figure 1.Consisted of the carry logic chain by cin to the cascade selector switch of co in Fig. 2.Clearly, the delay of carry logic chain is the maximum delay path of whole arithmetic logic, and it has determined the maximum operation frequency of whole totalizer.
And adopted one independently 4 to input look-up table configuration in conjunction with the mode of carry chain and 1 adder logic of one's own department or unit generation logic realization in a plurality of devices of xilinx company, and seeing US5481206 for details, Fig. 3 is the cascade structure schematic diagram of respectively this 1 adder logic.
Yet exist the low problem of hardware resource utilization as the existing plus-minus method implementation of xilinx company: when realizing plus-minus method with single LUT4 structure and carry logic etc., the programmable logic cells waste is many.Each programmable logic cells is the LUT unit of some, consists of in conjunction with large fan-in input selector (as in Fig. 4 402) and outside interconnect resource (as in Fig. 4 401).Therefore, under the fixing prerequisite of one-piece construction, the size of resource utilization depends on as far as possible with less programmable logic cells and realizes N position addition.4 input ports as its LUT in Fig. 4 have only used two, have the input selector 401 of half not use, and half resource has been wasted.As 2 LUT4 structures in Fig. 4 totally 8 inputs only realized two additions.When realizing plus-minus method, resource utilization may be defined as the ratio of attainable adding/subtraction input number and LUT independent input input number.Therefore be 2 inputs of 2/4(1 position addition as resource utilization in Fig. 4, one LUT4 input).
Therefore, the present inventor finds, the look-up table configuration number that consumes when realizing the plus-minus method logic based on the logical function production part of look-up table configuration merely causes too much that area is huge, cost rises, connect carry logic by the common interconnection between look-up table configuration simultaneously and also make large bit wide plus-minus method too large logical delay, can't satisfy the demand of high speed design.
Summary of the invention
The object of the present invention is to provide a kind of binary add subtracter based on enhancement mode LUT5 structure, greatly optimized the area utilization of large bit wide adder-subtractor.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of binary add subtracter based on enhancement mode LUT5 structure, comprise LUT5 structure, carry chain structure, first one's own department or unit XOR structure and second one's own department or unit XOR structure;
This LUT5 structure comprises a LUT4 structure and the 2nd LUT4 structure;
the one LUT4 structure comprises that four LUT2 structures and the 1 select 1 selector switch, the 2nd LUT4 structure comprises that four LUT2 structures and the 24 select 1 selector switch, two input ends of above-mentioned LUT2 structure connect respectively first and second of the first binary number, the above-mentioned the 1 selects 1 selector switch and the 24 to select each four input ends of 1 selector switch to connect respectively the output terminal of corresponding each four LUT2 structures, the one 4 selects two control ends of 1 selector switch to meet respectively add-subtract control signal and the second binary number first, the 24 selects two control ends of 1 selector switch to connect respectively the second of above-mentioned add-subtract control signal and the second binary number,
It is 0 o'clock at above-mentioned add-subtract control signal, first and the primary XOR result of the second binary number of the one LUT4 structure output the first binary number, the deputy XOR result of the second of the 2nd LUT4 structure output the first binary number and the second binary number;
It is 1 o'clock at above-mentioned add-subtract control signal, the anti-phase result of the primary XOR of first of the one LUT4 structure output the first binary number and the second binary number, the anti-phase result of the second of the 2nd LUT4 structure output the first binary number and the deputy XOR of the second binary number;
Above-mentioned carry chain structure is configured to receive first and Output rusults and the prime carry signal of second, an above-mentioned LUT4 structure and the 2nd LUT4 structure of the first binary number, and exports the first carry signal and the second carry signal;
Above-mentioned first one's own department or unit XOR structure is configured to receive the Output rusults of above-mentioned prime carry signal, a LUT4 structure and exports first one's own department or unit result, and above-mentioned second one's own department or unit XOR structure is configured to receive the Output rusults of above-mentioned the first carry signal, the 2nd LUT4 structure and exports second one's own department or unit result.
Embodiment of the present invention compared with prior art, the key distinction and effect thereof are:
The present invention includes enhancement mode 5 input LUT5 structures, carry chain structure and one's own department or unit XOR structure, the LUT4 structure that this enhancement mode LUT5 structure utilizes two 3 inputs to share realizes the plus-minus method logic of two simultaneously, the port resource utilization factor has reached 4/5, and when realizing controlled plus-minus method logic (with the input of add-subtract control signal), the port resource utilization factor has reached 5/5=100% especially, has greatly improved area utilization.
Further, above-mentioned carry chain structure comprises 2 carry look ahead chain structures, it has been reduced to the time delay of a tri-state inverter with 2 carry chains logical delay from two traditional selector switchs, reduced the carry transmission delay, has improved the frequency of operation of adder-subtractor.
Further, above-mentioned one's own department or unit XOR structure is lacked than traditional one's own department or unit XOR structure and is used two pipes, has further improved area utilization.
Further, by carry signal, each binary add subtractor stage is linked togather, has extensibility.
Description of drawings
Fig. 1 is the structural representation of existing 1 adder logic;
Fig. 2 is the structural representation of existing multi digit addition logic;
Fig. 3 is the structural representation of existing another kind of multi digit addition logic;
Fig. 4 is the structural representation of existing another kind of multi digit addition logic;
Fig. 5 is the structural representation of a kind of enhancement mode LUT5 structure in the first embodiment;
Fig. 6 is the structural representation of a kind of binary add subtracter based on enhancement mode LUT5 structure in first embodiment of the invention;
Fig. 7 is that in first embodiment of the invention, each LUT2 structure realizes X[0] and X[1] the schematic diagram of function;
Fig. 8 is the structural representation of a kind of binary add subtracter based on enhancement mode LUT5 structure in second embodiment of the invention;
Fig. 9 is a kind of schematic diagram based on 2 carry look ahead chain structures in the binary add subtracter of enhancement mode LUT5 structure in second embodiment of the invention;
Figure 10 is the structural representation of a kind of binary add subtracter based on enhancement mode LUT5 structure in third embodiment of the invention;
Figure 11 is the schematic diagram of existing one's own department or unit XOR structure;
Figure 12 is the structural representation of a kind of binary add subtracter cascade based on enhancement mode LUT5 structure in third embodiment of the invention;
Figure 13 is the structural representation of another kind of binary add subtracter cascade based on enhancement mode LUT5 structure in third embodiment of the invention.
Embodiment
In the following description, in order to make the reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to a kind of binary add subtracter based on enhancement mode LUT5 structure.Enhancement mode LUT5 structure refers to that the input end in common LUT5 structure increases by one 2 and selects 1 selector switch, produces the LUT4 structure that two 3 inputs are shared, and as shown in Figure 5, A, B, C are three input ends sharing, and D, E are another two input ends, and F is output.
Fig. 6 is based on the structural representation of the binary add subtracter of enhancement mode LUT5 structure shown in Figure 5, and the device of not using in Fig. 5 does not show.Should comprise LUT5 structure 601, carry chain structure 602, first one's own department or unit XOR structure 606a and second one's own department or unit XOR structure 606b based on the binary add subtracter of enhancement mode LUT5 structure.
As shown in Figure 6, this LUT5 structure comprises a LUT4 structure 601a and the 2nd LUT4 structure 601b.
the one LUT4 structure comprises that four LUT2 structures and the 1 select 1 selector switch, the 2nd LUT4 structure comprises that four LUT2 structures and the 24 select 1 selector switch, two input ends of each LUT2 structure meet respectively first X[0 of the first binary number X] and second X[1], the one 4 selects 1 selector switch and the 24 to select each four input ends of 1 selector switch to connect respectively the output terminal of corresponding each four LUT2 structures, the one 4 selects two control end S0 of 1 selector switch, S1 meets respectively first Y[0 of add-subtract control signal sub and the second binary number Y], the 24 selects two control end S0 of 1 selector switch, S1 meets respectively the second Y[1 of add-subtract control signal sub and the second binary number Y].
It is 0 o'clock at add-subtract control signal sub, first X[0 of the one LUT4 structure output the first binary number X] and first Y[0 of the second binary number Y] the XOR result, the second X[1 of the 2nd LUT4 structure output the first binary number X] and the second Y[1 of the second binary number Y] the XOR result.
It is 1 o'clock at add-subtract control signal sub, first X[0 of the one LUT4 structure output the first binary number X] and first Y[0 of the second binary number Y] the anti-phase result of XOR, the second X[1 of the 2nd LUT4 structure output the first binary number X] and the second Y[1 of the second binary number Y] the anti-phase result of XOR.
In a preferred example, the LUT4 structure 601a in Fig. 6 and the 2nd LUT4 structure 601b can realize the X that controlled by add-subtract control signal sub and the XOR between Y with or logic.Wherein, preferably, as shown in Figure 7, each 42 input look-up table LUT2 structures are used for realizing respectively X[0] and X[1] function, during sub=0, F0=X0^Y0, F1=X1^Y1; During sub=1, F0=/X0^Y0, F1=/X1^Y1.It will be appreciated, of course, that in other embodiments of the present invention, other functions also can be set as required to coordinate follow-up logical organization, be not limited to above-mentioned function.
Can be seen by Fig. 6, three input end A0, B0, C0 that two LUT4 structures are shared meet respectively X[0], X[1], sub, another two input end D0, E0 meet respectively Y[0], Y[1].Because Fig. 6 is based on enhancement mode LUT5 structure shown in Figure 5, Y[0], Y[1] meet respectively the control end S1 of a LUT4 structure and the 2nd LUT4 structure after selecting 1 selector switch through 1, but be understandable that Y[0], Y[1] also can directly connect the control end S1 of a LUT4 structure and the 2nd LUT4 structure.
First one's own department or unit XOR structure 606a is configured to receive the Output rusults F0 of prime carry signal Cin0, a LUT4 structure and exports first one's own department or unit S[0 as a result], second one's own department or unit XOR structure 606b is configured to receive the first carry signal Co[0], the Output rusults F1 of the 2nd LUT4 structure and export second one's own department or unit S[1 as a result].
The present invention includes enhancement mode 5 input LUT5 structures, carry chain structure and one's own department or unit XOR structure, the LUT4 structure that this enhancement mode LUT5 structure utilizes two 3 inputs to share realizes the plus-minus method logic of two simultaneously, the port resource utilization factor has reached 4/5, and when realizing controlled plus-minus method logic (with the input of add-subtract control signal), the port resource utilization factor has reached 5/5=100% especially, has greatly improved area utilization.
Second embodiment of the invention relates to a kind of binary add subtracter based on enhancement mode LUT5 structure.Fig. 8 is that this is based on the structural representation of the binary add subtracter of enhancement mode LUT5 structure.
The second embodiment improves on the basis of the first embodiment, main improvements are: above-mentioned carry chain structure comprises 2 carry look ahead chain structures, it has been reduced to the time delay of a tri-state inverter logical delay with 2 carry chains from two traditional selector switchs, reduce the carry transmission delay, improved the frequency of operation of adder-subtractor.Specifically:
Above-mentioned carry chain structure comprises 2 carry look ahead chain structures (604,605), as shown in Figure 8, three input end IN0, IN1 of 605 structures, IN2 connect respectively the output terminal of a LUT2 structure in prime carry signal Cin0, a LUT4 structure and the 2nd LUT4 structure, under the configuration of Fig. 7, the LUT2 structure that connects is exported respectively X[0] and X[1], it will be appreciated, of course, that input end IN1, IN2 also can directly connect input end A0, B0.And each control signal F1*F0, the F1*/F0 of 604 structures and/F1 meets respectively three control end S0, S1, the S2 of 605 structures to control the output of each input signal.
As shown in Figure 9, these 2 carry look ahead chain structures comprise and door, tristate inverter sinv, the first phase inverter, the second phase inverter, the first transmission gate, the second transmission gate and the 3rd transmission gate.
Be appreciated that transmission gate is a kind of switch of signal transmission, controlled by the control signal of control end.
The second X[1 of the input termination first binary number X of this first phase inverter], the input end of output termination the first transmission gate, the anti-phase Output rusults/F1 of control termination the 2nd LUT4 structure of this first transmission gate.
First X[0 of the input termination first binary number X of this second phase inverter], the input end of output termination the second transmission gate, the Output rusults F1 of control termination the 2nd LUT4 structure of this second transmission gate, the input end of output termination the 3rd transmission gate of this second transmission gate, the anti-phase Output rusults/F0 of control termination the one LUT4 structure of the 3rd transmission gate.
Should meet respectively Output rusults F0, the F1 of a LUT4 structure and the 2nd LUT4 structure with two input ends of door, should with the control end of the output termination tristate inverter sinv of door, the input termination prime carry signal Cin0 of this tristate inverter sinv.
The output terminal of above-mentioned the first transmission gate, the 3rd transmission gate and tristate inverter sinv is interconnected to form the anti-phase result/Co[1 of above-mentioned second carry signal of output terminal output of these 2 carry look ahead chain structures].
In addition, be appreciated that and also can not adopt 2 carry look ahead chain structures in other embodiments of the present invention, also can realize technical scheme of the present invention.
It should be noted that 2 carry logics generations in Fig. 6 are to select 1 selector switch cascade to generate by two 2, therefore will postpone through the two-stage selector switch.And the present invention becomes shown in Figure 8 604 and 605 high-speed structures that consist of, this circuit to realize Cin to Co[1 its circuit optimization] optimization of critical path delay.From Cin0 to/Co[1] path only has the gate delay (Tsinv) of one-level tristate inverter, is far smaller than the delay of two selector switchs in existing design, and can be with carry cascade delay reduction in a N position adder-subtractor to N/2 Tsinv.
Third embodiment of the invention relates to a kind of binary add subtracter based on enhancement mode LUT5 structure.Figure 10 is that this is based on the structural representation of the binary add subtracter of enhancement mode LUT5 structure.
The 3rd embodiment improves on the basis of first, second embodiment, and main improvements are: above-mentioned one's own department or unit XOR structure is lacked than traditional one's own department or unit XOR structure and is used two pipes, has further improved area utilization.Specifically:
as shown in figure 10, first one's own department or unit XOR structure 606a comprises the first Sheffer stroke gate, the 3rd phase inverter and the 1 selects 1 selector switch, wherein input termination prime carry signal Cin0 for one of the first Sheffer stroke gate, another input end is controlled by programmed point FUSE, the input end of output termination the 3rd phase inverter of this first Sheffer stroke gate also selects an input end of 1 selector switch to be connected with the 1, the output terminal and the 1 of the 3rd phase inverter selects another input end of 1 selector switch to be connected, the one 2 selects the Output rusults F0 of control termination the one LUT4 structure of 1 selector switch, it is 0 o'clock at programmed point FUSE, the one 2 selects the Output rusults F0 of output terminal output the one LUT4 structure of 1 selector switch, it is 1 o'clock at programmed point FUSE, the one 2 selects the output terminal of 1 selector switch to export first one's own department or unit S[0 as a result].
second one's own department or unit XOR structure 606b comprises the second Sheffer stroke gate, the 4th phase inverter and the 22 selects 1 selector switch, wherein input termination the first carry signal Co[0 for one of the second Sheffer stroke gate], another input end is controlled by programmed point FUSE, the input end of output termination the 4th phase inverter of this second Sheffer stroke gate also selects an input end of 1 selector switch to be connected with the 22, the output terminal and the 22 of the 4th phase inverter selects another input end of 1 selector switch to be connected, the 22 selects the Output rusults F1 of control termination the 2nd LUT4 structure of 1 selector switch, it is 0 o'clock at programmed point FUSE, the 22 selects the Output rusults F1 of output terminal output the 2nd LUT4 structure of 1 selector switch, it is 1 o'clock at programmed point FUSE, the 22 selects the output terminal of 1 selector switch to export second one's own department or unit S[1 as a result].
In addition, be appreciated that in other embodiments of the present invention, also can not adopt one's own department or unit XOR structure in Figure 10, also can realize technical scheme of the present invention.
Pattern in one's own department or unit XOR structure shown in Figure 10 is controlled by programmed point FUSE:
FUSE=0, circuit are the LUT patterns, the value F output of look-up table configuration.
FUSE=1, circuit are the carry addition patterns, and F and carry signal Cin carry out exporting after XOR (XOR).
General one's own department or unit XOR structure needs one 2 select 1 selector switch and XOR gate as shown in figure 11, and XOR gate needs a phase inverter and one 2 to select 1 selector switch to realize usually.
One's own department or unit XOR structure of Figure 10 and Figure 11 is compared, can find to select 1 selector switch to lack to use two pipes with door than 2 in Figure 11 in Figure 10, therefore further improved area utilization.
Preferably, as shown in figure 10, by the logical block of enhancement mode LUT5 structure, the carry chain logic (604 and 605) that the cooperation delay is optimized and one's own department or unit generation logic can efficiently realize 2 and add/subtracter.In addition, the improvement that is appreciated that each structure also can be used respectively.
Further, due to/Co[1] and Co[1] anti-phase, as shown in figure 12, the output terminal of 2 carry look ahead chain structures of a binary add subtracter can be connected with the prime carry signal of another binary add subtracter through a phase inverter, to realize more multidigit binary add subtraction.By carry signal, each binary add subtractor stage is linked togather, has extensibility.
In addition, be appreciated that, in other embodiments of the present invention, also can be as shown in figure 13, do not add phase inverter 901 in one's own department or unit XOR structure of one binary add subtracter, add phase inverter 901 in one's own department or unit XOR structure of one binary add subtracter, alternately connect to realize more multidigit binary add subtraction.
Will also be appreciated that the second carry signal that does not have the binary add of 2 carry look ahead chain structures subtracter can directly pass through a binary add subtracter is connected with the prime carry signal of another binary add subtracter, realizes more multidigit binary add subtraction.
Need to prove, in the claim and instructions of this patent, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operational zone, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make the process, method, article or the equipment that comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that " comprises " and limit by statement, and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (5)
1. the binary add subtracter based on enhancement mode look-up table LUT5 structure, comprise LUT5 structure, carry chain structure, first one's own department or unit XOR structure and second one's own department or unit XOR structure, it is characterized in that:
Described LUT5 structure comprises a LUT4 structure and the 2nd LUT4 structure;
the one LUT4 structure comprises that four LUT2 structures and the 1 select 1 selector switch, the 2nd LUT4 structure comprises that four LUT2 structures and the 24 select 1 selector switch, two input ends of described LUT2 structure connect respectively first and second of the first binary number, the described the 1 selects 1 selector switch and the 24 to select each four input ends of 1 selector switch to connect respectively the output terminal of corresponding each four LUT2 structures, the one 4 selects two control ends of 1 selector switch to meet respectively add-subtract control signal and the second binary number first, the 24 selects two control ends of 1 selector switch to connect respectively the second of described add-subtract control signal and the second binary number,
It is 0 o'clock at described add-subtract control signal, first and the primary XOR result of the second binary number of the one LUT4 structure output the first binary number, the deputy XOR result of the second of the 2nd LUT4 structure output the first binary number and the second binary number;
It is 1 o'clock at described add-subtract control signal, the anti-phase result of the primary XOR of first of the one LUT4 structure output the first binary number and the second binary number, the anti-phase result of the second of the 2nd LUT4 structure output the first binary number and the deputy XOR of the second binary number;
Described carry chain structure is configured to receive first and Output rusults and the prime carry signal of second, a LUT4 structure and the 2nd LUT4 structure of the first binary number, and exports the first carry signal and the second carry signal;
Described first one's own department or unit XOR structure is configured to receive the Output rusults of described prime carry signal, a LUT4 structure and exports first one's own department or unit result, and described second one's own department or unit XOR structure is configured to receive the Output rusults of described the first carry signal, the 2nd LUT4 structure and exports second one's own department or unit result.
2. the binary add subtracter based on enhancement mode LUT5 structure according to claim 1, it is characterized in that, described carry chain structure comprises 2 carry look ahead chain structures, and these 2 carry look ahead chain structures comprise and door, tristate inverter, the first phase inverter, the second phase inverter, the first transmission gate, the second transmission gate and the 3rd transmission gate;
The second of input termination first binary number of the first phase inverter, the input end of output termination the first transmission gate, the anti-phase Output rusults of control termination the 2nd LUT4 structure of this first transmission gate;
First of input termination first binary number of the second phase inverter, the input end of output termination the second transmission gate, the Output rusults of control termination the 2nd LUT4 structure of this second transmission gate, the input end of output termination the 3rd transmission gate of this second transmission gate, the anti-phase Output rusults of control termination the one LUT4 structure of the 3rd transmission gate;
Described two input ends with door connect respectively the Output rusults of a LUT4 structure and the 2nd LUT4 structure, the control end of the described tristate inverter of output termination of described and door, the described prime carry signal of the input termination of this tristate inverter;
The output terminal of described the first transmission gate, the 3rd transmission gate and tristate inverter is interconnected to form the anti-phase result of described second carry signal of output terminal output of described 2 carry look ahead chain structures.
3. the binary add subtracter based on enhancement mode LUT5 structure according to claim 1, it is characterized in that, described first one's own department or unit XOR structure comprises the first Sheffer stroke gate, the 3rd phase inverter and the 1 selects 1 selector switch, wherein input the described prime carry signal of termination for one of the first Sheffer stroke gate, another input end is controlled by programmed point FUSE, the input end of output termination the 3rd phase inverter of this first Sheffer stroke gate also selects an input end of 1 selector switch to be connected with the 1, the output terminal and the 1 of the 3rd phase inverter selects another input end of 1 selector switch to be connected, the one 2 selects the Output rusults of control termination the one LUT4 structure of 1 selector switch, it is 0 o'clock at described programmed point FUSE, the one 2 selects the Output rusults of output terminal output the one LUT4 structure of 1 selector switch, it is 1 o'clock at described programmed point FUSE, the one 2 selects output terminal output first one's own department or unit result of 1 selector switch,
described second one's own department or unit XOR structure comprises the second Sheffer stroke gate, the 4th phase inverter and the 22 selects 1 selector switch, wherein input described the first carry signal of termination for one of the second Sheffer stroke gate, another input end is controlled by described programmed point FUSE, the input end of output termination the 4th phase inverter of this second Sheffer stroke gate also selects an input end of 1 selector switch to be connected with the 22, the output terminal and the 22 of the 4th phase inverter selects another input end of 1 selector switch to be connected, the 22 selects the Output rusults of control termination the 2nd LUT4 structure of 1 selector switch, it is 0 o'clock at described programmed point FUSE, the 22 selects the Output rusults of output terminal output the 2nd LUT4 structure of 1 selector switch, it is 1 o'clock at described programmed point FUSE, the 22 selects output terminal output second one's own department or unit result of 1 selector switch.
4. the binary add subtracter based on enhancement mode LUT5 structure according to claim 2, it is characterized in that, the output terminal of described 2 carry look ahead chain structures of one binary add subtracter is connected with the prime carry signal of another binary add subtracter through a phase inverter, to realize more multidigit binary add subtraction.
5. according to claim 1 or 3 described binary add subtracters based on enhancement mode LUT5 structure, it is characterized in that, the second carry signal of one binary add subtracter is connected with the prime carry signal of another binary add subtracter, to realize more multidigit binary add subtraction.
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Cited By (4)
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| US20160246571A1 (en) * | 2013-10-02 | 2016-08-25 | The Penn State Research Foundation | Techniques and devices for performing arithmetic |
| CN107885485A (en) * | 2017-11-08 | 2018-04-06 | 无锡中微亿芯有限公司 | A kind of programmable logic unit structure that quick additions are realized based on carry look ahead |
| CN114461174A (en) * | 2022-04-13 | 2022-05-10 | 深圳云豹智能有限公司 | Lookup table circuit, chip and electronic equipment |
| CN114489563A (en) * | 2021-12-13 | 2022-05-13 | 深圳市紫光同创电子有限公司 | Circuit structure |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160246571A1 (en) * | 2013-10-02 | 2016-08-25 | The Penn State Research Foundation | Techniques and devices for performing arithmetic |
| US9916131B2 (en) * | 2013-10-02 | 2018-03-13 | The Penn State Research Foundation | Techniques and devices for performing arithmetic |
| CN107885485A (en) * | 2017-11-08 | 2018-04-06 | 无锡中微亿芯有限公司 | A kind of programmable logic unit structure that quick additions are realized based on carry look ahead |
| CN107885485B (en) * | 2017-11-08 | 2021-07-06 | 无锡中微亿芯有限公司 | Programmable logic unit structure for realizing rapid addition based on carry look ahead |
| CN114489563A (en) * | 2021-12-13 | 2022-05-13 | 深圳市紫光同创电子有限公司 | Circuit structure |
| CN114489563B (en) * | 2021-12-13 | 2023-08-29 | 深圳市紫光同创电子有限公司 | Circuit structure |
| CN114461174A (en) * | 2022-04-13 | 2022-05-10 | 深圳云豹智能有限公司 | Lookup table circuit, chip and electronic equipment |
| CN114461174B (en) * | 2022-04-13 | 2022-06-07 | 深圳云豹智能有限公司 | Lookup table circuit, chip and electronic equipment |
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| CN103176766B (en) | 2016-06-08 |
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