CN110008075A - A kind of chip adjustment method and device - Google Patents
A kind of chip adjustment method and device Download PDFInfo
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- CN110008075A CN110008075A CN201810010819.4A CN201810010819A CN110008075A CN 110008075 A CN110008075 A CN 110008075A CN 201810010819 A CN201810010819 A CN 201810010819A CN 110008075 A CN110008075 A CN 110008075A
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- debug
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000006243 chemical reaction Methods 0.000 claims description 19
- 230000009471 action Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 7
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Abstract
Disclosing one kind herein, the embodiment of the invention provides a kind of chip adjustment method and devices, comprising: after entering DEBUG mode, receives the address signal of the register of serial input；According to the register address signal, the value of corresponding registers is read；By the value Serial output of the register.The application can debug chip interior whole key signal and register with cost as few as possible.
Description
Technical field
The present invention relates to chip design art fields, and in particular to a kind of chip adjustment method and device.
Background technique
In the related technology, chip is to the DEBUG technology of internal signal, primarily directed to CPU and its accessory module data into
Row DEBUG, such as joint test working group (JTAG, Joint Test Action Group) debugging, TRACE debugging, pass through
Cpu instruction or data directly or after storage are exported again by specifically defined interface, thus reach DEBUG purpose, but
When crashing generation, the method just has certain limitation, can not carry out reading behaviour to key signal in chip and critical registers
Make, and the value of key signal can help to judgement of the commissioning staff to crash reason.
Therefore, how to carry out reading during DEBUG when crashing in chip key signal value and register value for
Commissioning staff checks, is a technical problem to be solved urgently.
Summary of the invention
It in order to solve the above-mentioned technical problem, can be with the embodiment of the invention provides a kind of chip adjustment method and device
Cost debugging chip interior whole key signal as few as possible and register.
The embodiment of the invention provides following technical solutions:
A kind of chip adjustment method, comprising:
After entering DEBUG mode, the address signal of the register of serial input is received；
According to the register address signal, the value of corresponding registers is read；
By the value Serial output of the register.
Wherein, described according to the register address signal, read the value of corresponding registers, comprising: decode the deposit
Device address signal determines module belonging to corresponding registers, and reads the register to module belonging to the register
Value.
Wherein, the method also includes: after the value for reading the register, execute and turn string operation.
Wherein, by DEBUG_ADDR pin predetermined by the value Serial output of the register.
Wherein, the method also includes one of following:
DEBUG_EN pin is set to height, to enter the DEBUG mode；
After the value Serial output of the register, the DEBUG_EN pin is set to it is low, to exit the DEBUG
Mode.
A kind of chip debugging apparatus, comprising:
Decoder module, for receiving the address signal of the register of serial input after entering DEBUG mode, according to
The register address signal, reads the value of corresponding registers；
Output module, for by the value Serial output of the register.
Wherein, further includes: conversion module；The decoder module, the register address specifically for receiving serial input are believed
Number, the register address signal is decoded, determines module belonging to corresponding registers, and into module belonging to the register
Conversion module send read operation instruction；The conversion module is read for receiving the read operation instruction from the decoder module
It takes the value of corresponding registers and the value of the register is carried out and turns string operation.
Wherein, the output module, includes at least: DEBUG_ADDR pin predetermined.
Wherein, further includes: DEBUG_EN pin has entered DEBUG mode for indicating when being set to high.
A kind of chip, comprising:
It is stored with the memory of chip debugging routine；
Processor is configured to execute operation of the chip debugging routine to execute said chip adjustment method.
A kind of computer readable storage medium is stored with chip debugging routine, institute on the computer readable storage medium
State the step of said chip adjustment method is realized when chip debugging routine is executed by processor.
The embodiment of the present invention can realize the purpose of the full chip of DEBUG by simple logic and less pin, i.e., with to the greatest extent
The cost that may lack realizes the purpose of debugging chip interior whole key signal and register, while having also achieved saving pin
Effect, accelerate debugging progress.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the flow diagram of chip of embodiment of the present invention adjustment method；
Fig. 2 is the structural schematic diagram of chip of embodiment of the present invention debugging apparatus；
Fig. 3 is the exemplary structure schematic diagram of chip in the embodiment of the present invention；
Fig. 4 is the functional schematic of decoder module in chip shown in Fig. 3；
Fig. 5 is the functional schematic of conversion module in chip shown in Fig. 3；
Fig. 6 is the exemplary implementation flow chart of chip of embodiment of the present invention adjustment method.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
In current chip design, DEBUG is very important a ring design, is related to the debugging progress of chip, Jin Erying
Ring the listing progress of product.If the execution method of DEBUG is unreasonable, human time's cost of cost is inestimable.Related skill
The similar techniques scheme limitation of art is larger in the related technology, and the debugging of chip is the DEBUG function of being carried using CPU, from
JTAG to TRACE, but these schemes need the biggish module of highly complex and area, it is also desirable to chip design engineer and debugging
The study of engineer's long period understands and application, and when chip crashes, the range that can be debugged is also extremely limited, JTAG tune
Examination does not work even.Therefore, either chip area cost, the human cost of subsequent debugging are all very high.
For the above-mentioned technical problem of the relevant technologies, this application provides the following technical solutions.The technical side of the application
Case can reach the purpose of DEBUG full chip register and key signal by simple logic and less pin.
The implementation of technical scheme is described in detail below.
Embodiment one
As shown in Figure 1, providing a kind of chip adjustment method characterized by comprising
Step 101, after entering DEBUG mode, the address signal of the register of serial input is received；
Step 102, according to the register address signal, the value of corresponding registers is read；
Step 103, by the value Serial output of the register, so that observation device (for example, oscillograph) receives described post
The value of storage is simultaneously shown (for example, value that the register is shown by waveform), so that commissioning staff is observed.
Here, register is the register of pre-debug, and register address signal refers to the address of the register of the pre-debug
Signal.
In the present embodiment, by dedicated two debugging pin, while chip content increases simple logic, and all
The IP module of AMBA bus interface is connected, by the control of enable pin, from the address of pin input observation, module register
Register value can be read by link block, while change into serial data and exporting to pin, can be seen by oscillograph
It surveys.In this way, method through this embodiment still can quickly access internal deposit when chip crashes, CPU can not be accessed
Device grabs the value of key signal, quick positioning failure, to achieve the purpose that the full chip register of DEBUG and key signal.By
This is it is found that the present embodiment can realize the purpose of the full chip of DEBUG by simple logic and less pin, i.e., with as few as possible
Cost realize debugging chip interior whole key signal and register purpose, while have also achieved save pin effect
Fruit accelerates debugging progress.
It is described that the value of corresponding registers is read according to the register address signal in the present embodiment, it may include: solution
The code register address signal determines module belonging to corresponding registers, and reads institute to module belonging to the register
State the value of register.
In the present embodiment, after the method can also include: the value for reading the register, executes and simultaneously turn string behaviour
Make.
In the present embodiment, by DEBUG_ADDR pin predetermined by the value Serial output of the register.
It can also include one of following or two in the present embodiment: 1) DEBUG_EN pin is set to height, described in entrance
DEBUG mode；2) after the value Serial output of the register, the DEBUG_EN pin will be set to it is low, it is described to exit
DEBUG mode.
Embodiment two
A kind of chip debugging apparatus, as shown in Fig. 2, may include:
Decoder module 21, for receiving the address signal of the register of serial input, root after entering DEBUG mode
According to the register address signal, the value of corresponding registers is read；
Output module 22, for by the value Serial output of the register.
In the present embodiment, said chip debugging apparatus can also include: conversion module 23；The decoder module 21, specifically
The register address signal that can be used for receiving serial input decodes the register address signal, determines belonging to corresponding registers
Module, and conversion module into module belonging to the register sends read operation instruction；The conversion module 23, can use
It is instructed in receiving the read operation from the decoder module, read the value of corresponding registers and carries out the value of the register simultaneously
Turn string operation.
In the present embodiment, the output module 22 at least may include: DEBUG_ADDR pin predetermined.Change speech
It, by the DEBUG_ADDR pin predetermined by the value Serial output of the register.
In the present embodiment, above-mentioned apparatus can also include: DEBUG_EN pin, enter for indicating when being set to high
DEBUG mode.In addition, DEBUG_EN pin, it may also be used for when being set to low, instruction has dropped out DEBUG mode.
Other technologies details in the present embodiment is referring to embodiment one.
Embodiment three
A kind of chip, comprising:
It is stored with the memory of chip debugging routine；
Processor is configured to execute behaviour of the chip debugging routine to execute chip adjustment method described in embodiment one
Make.
Other technologies details in the present embodiment is referring to embodiment one.
Example IV
A kind of computer readable storage medium is stored with chip debugging routine, institute on the computer readable storage medium
State when chip debugging routine is executed by processor realize embodiment one described in chip adjustment method the step of.
Other technologies details in the present embodiment is referring to embodiment one.
The example implementations of the various embodiments described above are described in detail below.It should be noted that hereafter each reality
Example can any combination.Also, in practical applications, the various embodiments described above can also have other implementations, in Examples below
Each process, implementation procedure etc. can also be adjusted according to the needs of practical application.
Example 1
As shown in figure 3, being the exemplary structure schematic diagram of a chip.As shown in figure 3, be provided in chip decoder module,
And with module original in chip (module 1 ..., the conversion module that connect one by one of module n).Wherein, as shown in figure 4, decoding
Module is responsible for address decoding, serial address input, module selection and serial mode output, as shown in figure 5, each modulus of conversion
Block is each responsible for that the serial address signals of its link block are switched to AMBA bus reading interface, AMBA bus reading data turn serially
Data-signal.It further include control submodule in conversion module, which is responsible for the timing control of conversion module.Specifically
, control submodule executes corresponding operating according to following timing for controlling conversion module: operation read address, then obtains data,
It is exported again to pin.
As shown in fig. 6, for the exemplary implementation process of chip debugging.
As shown in fig. 6, the exemplary execution process of chip debugging may include:
Step 601, set DEBUG_EN pin as height, indicate that chip is in DEBUG mode, internal conversion module can automatically by
The IP module and original AMBA bus of pre-debug disconnect, and module is made directly to be connected with conversion module；
Step 602, from DEBUG_ADDR pin into chip serial input 32 bit register address signals；
Step 603, decoder module is decoded 32 bit register address signals of serial input, according to register
Location determination will access the register of which module, and the conversion module for selecting the module to connect executes read operation.
In the application, key signal is assigned in register, directly can access and read will pass through register address
The signal value of the key signal.
Step 604, conversion module will read the value of corresponding registers and carry out and turn the operation gone here and there, and will be serial accordingly
Data-signal returns to decoder module；
Step 605, decoder module receives the serial data signal that above-mentioned register returns, by corresponding data, that is, register
Value Serial output to pin, commissioning staff can observe the value of the register by oscillograph.In view of observability, solution
The value of register can be carried out jump output by the coding of certain format by code module, to prevent caused by continuous 0 or continuous 1
Observation is inconvenient, can also be repeated as many times and export.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware (such as processor) is completed, and described program can store in computer readable storage medium, as read-only memory,
Disk or CD etc..Optionally, one or more integrated circuits also can be used in all or part of the steps of above-described embodiment
It realizes.Correspondingly, each module/unit in above-described embodiment can take the form of hardware realization, such as pass through integrated circuit
It realizes its corresponding function, can also be realized in the form of software function module, such as be stored in and deposited by processor execution
Program/instruction in reservoir realizes its corresponding function.The application is not limited to the knot of the hardware and software of any particular form
It closes.
The advantages of basic principles and main features and the application of the application have been shown and described above.The application is not by upper
The limitation for stating embodiment, the above embodiments and description only describe the principles of the application, are not departing from the application
Under the premise of spirit and scope, the application be will also have various changes and improvements, these changes and improvements both fall within claimed
Within the scope of the application.
Claims (11)
1. a kind of chip adjustment method characterized by comprising
After entering DEBUG mode, the address signal of the register of serial input is received；
According to the register address signal, the value of corresponding registers is read；
By the value Serial output of the register.
2. reading is corresponding the method according to claim 1, wherein described according to the register address signal
The value of register, comprising:
The register address signal is decoded, determines module belonging to corresponding registers, and to module belonging to the register
Read the value of the register.
3. method according to claim 1 or 2, which is characterized in that the method also includes:
After the value for reading the register, executes and turn string operation.
4. the method according to claim 1, wherein
By DEBUG_ADDR pin predetermined by the value Serial output of the register.
5. the method according to claim 1, wherein the method also includes one of following:
DEBUG_EN pin is set to height, to enter the DEBUG mode；
After the value Serial output of the register, the DEBUG_EN pin is set to it is low, to exit the DEBUG mould
Formula.
6. a kind of chip debugging apparatus, comprising:
Decoder module, for the address signal of the register of serial input being received, according to described after entering DEBUG mode
Register address signal reads the value of corresponding registers；
Output module, for by the value Serial output of the register.
7. chip debugging apparatus according to claim 6, which is characterized in that further include: conversion module；
The decoder module decodes the register address signal specifically for the register address signal of reception serial input,
Determine module belonging to corresponding registers, and the conversion module into module belonging to the register sends read operation instruction；
The conversion module reads the value of corresponding registers and incites somebody to action for receiving the read operation instruction from the decoder module
The value of the register carries out and turns string operation.
8. chip debugging apparatus according to claim 6, which is characterized in that
The output module, includes at least: DEBUG_ADDR pin predetermined.
9. chip debugging module according to claim 6, which is characterized in that further include:
DEBUG_EN pin has entered DEBUG mode for indicating when being set to high.
10. a kind of chip, comprising:
It is stored with the memory of chip debugging routine；
Processor is configured to execute the chip debugging routine to execute the chip debugging side as described in any one of claim 1 to 5
The operation of method.
11. a kind of computer readable storage medium, which is characterized in that be stored with chip tune on the computer readable storage medium
Program is tried, the chip debugging side as described in any one of claims 1 to 5 is realized when the chip debugging routine is executed by processor
The step of method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810010819.4A CN110008075A (en) | 2018-01-05 | 2018-01-05 | A kind of chip adjustment method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810010819.4A CN110008075A (en) | 2018-01-05 | 2018-01-05 | A kind of chip adjustment method and device |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663922A (en) * | 1994-11-10 | 1997-09-02 | Sgs-Thomson Microelectronics S.A. | Method for the anticipated reading of serial access memory, and memory pertaining thereto |
| CN1269906A (en) * | 1997-12-08 | 2000-10-11 | 爱特梅尔股份有限公司 | Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations |
| US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
| US6154856A (en) * | 1997-04-08 | 2000-11-28 | Advanced Micro Devices, Inc. | Debug interface including state machines for timing synchronization and communication |
| DE10034854A1 (en) * | 2000-07-18 | 2002-02-14 | Infineon Technologies Ag | Method and device for generating digital signal patterns |
| US20020133794A1 (en) * | 2001-02-24 | 2002-09-19 | Ruban Kanapathippillai | Method and apparatus for integrated circuit debugging |
| CN1889066A (en) * | 2006-07-12 | 2007-01-03 | 北京中星微电子有限公司 | Automatic switching device for complexing pin working mode |
| DE102008008709A1 (en) * | 2008-02-11 | 2009-08-13 | Atmel Germany Gmbh | Microcontroller, has computing unit whose address output is connected with parallel input of shift register, where series input and output of shift register are connected with connection of microcontroller and computing unit, respectively |
| CN101593218A (en) * | 2008-05-28 | 2009-12-02 | 中兴通讯股份有限公司 | Chip maintenance method |
| CN101938566A (en) * | 2010-09-10 | 2011-01-05 | 青岛海信移动通信技术股份有限公司 | Visual terminal debugging method and device |
| CN102236066A (en) * | 2010-04-22 | 2011-11-09 | 上海华虹集成电路有限责任公司 | Method for realizing rapid debugging and locating of chip functional fault and debugging circuit |
| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
-
2018
- 2018-01-05 CN CN201810010819.4A patent/CN110008075A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663922A (en) * | 1994-11-10 | 1997-09-02 | Sgs-Thomson Microelectronics S.A. | Method for the anticipated reading of serial access memory, and memory pertaining thereto |
| US6154856A (en) * | 1997-04-08 | 2000-11-28 | Advanced Micro Devices, Inc. | Debug interface including state machines for timing synchronization and communication |
| CN1269906A (en) * | 1997-12-08 | 2000-10-11 | 爱特梅尔股份有限公司 | Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations |
| US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
| DE10034854A1 (en) * | 2000-07-18 | 2002-02-14 | Infineon Technologies Ag | Method and device for generating digital signal patterns |
| US20020133794A1 (en) * | 2001-02-24 | 2002-09-19 | Ruban Kanapathippillai | Method and apparatus for integrated circuit debugging |
| CN1889066A (en) * | 2006-07-12 | 2007-01-03 | 北京中星微电子有限公司 | Automatic switching device for complexing pin working mode |
| DE102008008709A1 (en) * | 2008-02-11 | 2009-08-13 | Atmel Germany Gmbh | Microcontroller, has computing unit whose address output is connected with parallel input of shift register, where series input and output of shift register are connected with connection of microcontroller and computing unit, respectively |
| CN101593218A (en) * | 2008-05-28 | 2009-12-02 | 中兴通讯股份有限公司 | Chip maintenance method |
| CN102236066A (en) * | 2010-04-22 | 2011-11-09 | 上海华虹集成电路有限责任公司 | Method for realizing rapid debugging and locating of chip functional fault and debugging circuit |
| CN101938566A (en) * | 2010-09-10 | 2011-01-05 | 青岛海信移动通信技术股份有限公司 | Visual terminal debugging method and device |
| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
Non-Patent Citations (1)
| Title |
|---|
| 梁廷贵 王裕琛主编: "《计数器 公频器 锁存器 驱动器分册》", pages: 205 - 209 * |
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