CN1481015A - Method for forming contact hole - Google Patents
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- CN1481015A CN1481015A CNA02131862XA CN02131862A CN1481015A CN 1481015 A CN1481015 A CN 1481015A CN A02131862X A CNA02131862X A CN A02131862XA CN 02131862 A CN02131862 A CN 02131862A CN 1481015 A CN1481015 A CN 1481015A
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Abstract
Conduction structures of first, second, third grid electrode are formed on surface of a semiconductor substrate in sequence. There is a cover layer on top part of each grid electrode, and conduction structures of second and third grid are located in an active area. First inner dielectric layer possessing flat surface is formed in order to fill in gap between conduction structures of grid electrode. Patternized photoresist is formed on part surface of inner dielectric layer. Selective etching cover layer of the first grid conduction structure by using patternized photoresist as mask exposes top part of the structure. Flat second inner dielectric layer is formed on whole surface of substrate, and patternized mask layer is formed on surface of second inner dielectric layer. Etching first, second inner dielectric layers by using the said patternized mask layer as etching mask forms first and second contact holes in first and second inner dielectric layer.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly a kind of formation method of contact hole.
Background technology
Memory product now comprises: trench formula DRAM, stacked dram, FLASH memory.It is made, and in order to reach the purpose of dwindling chip size, (selfaligned contact, SAC) technology can define and shorten the spacing of adjacent gate conductive structure effectively can to adopt self-aligned contacts in traditional semiconductor technology.
Figure 1A to Fig. 1 G is the generalized section that shows existing SAC technology.
At first, please refer to Figure 1A, a P type silicon substrate 10 be provided, include: a plurality of shallow-trench isolation (shallow trench isolation, STI) district 12, be used for isolated adjacent active region (active area, AA); A plurality of gate conductive structure 161～163 are formed on gate insulator 14 surfaces, and wherein each gate conductive structure 161～163rd is made of a gate insulator 14, a polysilicon layer 17 and a tungsten silicide 19; A plurality of silicon nitride cover layers 24 are formed at the sidewall and the top of gate conductive structure 161～163 respectively; And a plurality of ion implanted regions 22, be formed at respectively on silicon substrate 10 surfaces of adjacent gate conductive structure 161～163.
Then, please refer to Figure 1B, utilize suitable sedimentation and chemico-mechanical polishing (chemicalmechanical polishing earlier; CMP) technology, formation one has core dielectric material (the inter-layer dielectric of flat surfaces; ILD) layer 26 is in the entire substrate surface, to fill up the gap of adjacent gate conductive structure 161～163.The material of ILD layer 26 can be selected boron phosphorus silicate glass (boro-phsphosilicate glass for use; BPSG), high-density plasma (high density plasma; HDP) silica or tetraethyl orthosilicate (tetraethylorthosilicate; TEOS) or its combined material.Form a mask layer (hard mask) 25 again in ILD layer 26 surface, with in subsequent etch bit line contact hole (contact tobit-line; CB) with grid contact hole (contact to gate; CG) as etching mask, the selection of its material must have 2 considerations the time: one, different with the material (silica) of ILD layer 26.Two, different with the material (silicon nitride) of cover layer 24.Therefore, the material of mask layer 25 for example is a polysilicon (poly-silicon).
Subsequently, please refer to Fig. 1 C, form one earlier and have the first patterning photoresist 28 of bit line contact hole (contact to bit-line) and grid contact hole (contact to gate) pattern in mask layer 25 surfaces.Be mask etching mask layer 25 with the first patterning photoresist 28 again, to form a patterned mask layer 25a.
Then, please refer to Fig. 1 D, with patterned mask layer 25a is mask, implement a suitable etching work procedure, for example: dry etching, simultaneously the ILD layer between gate conductive structure 161 tops and 162,163 26 is removed, form opening 301 and 302, expose silicon nitride cover layer 24 surfaces that are covered on the gate conductive structure 161 and form a bit line contact hole 302 between gate conductive structure 162,163, can expose ion implanted region 22.
Then, please refer to Fig. 1 E, form one second patterning photoresist 32 in mask layer 25a surface and fill up in the bit line contact hole 302, only expose opening 301.
Then, please refer to Fig. 1 F, with the patterned mask layer 25a and the second patterning photoresist 32 is mask, implement a suitable etching work procedure, for example: dry etching, be covered in the cover layer 24 of gate conductive structure 161 tops with removal, form a grid contact hole 301a, can expose tungsten silicide layer 19 surfaces in gate conductive structure 161 tops.
At last, please refer to Fig. 1 G, remove second photoresist 32 after, expose bit line contact hole 302a, just finish the making that grid touches hole 301a and bit line contact hole 302a.
Yet existing contact hole formation method has following point:
1. along with the increase of semiconductor integrated level, the live width of semiconductor element also with dwindle, therefore, if the draw ratio (aspect ratio) of the grid contact hole (CG) that desire forms is too high, then when the development step that desire is removed second photoresist 32 of opening 301 parts, tend to because opening 301 degree of depth are too dark and add the interference of the polysilicon mask layer with high reflectance, make the exposure energy deficiency, can't remove second photoresist 32 in the opening 301 clean, and the residual problem of second photoresist 32 is arranged, cause cover layer 24 difficulties of etching grid conductive structure 161 tops, be unfavorable for the formation of grid contact hole 301a.
2. the formation of bit line contact hole (CB) and grid contact hole (CG), utilize the twice photoresist to carry out etching respectively for mask, so forming the position of first photoresist 28 and second photoresist 32 in photoetching process must be quite accurate, but when the integrated level of semiconductor element increases, the twice photoresist forms if the situation of contraposition inaccurate (mis-alignment) is arranged slightly, will have a strong impact on follow-up component properties.
3. being adopted as of mask layer 25 solves aforementioned photoresist at first and residues in problem in the grid contact hole in the existing technology, change with mask layer 25 and replace the first patterning photoresists 28 and the second patterning photoresist 32 respectively as the mask of etching grid contact hole and bit line grid contact hole, yet, the selection of mask layer 25 materials is limited many, and 2 considerations must be arranged: one, different with the material (silica) of ILD layer 26.Two, different with the material (silicon nitride) of cover layer 24.Therefore, existing technology constitutes mask layer 25 with polysilicon (poly-silicon).Yet in the photoetching process that forms second photoresist 32, because polysilicon is reflective quite strong, the aligning that makes second photoresist 32 be formed on polysilicon mask layer 25 surface is difficult for.
Summary of the invention
Therefore, the technical problem to be solved in the present invention is to provide a kind of formation method of contact hole, can avoid the problems referred to above.
One of purpose of the present invention is to provide a kind of method that forms grid contact hole (CG) and bit line contact hole (CB) simultaneously, takes place to avoid the inaccurate problem of contraposition.
Two of purpose of the present invention is to provide a kind of formation method of contact hole, can select the mask layer of suitable material as the etching contact hole, helps forming the contact hole of high depth ratio.
Three of purpose of the present invention is to provide a kind of formation method of contact hole, can avoid existing photoresist to residue in problem in the grid contact hole.
For realizing above-mentioned purpose, the present invention proposes a kind of formation method of contact hole, and the step of the method mainly comprises:
At first, semi-conductive substrate is provided, its surface is provided with an adjacent in regular turn first grid conductive structure, a second grid conductive structure and one the 3rd gate conductive structure, wherein the top of above-mentioned each gate conductive structure and sidewall all have a material and for example are the cover layer of nitrogen silicon compound, and above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure are positioned at an active region.More comprise a plurality of shallow trench isolation areas in the above-mentioned Semiconductor substrate, be arranged between above-mentioned first grid conductive structure and the above-mentioned second grid conductive structure, in order to define above-mentioned active region.
Then, formation one has the first core dielectric material layer of flat surfaces, space with the space of filling up above-mentioned first grid conductive structure and above-mentioned second grid conductive structure, above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure, wherein forming above-mentioned method with first core dielectric material layer of flat surfaces can comprise: form the above-mentioned second core dielectric material layer earlier in the whole surface of above-mentioned substrate, implement a chemical-mechanical polishing process again, up to exposing above-mentioned cover surface.
Then, form a patterning photoresist, to expose the first core dielectric material layer segment of above-mentioned first grid conductive structure top in the part surface of above-mentioned core dielectric material layer.
Then, be mask with above-mentioned patterning photoresist, the cover layer of the above-mentioned first grid conductive structure of selective etch is to expose the top of above-mentioned first grid conductive structure.
Then, form one and have the second core dielectric material layer of flat surfaces on the whole surface of above-mentioned substrate, with the top of filling up above-mentioned first grid conductive structure and cover above-mentioned first grid conductive structure, above-mentioned second grid conductive structure, above-mentioned the 3rd gate conductive structure and the above-mentioned first core dielectric material layer, wherein forming above-mentioned method with second core dielectric material layer of flat surfaces can comprise: the above-mentioned second core dielectric material layer of comprehensive formation earlier is on the whole surface of above-mentioned substrate, implement a heat treatment step again, make the above-mentioned second core dielectric material layer hot-fluid (flow) and the tool flat surfaces.
Then, form a patterned mask layer in the above-mentioned second core dielectric material laminar surface.
At last, with above-mentioned patterned mask layer is mask, the above-mentioned core dielectric material layer of etching, form one first contact hole and one second contact hole simultaneously in above-mentioned first inner layer dielectric layer and above-mentioned second inner layer dielectric layer, wherein above-mentioned first contact hole exposes the top of above-mentioned first grid conductive structure, and above-mentioned second contact hole exposes substrate surface between above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure.
As previously mentioned, the above-mentioned first core dielectric material layer and the second core dielectric material layer can be made of following at least a material: boron phosphorus silicate glass (boro-phspho silicate glass; BPSG), high-density plasma (high density plasma; HDP) silica or tetraethyl orthosilicate (tetra-ethyl-ortho-silicate; TEOS).Moreover above-mentioned patterned mask layer can be made of following at least a material: SiON, SiN or polysilicon (poly-silicon).
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Figure 1A to Fig. 1 G is the generalized section that shows existing SAC technology; And
Fig. 2 A to Fig. 2 H is the profile that shows contact hole formation technology according to one preferred embodiment of the present invention.
Description of reference numerals in the accompanying drawing is as follows: 10,50 substrates, 12 shallow-trench isolation, 14 gate insulators 7,57 polysilicon layers 19,59 tungsten silicide layers 24,64 cover layers 22,52 ion implanted regions, 26 core dielectric material layers, 28 first patterning photoresist, 25 mask layer 25a patterned mask layer 301,302 openings, 32 patterning photoresist 301a grid contact hole 302a bit line contact hole 301a grids touch hole 66 first core dielectric material layers, 68 first patterning photoresist, 70 second core dielectric material layers, 72 mask layer 72a patterned mask layer, 741 first contact holes 161～163,561～563 gate conductive structure, 742 second contact holes
Embodiment
Below please refer to the process section of Fig. 2 A to Fig. 2 G, illustrate according to a preferred embodiment of the invention.
At first, please refer to Fig. 2 A, semi-conductive substrate 50 is provided, its surface is provided with adjacent in regular turn a first grid conductive structure 561, a second grid conductive structure 562 and one the 3rd gate conductive structure 563, and above-mentioned each gate conductive structure can be made of a gate insulator 54, a polysilicon layer 57 and a tungsten silicide layer 59.The top of wherein above-mentioned each gate conductive structure 561～563 and sidewall all can have a material and for example be the cover layer of nitrogen silicon compound (cap layer) 64, and wherein the nitrogen silicon compound for example is SiON or SiN.And above-mentioned second grid conductive structure 562 is positioned at together active region (AA) with above-mentioned the 3rd gate conductive structure 563, more comprises a plurality of shallow trench isolation areas (shallow trench isolated area in the above-mentioned substrate 50; STI) 52, be arranged between above-mentioned first grid conductive structure 561 and the above-mentioned second grid conductive structure 562, in order to define above-mentioned active region (AA).
Then, please refer to Fig. 2 B, earlier (for example: chemical vapour deposition technique) form the above-mentioned first core dielectric material layer 66, with the space of the space of filling up above-mentioned first grid conductive structure 561 and above-mentioned second grid conductive structure 562, above-mentioned second grid conductive structure 562 and above-mentioned the 3rd gate conductive structure 563 in the whole surface of above-mentioned substrate 50 with suitable deposition procedures.Implement a chemico-mechanical polishing (chemical mechanical polishing again; CMP) operation is up to exposing above-mentioned cover layer 64 surfaces, to form the first core dielectric material layer 66 of a tool flat surfaces.Wherein, the material of the above-mentioned first core dielectric material layer 66 is mainly Si oxide, can be by boron phosphorus silicate glass (boro-phspho silicateglass; BPSG), high-density plasma (high density plasma; HDP) silica or tetraethyl orthosilicate (tetra-ethyl-ortho-silicate; TEOS) a kind of or its combination wherein constitutes.
Then, please refer to Fig. 2 C, form one first patterning photoresist 68, with cover layer 64 and the first core dielectric material layer, 66 part of exposing above-mentioned first grid conductive structure 561 tops in the part surface of the above-mentioned first core dielectric material layer 66.
Then, please refer to Fig. 2 D, is mask with the above-mentioned first patterning photoresist 68, utilizes suitable etching work procedure, for example: with phosphoric acid (H
3PO
4) be the wet etching of etching solution or with N
2Plasma is the dry etching of etching gas, and the cover layer 64 of the above-mentioned first grid conductive structure 561 of selective etch is with tungsten silicide layer 57 tops of exposing above-mentioned first grid conductive structure 561.Etchant is about 10～40 to the selection ratio of nitrogen silicon compound/Si oxide, that is etchant to the etching speed of above-mentioned cover layer 64 much larger than the above-mentioned first core dielectric material layer 66, therefore above-mentioned cover layer 64 can be etched and be kept the above-mentioned first core dielectric material layer 66.
Then, please refer to Fig. 2 E, form earlier one second core dielectric material layer 70 on the whole surface of above-mentioned substrate, with the top of filling up above-mentioned first grid conductive structure 561 and cover above-mentioned first grid conductive structure 561, above-mentioned second grid conductive structure 562, above-mentioned the 3rd gate conductive structure 563 and the above-mentioned first core dielectric material layer 66.The material of the above-mentioned second core dielectric material layer 70 is mainly Si oxide, can be by boron phosphorus silicate glass (boro-phspho silicate glass; BPSG), high-density plasma (high density plasma; HDP) silica or tetraethyl orthosilicate (tetra-ethyl-ortho-silicate; TEOS) a kind of or its combination wherein constitutes.Then, implement a rapid thermal treatment (rapid thermal anneal again; RTA) operation, its temperature are about 900～1000 ℃, serve as preferred with 950～970 ℃ wherein, make the above-mentioned second core dielectric material layer, 70 hot-fluid (flow) and have smooth surface.
Then, please refer to Fig. 2 F, (for example: chemical vapour deposition technique) form a mask layer 72 in the above-mentioned second core dielectric material layer 70 surface, wherein the material of aforementioned mask layer 72 for example is SiON, SiN or polysilicon (poly-silicon) to utilize suitable sedimentation.
Then, please refer to Fig. 2 G, form a patterning photoresist (not shown) earlier in aforementioned mask layer 72 surface, be mask etching aforementioned mask layer 72 with above-mentioned patterning photoresist, to form a patterned mask layer 72a, expose the second core dielectric material layer, 70 surface of top between above-mentioned first grid conductive structure 561 tops and above-mentioned second grid conductive structure 562, above-mentioned the 3rd gate conductive structure 563 in the above-mentioned second core dielectric material layer 70 surface.
At last, please refer to Fig. 2 H, is mask with above-mentioned pattern mask 72a layer, for example with C
5F
8Or C
4F
8Be etchant, the above-mentioned first core dielectric material layer 70 and the above-mentioned second core dielectric material layer 66 of etching forms one first contact hole 741 and one second contact hole 742 simultaneously in above-mentioned first inner layer dielectric layer 70 and above-mentioned second inner layer dielectric layer 66.Wherein, above-mentioned first contact hole 741 exposes the top of above-mentioned first grid conductive structure, is so-called grid contact hole (CG).And above-mentioned second contact hole 742 exposes substrate surface between above-mentioned second grid conductive structure 562 and above-mentioned the 3rd gate conductive structure 563, is so-called bit line contact hole (CB).
Comprehensively above-mentioned, the present invention has following advantage:
1. according to contact hole formation method of the present invention, can form grid contact hole (CG) 741 and bit line contact hole (CB) 742 simultaneously, need not cover as the bit line contact hole that many one photoresists of existing process using will form earlier, etch the grid contact hole again, therefore, the present invention can avoid existing photoresist to residue in the problem of grid contact hole.
2. selecting to consider to be must the material different with Si oxide according to mask layer material according to the present invention, for example is SiON, SiN or polysilicon (poly-silicon).Therefore, compare in existing technology, mask layer material of the present invention is selected more.And if select SiON as mask layer, then SiON also can play the part of anti-reflecting layer (anti-reflection layer simultaneously; ARC) role.Moreover, use the material of polysilicon if abandon as mask layer, then can avoid existing polysilicon mask layer to take place because of the problem that reflective mistake causes dislocation to aim at (misalignment) in the photoetching process that forms photoresist by force.
Though the present invention with preferred embodiment openly as above; but it is not in order to limiting scope of the present invention, and those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be looked being as the criterion that claims define.
Claims (18)
1. the formation method of a contact hole comprises:
Semi-conductive substrate is provided, its surface is provided with an adjacent in regular turn first grid conductive structure, a second grid conductive structure and one the 3rd gate conductive structure, wherein the top of above-mentioned each gate conductive structure all has a cover layer, and above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure are positioned at an active region;
Form one first core dielectric material layer, with the space of the space of filling up above-mentioned first grid conductive structure and above-mentioned second grid conductive structure, above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure;
Form a patterning photoresist in the part surface of above-mentioned core dielectric material layer, to expose the cover layer of above-mentioned first grid conductive structure top;
With above-mentioned patterning photoresist is mask, and the cover layer of the above-mentioned first grid conductive structure of selective etch is to expose the top of above-mentioned first grid conductive structure;
Form one second core dielectric material layer on the whole surface of above-mentioned substrate, with the top of filling up above-mentioned first grid conductive structure and cover above-mentioned first, second and the 3rd gate conductive structure and the above-mentioned first core dielectric material layer;
Form one and have the patterned mask layer of one first opening and one second opening in the above-mentioned second core dielectric material laminar surface, wherein above-mentioned first opening is corresponding to the top of above-mentioned first grid conductive structure, and above-mentioned second opening is corresponding to the top, space of above-mentioned first and second gate conductive structure; And
With above-mentioned patterned mask layer is mask, the above-mentioned core dielectric material layer of etching, form one first contact hole and one second contact hole simultaneously in above-mentioned first inner layer dielectric layer and above-mentioned second inner layer dielectric layer, wherein above-mentioned first contact hole exposes the top of above-mentioned first grid conductive structure, and above-mentioned second contact hole exposes substrate surface between above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure.
2. the formation method of contact hole as claimed in claim 1, wherein above-mentioned cover layer is made of the nitrogen silicon compound.
3. the formation method of contact hole as claimed in claim 1 wherein is formed with a spaced walls on the sidewall of each gate conductive structure.
4. the formation method of contact hole as claimed in claim 3, wherein above-mentioned spaced walls is made of the nitrogen silicon compound.
5. the formation method of contact hole as claimed in claim 1, the wherein above-mentioned first core dielectric material layer is made of following at least a material: boron phosphorus silicate glass, high-density plasma silica or tetraethyl orthosilicate.
6. the formation method of contact hole as claimed in claim 1, the wherein above-mentioned second core dielectric material layer is made of following at least a material: boron phosphorus silicate glass, high-density plasma silica or tetraethyl orthosilicate.
7. the formation method of contact hole as claimed in claim 1 wherein forms above-mentioned method with first core dielectric material layer of flat surfaces and comprises:
Form the above-mentioned second core dielectric material layer in the whole surface of above-mentioned substrate, with the space of the space of filling up above-mentioned first grid conductive structure and above-mentioned second grid conductive structure, above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure; And
Implement a chemical-mechanical polishing process, up to exposing above-mentioned cover surface.
8. the formation method of contact hole as claimed in claim 1 wherein forms above-mentioned method with second core dielectric material layer of flat surfaces and comprises:
The above-mentioned second core dielectric material layer of comprehensive formation is on the whole surface of above-mentioned substrate, to fill up above-mentioned first grid conductive structure top and to cover above-mentioned first grid conductive structure, above-mentioned second grid conductive structure, above-mentioned the 3rd gate conductive structure and the above-mentioned first core dielectric material layer; And
Implement a heat treatment step, make the above-mentioned second core dielectric material layer hot-fluid and the tool flat surfaces.
9. the formation method of contact hole as claimed in claim 1, wherein above-mentioned patterned mask layer is made of following at least a material: SiON, SiN or polysilicon.
10. the formation method of contact hole as claimed in claim 1 also comprises a plurality of shallow trench isolation areas in the wherein above-mentioned Semiconductor substrate, is arranged between above-mentioned first grid conductive structure and the above-mentioned second grid conductive structure, in order to define above-mentioned active region.
11. the formation method of a contact hole comprises:
Semi-conductive substrate is provided, its surface is provided with an adjacent in regular turn first grid conductive structure, a second grid conductive structure and one the 3rd gate conductive structure, wherein the top of above-mentioned each gate conductive structure all have a cover layer and above-mentioned each gate conductive structure around all have a spaced walls, and above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure are positioned at an active region;
Form the whole surface of one first core dielectric material layer in above-mentioned substrate, with the space of filling up above-mentioned first and second gate conductive structure, above-mentioned second with the space of above-mentioned the 3rd gate conductive structure;
Implement a chemical-mechanical polishing process, up to exposing above-mentioned cover surface;
Form a patterning photoresist in the part surface of above-mentioned core dielectric material layer, to expose the cover layer of above-mentioned first grid conductive structure top;
With above-mentioned patterning photoresist is mask, and the cover layer of the above-mentioned first grid conductive structure of selective etch is to expose the top of above-mentioned first grid conductive structure;
Form one second core dielectric material layer on the whole surface of above-mentioned substrate, with the top of filling up above-mentioned first grid conductive structure and cover above-mentioned first grid conductive structure, above-mentioned second grid conductive structure, above-mentioned the 3rd gate conductive structure and the above-mentioned first core dielectric material layer;
Implement a heat treatment step, make the above-mentioned second core dielectric material layer hot-fluid and the tool flat surfaces;
Form one and have the patterned mask layer of one first opening and one second opening in the above-mentioned second core dielectric material laminar surface, wherein above-mentioned first opening is corresponding to the top of above-mentioned first grid conductive structure, and above-mentioned second opening is corresponding to the top, space of above-mentioned first and second gate conductive structure; And
With above-mentioned patterned mask layer is mask, above-mentioned first inner layer dielectric layer of etching and above-mentioned second inner layer dielectric layer, form one first contact hole and one second contact hole simultaneously in above-mentioned first inner layer dielectric layer and above-mentioned second inner layer dielectric layer, wherein above-mentioned first contact hole exposes the top of above-mentioned first grid conductive structure, and above-mentioned second contact hole exposes substrate surface between above-mentioned second grid conductive structure and above-mentioned the 3rd gate conductive structure.
12. the formation method of contact hole as claimed in claim 11, wherein above-mentioned cover layer is made of the nitrogen silicon compound.
13. the formation method of contact hole as claimed in claim 11 wherein is formed with a spaced walls on the sidewall of each gate conductive structure.
14. the formation method of contact hole as claimed in claim 13, wherein above-mentioned spaced walls is made of the nitrogen silicon compound.
15. the formation method of contact hole as claimed in claim 11, the wherein above-mentioned first core dielectric material layer is made of following at least a material: boron phosphorus silicate glass, high-density plasma silica or tetraethyl orthosilicate.
16. the formation method of contact hole as claimed in claim 11, the wherein above-mentioned second core dielectric material layer is made of following at least a material: boron phosphorus silicate glass, high-density plasma silica or tetraethyl orthosilicate.
17. the formation method of contact hole as claimed in claim 11, wherein above-mentioned patterned mask layer is made of following at least a material: SiON, SiN or polysilicon.
18. the formation method of contact hole as claimed in claim 11 also comprises a plurality of shallow trench isolation areas in the wherein above-mentioned Semiconductor substrate, is arranged between above-mentioned first grid conductive structure and the above-mentioned second grid conductive structure, in order to define above-mentioned active region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA02131862XA CN1481015A (en) | 2002-09-06 | 2002-09-06 | Method for forming contact hole |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA02131862XA CN1481015A (en) | 2002-09-06 | 2002-09-06 | Method for forming contact hole |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107533980A (en) * | 2015-05-01 | 2018-01-02 | 株式会社佛罗迪亚 | The manufacture method of memory cell, conductor integrated circuit device and conductor integrated circuit device |
| CN110767627A (en) * | 2018-07-27 | 2020-02-07 | 联华电子股份有限公司 | Semiconductor device and manufacturing process thereof |
-
2002
- 2002-09-06 CN CNA02131862XA patent/CN1481015A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107533980A (en) * | 2015-05-01 | 2018-01-02 | 株式会社佛罗迪亚 | The manufacture method of memory cell, conductor integrated circuit device and conductor integrated circuit device |
| US10276727B2 (en) | 2015-05-01 | 2019-04-30 | Floadia Corporation | Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device |
| CN110767627A (en) * | 2018-07-27 | 2020-02-07 | 联华电子股份有限公司 | Semiconductor device and manufacturing process thereof |
| US11145546B2 (en) | 2018-07-27 | 2021-10-12 | United Microelectronics Corp. | Method of forming semiconductor device |
| CN110767627B (en) * | 2018-07-27 | 2022-03-22 | 联华电子股份有限公司 | Semiconductor device and manufacturing process thereof |
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