CN1450640A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1450640A
CN1450640A CN 03109521 CN03109521A CN1450640A CN 1450640 A CN1450640 A CN 1450640A CN 03109521 CN03109521 CN 03109521 CN 03109521 A CN03109521 A CN 03109521A CN 1450640 A CN1450640 A CN 1450640A
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CN
China
Prior art keywords
lid
terminal
semiconductor device
projection
groove
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Granted
Application number
CN 03109521
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Chinese (zh)
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CN100338771C (en
Inventor
石川勝美
伊君高志
豊田瑛一
岡松茂俊
黑须俊树
森睦宏
齋藤隆一
関根茂树
加藤修治
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Hitachi Power Semiconductor Device Ltd
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Hitachi Ltd
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Publication of CN1450640A publication Critical patent/CN1450640A/en
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Publication of CN100338771C publication Critical patent/CN100338771C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Inverter Devices (AREA)

Abstract

In a semiconductor device containing semiconductor elements, insulating caps for covering semiconductor, and at least first and second conduct terminals electrically connected to semiconductor elements, the first conduct terminal has a first terminal project extruding from a first surface and including a first terminate end and a first root end, a second conduct terminal has a second terminal project extruding from a second surface and including a second terminate end and a second root end, cap has at least one of cap project and cap groove in cross section obtained from imaginary plane being parallel with extruding direction, the cap project extrudes to height higher than that of the first and second terminate end, bottom of the cap groove is depressed relative to the first and second surface of the cap.

Description

Semiconductor device
Technical field
The present invention relates to a kind of semiconductor device, it comprises semiconductor element, covers semi-conductive electric insulation lid, and at least the first and second conducting terminals that are electrically connected to semiconductor element respectively.
Background technology
JP-A-61-263144 discloses a kind of semiconductor device, and wherein conducting terminal is surrounded by electric insulation wall part ground.JP-U-2-36281 discloses a kind of semiconductor device, and wherein projection arrangements is between conducting terminal.JP-A-1-144662 discloses a kind of semiconductor device, and wherein groove arrangement is between conducting terminal.JP-A-10-84078 discloses a kind of semiconductor device, and its protrusions and groove arrangement are between conducting terminal.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device, it comprises semiconductor element, cover semi-conductive electric insulation lid, and at least the first and second conducting terminals that are electrically connected to semiconductor element respectively, in this device, between the conducting terminal and/or the electrical insulation capability between the grounded part that is mounted thereon of at least one conducting terminal and device improved.
Comprising semiconductor element, cover semi-conductive electric insulation lid, and be electrically connected to respectively in the semiconductor device of at least the first and second conducting terminals of semiconductor element, because first conducting terminal has the first terminal projection, it is outstanding and comprise first clearing end and the first root end (root end) along first surface at projected direction from the first surface of lid, second conducting terminal has the second terminal projection, it is outstanding and comprise second clearing end and the second root end along second surface at projected direction from the second surface of lid, and along by first and second terminals projectioies and be parallel in the semiconductor device cross-sectional view that imaginary plane that projected direction extends obtains, lid has in lid projection and the lid groove at least one, the lid projection is projected into the height that is higher than the first and second clearing end height with respect to first and second surfaces of lid on projected direction, cave on projected direction with respect to first and second surfaces of lid in the bottom of lid groove, in lid projection and the lid groove this at least one increase between terminal and/or isolation creepage distance of the electricity between the surface electrical ground and/or spatial separation distance that at least one terminal and device are mounted thereon, make the electrical insulation capability of device sufficiently to keep, though between the terminal and/or at least one terminal and electrical ground the distance between the surface reduce.
Preferably, in order to keep at least one terminal and the creepage distance (creepage distance) of the isolation of the electricity between the surface electrical ground, the bottom that peripheral wall by lid prevents to cover groove extends at least one clearing end of lid, as finding on projected direction, just, groove stops in the radius of the peripheral wall of lid, as finding on projected direction.Preferably, isolate creepage distance in order to keep the electricity between the terminal, at least one is arranged in cross-sectional view between first and second conducting terminals in lid projection and the lid groove.
Preferably, make the distance between the terminal minimum when keeping electricity between the terminal to isolate creepage distance, extend along common plane the side of the side of lid groove and lid projection.The electric insulation lid can comprise that electrical insulation synthetic resin is as its main component.
When first and second clearing ends can contact each conductive component that is electrically connected to semiconductor element, preferably, the lid projection had been projected into the height that is higher than conductive component height on first and second clearing ends with respect to first and second surfaces of lid on the projected direction.Preferably, extend along imaginary plane on first and second surfaces of lid, and perhaps Gai first and surface extends parallel to each other.
Preferably, for increase between the terminal and/or at least one terminal and electrical ground the electricity between the surface isolate creepage distance and/or spatial separation distance, the lid projection is changing to the protruding clearing end direction of lid on first and second surfaces from lid perpendicular to the thickness on the thickness direction of projected direction, and the variation of lid projection thickness comprises covers the increase of projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, and the minimizing of lid projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, make and isolate the creepage distance increase along the electricity of lid projection.Preferably, for easy manufacturing installation when lid projection and lid groove are adjacent one another are on thickness direction, cover protruding only performance and cover the minimizing of projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, wherein clearing end is positioned at and covers first side of crowning to the lid groove, and minimizing and the increase of projection thickness on from first and second surfaces of lid to the clearing end direction of lid projection cover in lid projection performance, wherein clearing end be positioned at lid protruding on thickness direction with the first side second side surface opposite.
Preferably, at least one is not less than between first and second conducting terminals perpendicular to the minimum range on the direction of projected direction at the outstanding height of projected direction from first and second surfaces of lid for lid projection.Preferably, the height that lid projection is outstanding is not more than three times of minimum range between first and second conducting terminals.
Preferably, in order to improve as the electrical insulation capability on being seen both direction at least on the projected direction, in another cross-sectional view of semiconductor device that obtains along another imaginary plane, wherein this another imaginary plane is perpendicular to parallel with projected direction and extend by one imaginary plane in the first and second terminal projectioies, the lid groove extends in such a way, make and to cover groove arrangement in respect to the first and second terminal projectioies at least one face of one, perhaps preferably, in order to improve as the electrical insulation capability on being seen at least three directions on the projected direction, the lid groove extends in such a way, make in another cross-sectional view of semiconductor device that obtains along another imaginary plane, wherein this another imaginary plane is perpendicular to parallel with projected direction and extend by the imaginary plane of each in the first and second terminal projectioies, and the lid groove arrangement is on each face with respect to each terminal projection.Preferably, in order to keep at least one terminal and the creepage distance of the isolation of the electricity between the surface electrical ground, the bottom that peripheral wall by lid prevents to cover groove extends at least one clearing end of lid, as in the projected direction finding, just, groove stops in the radius of peripheral wall of lid, as in the projected direction finding.
Preferably, for the electricity that increases between the terminal is isolated creepage distance and/or spatial separation distance, lid projection and lid groove are arranged in cross-sectional view between first and second conducting terminals.Preferably, for increase between the terminal effectively and/or at least one terminal and electrical ground the electricity between the surface isolate creepage distance and/or spatial separation distance, the width of lid groove is not less than 2mm.
Other purpose of the present invention, feature and advantage will become clear from the description below in conjunction with the embodiment of the present invention of accompanying drawing.
Description of drawings
Fig. 1 is the top view as the semiconductor device of first embodiment of the invention.
Fig. 2 is imaginary plane A-A and the first embodiment cross-sectional view that obtains in Fig. 1.
Fig. 3 is the schematic diagram that display set is formed in the circuit in the semiconductor device.
Fig. 4 is the cross-sectional view as the semiconductor device of second embodiment of the invention.
Fig. 5 is the second embodiment guide wire of alternative shape.
Fig. 6 is the top view as the semiconductor device of third embodiment of the invention.
Fig. 7 is imaginary plane B-B and the 3rd embodiment cross-sectional view that obtains in Fig. 6.
Fig. 8 is imaginary plane C-C and the 3rd embodiment cross-sectional view that obtains in Fig. 6.
Fig. 9 is the schematic diagram that display set is formed in the circuit in the 3rd embodiment.
Figure 10 is the top view as the semiconductor device of four embodiment of the invention.
Figure 11 is imaginary plane D-D and the 4th embodiment cross-sectional view that obtains in Figure 10.
Figure 12 is imaginary plane E-E and the 4th embodiment cross-sectional view that obtains in Figure 10.
Figure 13 is the cross-sectional view as the semiconductor device of fifth embodiment of the invention.
Figure 14 is the top view as the semiconductor device of sixth embodiment of the invention.
Figure 15 is the schematic diagram that display set is formed in the circuit in the 6th embodiment.
Embodiment
(embodiment 1)
In semiconductor device as shown in fig. 1, by copper, copper alloy (for example copper-molybdenum alloy or copper-cuprous oxide alloy), the bottom metal substrate 25 that aluminum/silicon carbide or molybdenum are made is arranged in the bottom of device, and power semiconductor 291-294 is fixed by welding to the Al that is installed on the bottom metal substrate 2O 3Or on the electrical insulating board 281 and 282 of AlN, and be electrically connected to distribution on electrical insulating board 281 and 282 by welding.Alternating current terminal 21, direct current is (P) terminal 22 just, negative (N) terminal 23 of direct current and internal control terminal 271-274 are electrically connected to control circuit substrate 26 on it by welding, are fixed on the terminal board of being made by electrical insulation synthetic resin 31 by the thermoset epoxy resin.Terminal board 31 have plane 13 and from the plane 13 outstanding terminal table top 141-143, and alternating current terminal 21, direct current is (P) terminal 22 just, the part of negative (N) terminal 23 of direct current is outstanding from its end face.Alternating current terminal 21, direct current is (P) terminal 22 just, negative (N) terminal 23 of direct current and internal control terminal 271-274 are electrically connected and are fixed to the distribution on electrical insulating board 281 and 282 by welding, electrical insulating board 281 and 282 is electrically connected to power semiconductor 291-294 respectively.Electric insulation resin shell 30 is installed on the bottom metal substrate 25, to surround the combination of terminal board 31 and electrical insulating board 281 and 282, and fill with the thermoset epoxy resin between bottom metal substrate 25 and the resin enclosure 30 and gap between terminal board 31 and the resin enclosure 30, so that they are together fixed to one another.By resin enclosure 30, terminal board 31 and bottom metal substrate 25 limit, and the alternating current terminal 21 that removal apparatus comprised, direct current is (P) terminal 22 just, direct current is born (N) terminal 23, fill in such a way with silicone gel in the space of residual volume outside control circuit substrate 26 and the internal control terminal 271-274, make alternating current terminal 21 in the device, direct current is (P) terminal 22 and negative (N) terminal 23 of direct current just, and control circuit substrate 26 and internal control terminal 271-274 are covered with the electrical insulation capability in the modifying device by silicone gel.After fill with silicone gel in the space, be used on the terminal board 31 silicone gel is clogged with the silicones rubber cap by the opening that it joins device.Resin enclosure 30 and terminal board 31 form the electric insulation lid of power semiconductor 291-294.
As shown in Figure 2, lid projection 111 and cover groove 121 and be arranged in alternating current terminal 21 and direct current just between (P) terminal 22, lid projection 112 and lid groove 122 are arranged in direct current, and just (P) terminal 22 and direct current are born between (N) terminal 23, and extend along common plane the side of lid adjacent one another are projection and lid groove, makes lid projection adjacent one another are and the distance between the lid groove reach minimum.The electricity that lid projection 113 is used between negative (N) terminal 23 of direct current and the external control terminal 24 is isolated, and the electricity that lid groove 123 is used between alternating current terminal 21 and the device outside is isolated.
The height that covers protruding 111-113 is greater than alternating current terminal 21, and direct current is the height of (P) terminal 22 and negative (N) terminal 23 of direct current just.The bottom of lid groove 121-123 is lower than end face and the alternating current terminal 21 of the terminal table top 141-143 of terminal board 31, and direct current just (P) terminal 22 and direct current is born interface between (N) terminal 23.The width of each lid groove 121-123 should be not less than 2mm.
As shown in Figure 3, IGBT 411 is formed by electricity IGBT power semiconductor 291 and 292 in parallel, and IGBT 412 is formed by electricity IGBT power semiconductor 293 and 294 in parallel.The external control terminal 24 of fastening structure is electrically connected to upper arm grid control terminal 43, upper arm emitter control terminal 44, underarm grid control terminal 46 and underarm emitter control terminal 47.The external control terminal 24 of fastening structure can be electrically connected to upper arm collector electrode control terminal and underarm collector electrode control terminal respectively.Lid projection and/or lid groove can form between external control terminal 24 adjacent one another are.The external control terminal 24 of fastening structure can be directly electrically connected to internal control terminal 271-274 and not have control circuit substrate 26 therebetween.
(embodiment 2)
As shown in Figures 4 and 5, cover protruding 111-113 and can have separately protuberance 151-153, protuberance 151-153 extends on the direction perpendicular to the protruding 111-113 projected direction of lid.Protuberance 151-153 can be by adhesive attachment in the protruding 111-113 of lid.The height that covers protruding 111-113 is greater than enough being screwed into alternating current terminal 21, and direct current is the screw 581 in (P) terminal 22 and negative (N) terminal 23 of direct current and 582 height just.
(embodiment 3)
As Fig. 6, in the semiconductor device shown in 7 and 8, by copper, copper alloy (for example copper-molybdenum alloy or copper-cupric oxide alloy), the bottom metal substrate 25 that aluminum/silicon carbide or molybdenum are made is arranged in the bottom of device, and power semiconductor 29 is fixed by welding to the Al that is installed on the bottom metal substrate 2O 3Or on the electrical insulating board 28 of AlN, and be electrically connected to distribution on the electrical insulating board 28 by welding.The internal control terminal 27 of leads ends plate structure and external control terminal 16 are electrically connected by welding and are fixed to control circuit substrate 26, and wherein control circuit substrate 26 usefulness thermoset epoxy resins are installed on the terminal board 31.Alternating current terminal 21, direct current be (P) terminal 22 just, and negative (N) terminal 23 of direct current and internal control terminal 271-274 are electrically connected and are fixed to the distribution on the electrical insulating board 28 by welding, and wherein electrical insulating board 28 is electrically connected to power semiconductor 29 respectively.Resin enclosure 30 is installed on the bottom metal substrate 25, to surround the combination of terminal board 31 and electrical insulating board 281 and 282, and fill with the thermoset epoxy resin between bottom metal substrate 25 and the resin enclosure 30 and gap between terminal board 31 and the resin enclosure 30, so that they are together fixed to one another.By resin enclosure 30, terminal board 31 and bottom metal substrate 25 limit, and the alternating current terminal 21 that removal apparatus comprised, direct current is (P) terminal 22 just, direct current is born (N) terminal 23, fill in such a way with silicone gel in the space of residual volume outside control circuit substrate 26 and the internal control terminal 27, make alternating current terminal 21 in the device, direct current is (P) terminal 22 and negative (N) terminal 23 of direct current just, and control circuit substrate 26 and internal control terminal 27 are covered with the electrical insulation capability in the modifying device by silicone gel.After fill with silicone gel in the space, be used on the terminal board 31 silicone gel is clogged by opening 321 and the 322 usefulness silicones rubber caps that it joins device.Resin enclosure 30 and terminal board 31 form the electric insulation lid of power semiconductor 29.
As shown in Fig. 7 and 8, lid projection 111 and cover groove 121 and be arranged in alternating current terminal 21 and direct current just between (P) terminal 22, lid projection 112 and lid groove 122 are arranged in direct current, and just (P) terminal 22 and direct current are born between (N) terminal 23, and extend along common plane the side of lid adjacent one another are projection and lid groove, makes lid projection adjacent one another are and the distance between the lid groove reach minimum.The electricity that lid projection 113 is used between control terminal 161-169 and negative (N) terminal 231-233 of direct current is isolated.
The height that covers protruding 111-113 is greater than alternating current terminal 21, and direct current is the height of (P) terminal 22 and negative (N) terminal 23 of direct current just, and screw is screwed into alternating current terminal 21 fully, and direct current is just in (P) terminal 22 and negative (N) terminal 23 of direct current.The bottom of lid groove 121-123 is lower than end face and the alternating current terminal 21 of the terminal table top 141-143 of terminal board 31, and direct current just (P) terminal 22 and direct current is born interface between (N) terminal 23.The width of each lid groove 121-123 should be not less than 2mm.
As shown in Figure 9, each combination of IGBT 411-416 and free-wheel diode 421-426 is formed by electricity IGBT power semiconductor 29 in parallel.The external control terminal 131-139 of socket lock construction is electrically connected to upper arm grid control terminal 43 (431 in each excites mutually, 432 or 433), upper arm emitter control terminal 44 (441,442 or 443), upper arm collector electrode control terminal 45 (451,452 or 453), underarm grid control terminal 46 (461,462 or 463), underarm emitter control terminal 47 (461,462 or 463) and underarm collector electrode control terminal 48 (481,482 or 483).Each covers protruding 171-178 and is arranged between the control terminal 161-169 adjacent one another are.As shown in Figure 6, each covers protruding 111-113 can have protuberance 18 with the electric terminal 21 of increasing exchanges, and direct current is the electric insulation creepage distance between negative (N) terminal 23 of (P) terminal 22 and direct current just.External control terminal 161-169 can be directly electrically connected to internal control terminal 27, and does not have control circuit substrate 26 therebetween.
As shown in Figure 5, the height Y of lid projection is not less than the minimum range X between the terminal adjacent one another are, keeping electric insulation therebetween, and is not more than three times of minimum range X, so that another conductive component is installed to each terminal.
(embodiment 4)
As shown in Figure 10-12, cover protruding 111-115 and lid groove 121-123 and can be arranged between the alternating current terminal 211-213 adjacent one another are and between the direct current terminal 221-223 and 231-233 adjacent one another are.
(embodiment 5)
As shown in Figure 13, be installed on the fin by lubricating grease as the anti-phase type power module of the two-stage of semiconductor device the 5th embodiment of the present invention 53.In power module 53, just negative (N) terminal 23 of (P) terminal 22 and direct current is along straight imaginary line for direct current, and main circuit distribution 561 and 562 forms respectively, and just (P) terminal 22 and negative (N) terminal 23 of direct current are parallel to the bus of lid projection 111 and 112 upwardly extending 1mm thickness from direct current.At least one can use epoxy coating in the main circuit distribution 561 and 562, when main circuit distribution 561 and 562 and direct current when just the insulating space between negative (N) terminal 23 of (P) terminal 22 and direct current is apart from deficiency. Main circuit distribution 561 and 562 is electrically connected to capacitor 52.Alternating current terminal 21 is electrically connected to the AC motor by motor distribution 57.Screw 581-583 is screwed into respectively among the terminal 21-23, and with conductive component, for example main circuit distribution 561 and 562 is fixed on the terminal 21-23.Gate wirings 55 is extended from the leads ends template external control terminal 24 with soft lock mechanism.
(embodiment 6)
As shown in Figure 14 and 15, three grades of inverters as semiconductor device the 5th embodiment of the present invention comprise two capacitors 521 and 522, two capacitors 521 and 522 electricity are connected in series to DC power supply, make to obtain three output voltage levels, to form high voltage and high power inverter.The main circuit of three grades of inverters comprises two power modules 531 and 532, diode (led) module 59 and two capacitors.Power module 531 and 532 and diode (led) module 59 be installed on the fin by lubricating grease.Gate wirings 55 extends to the leads ends template external control terminal 16 with soft lock mechanism from gate drivers 54.At least one can be with thermoset epoxy resin coating among the main circuit distribution 561-569, to keep just insulating space distance and the electricity isolation creepage distance between (P) terminal 22 and negative (N) terminal 23 of direct current of main circuit distribution and direct current.
Though those skilled in the art should further be recognized that the description of front based on embodiment of the present invention, the present invention is not limited thereto, can not deviate from the scope of spirit of the present invention and accessory claim book and make various changes and correction.

Claims (18)

1. semiconductor device, comprise semiconductor element (29,291-294,411-416,421-426), cover semi-conductive electric insulation lid (30,31), and be electrically connected to semiconductor element (29 respectively, 291-294,411-416, at least the first and second conducting terminals (21-23) 421-426), it is characterized in that
First conducting terminal has the first terminal projection, it is outstanding and comprise first clearing end and the first root end along first surface at projected direction from the first surface of lid, second conducting terminal has the second terminal projection, it is outstanding and comprise second clearing end and the second root end along second surface at projected direction from the second surface of lid, and along by first and second terminals projectioies and be parallel in the semiconductor device cross-sectional view that imaginary plane that projected direction extends obtains, lid has in lid projection (111-115) and the lid groove (121-123) at least one, the lid projection is projected into the height that is higher than the first and second clearing end height with respect to first and second surfaces of lid on projected direction, cave on projected direction with respect to first and second surfaces of lid in the bottom of lid groove.
2. according to the semiconductor device of claim 1, the bottom that it is characterized in that preventing covering groove extends at least one clearing end of lid, as finding on projected direction.
3. according to the semiconductor device of claim 1, it is characterized in that at least one is arranged between first and second conducting terminals in lid projection and the lid groove in cross-sectional view.
4. according to the semiconductor device of claim 1, it is characterized in that covering the side of groove and cover protruding side and extend along common plane.
5. according to the semiconductor device of claim 1, it is characterized in that the electric insulation lid comprises electrical insulation synthetic resin.
6. according to the semiconductor device of claim 1, it is characterized in that first and second clearing ends can contact each conductive component that is electrically connected to semiconductor element.
7. according to the semiconductor device of claim 6, it is characterized in that covering projection and be projected into the height that is higher than conductive component height on first and second clearing ends on the projected direction with respect to first and second surfaces of covering.
8. according to the semiconductor device of claim 1, it is characterized in that first and second surfaces of covering extend along imaginary plane.
9. according to the semiconductor device of claim 1, it is characterized in that first and second surfaces of covering extend parallel to each other.
10. according to the semiconductor device of claim 1, it is characterized in that covering projection is changing to the protruding clearing end direction of lid on first and second surfaces from lid perpendicular to the thickness on the thickness direction of projected direction, and the variation of lid projection thickness comprises covers the increase of projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, and the minimizing of lid projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, make and isolate the creepage distance increase along the electricity of lid projection.
11. semiconductor device according to claim 10, it is characterized in that lid projection and lid groove are adjacent one another are on thickness direction, and be positioned at and cover first side of crowning to the lid groove, cover protruding only performance and cover the minimizing of projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid, and be positioned at lid projection on thickness direction with the first side second side surface opposite, minimizing and the increase of projection thickness on the clearing end direction protruding to lid from first and second surfaces of lid cover in the performance of lid projection.
12. according to the semiconductor device of claim 1, at least one is not less than between first and second conducting terminals perpendicular to the minimum range on the direction of projected direction at the outstanding height of projected direction from first and second surfaces of lid to it is characterized in that covering projection.
13., it is characterized in that covering the outstanding height of projection and be not more than three times of minimum range between first and second conducting terminals according to the semiconductor device of claim 12.
14. semiconductor device according to claim 1, it is characterized in that in another cross-sectional view of semiconductor device that obtains along another imaginary plane, wherein this another imaginary plane is perpendicular to parallel with projected direction and extend by one imaginary plane in the first and second terminal projectioies, the lid groove extends in such a way, makes to cover groove arrangement in respect to the first and second terminal projectioies at least one face of each side of one.
15. semiconductor device according to claim 1, it is characterized in that covering groove extends in such a way, make in another cross-sectional view of semiconductor device that obtains along another imaginary plane, wherein this another imaginary plane is perpendicular to parallel with projected direction and extend by the imaginary plane of each in the first and second terminal projectioies, on each side of lid groove arrangement each side of each in respect to the first and second terminal projectioies.
16. according to the semiconductor device of claim 14 or 15, the bottom (13) that it is characterized in that preventing to cover groove extends at least one clearing end of lid, as finding on projected direction.
17., it is characterized in that lid projection and lid groove all are arranged between first and second conducting terminals in cross-sectional view strength according to the semiconductor device of claim 1.
18., it is characterized in that the width that covers groove is not less than 2mm according to the semiconductor device of claim 1.
CNB031095216A 2002-04-08 2003-04-08 Semiconductor device Expired - Fee Related CN100338771C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP104955/2002 2002-04-08
JP2002104955A JP2003303939A (en) 2002-04-08 2002-04-08 Power semiconductor device and inverter device

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Publication Number Publication Date
CN1450640A true CN1450640A (en) 2003-10-22
CN100338771C CN100338771C (en) 2007-09-19

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CN (1) CN100338771C (en)
DE (1) DE10313917B4 (en)

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