CN1433061A - Making process of intraconnection with no effect of chemical and mechanical grinding disc - Google Patents
Making process of intraconnection with no effect of chemical and mechanical grinding disc Download PDFInfo
- Publication number
- CN1433061A CN1433061A CN 02101728 CN02101728A CN1433061A CN 1433061 A CN1433061 A CN 1433061A CN 02101728 CN02101728 CN 02101728 CN 02101728 A CN02101728 A CN 02101728A CN 1433061 A CN1433061 A CN 1433061A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- layer
- chemical
- grinding
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The intraconnection wire making process to eliminate disc effect of chemical and mechanical grinding includes forming one griding stopping layer between the dielectric layer of semiconductor substrate with metal wires and forming metal layer in embedding structure through embedding process. The grinding stopping layer is used as the first grinding terminating layer in executing the first chemical and mechanical grinding process to grind out the barrier layer and the metal layer over the grinding stopping layer; and the surface of the metal layer is used as the second grinding terminal in executing the second and mechanical grinding process to grind out the grinding stopping layer. The said method can avoid disc effect of chemical and mechanical grinding.
Description
Technical field
The invention relates to a kind of intraconnections manufacture method, particularly relevant for a kind of in inlaying the lead processing procedure, in order to eliminate the intraconnections manufacture method of effect of chemical and mechanical grinding disc.
Background technology
Along with the semiconductor element size is dwindled day by day, require more to become strict for the resolution of photolithography in the processing procedure (photolithography).In order to reach higher Optical Resolution, not only need to improve the performance of process apparatus, also must get rid of for the factor that may cause interference in the processing procedure simultaneously, and the alignment error that the material surface unevenness is caused is one of them.Therefore, in the processing procedure of high density integrated circuit, the microcosmic surface of material is become more smooth, promptly become indispensable step.For example in metal internal connecting line (aetal interconnection) processing procedure, the inner metal dielectric layer of deposition can produce height along with the first metal layer of wafer surface and rise and fall, just must solve the problem of high low head by flattening method, meet with the difficulty that is difficult for shifting pattern because of exposure focusing with the micro-photographing process of second metal level of avoiding follow-up making.
In various flattening methods, chemical mechanical lapping (Chemical-MechanicalPoflishing, CMP) technology is held the advantage of its global planarization under the arm, become process technique important on the present production line, and be widely used in aspects such as shallow trench separation process (STI), metal internal connecting line processing procedure.
Inlaying the lead processing procedure is a kind of metal internal connecting line processing procedure.The known lead processing procedure of inlaying mainly is after defining the mosaic texture zone that connects intraconnections, form a barrier layer in the dielectric layer surface that isolates intraconnections and the inwall of mosaic texture again, and then with the preferable metal material of conductivity, for example materials such as copper, aluminium, tungsten or aluminium copper are inserted above-mentioned mosaic texture.Then, grind with chemical mechanical milling method excess metal material that irrigation canals and ditches are outer and barrier layer again and remove and in this mosaic texture, form one and be connected the lead of inlaying that intraconnections uses.Below will introduce the step that tradition is inlayed the lead processing procedure.
Figure 1A-1D be show conventional art inlay lead section processing procedure.At first, consult Figure 1A, semiconductor substrate 100 is provided.Secondly, utilize metallization process on the semiconductor-based end 100, to form a metal wire 110.Then, form a dielectric layer 120 in substrate 100 surfaces, and metal wire 110 is covered.Wherein, dielectric layer 120 can be simple layer or is made of the heterozygosis low-resistance matter dielectric material of multilayer, and it can optionally be adjusted.Then, consult Figure 1B, with damascene process definition dielectric layer 120, form the dual-damascene structure 130 that runs through dielectric layer 120 and connect metal wire 110 again.
Secondly, consult Fig. 1 C, form barrier layer 140 with physics or chemical vapour deposition technique in dielectric layer 120 and dual-damascene structure 130 inwalls earlier.Then, form the preferable metal level 150 of conductivity in barrier layer 140 surfaces with chemical vapour deposition technique or physical vaporous deposition, and dual-damascene structure 130 is filled up.Wherein, the material of metal level 150 can be the preferable copper of conductivity, aluminium, tungsten, aluminium copper etc.
Then, consult Fig. 1 D, after metal level 150 forms, utilize chemical mechanical milling method (CMP) to carry out planarization, excess metal layer 150 beyond the dual-damascene structure 130 and barrier layer 140 are removed.Yet; in process of lapping; because each regional grinding rate and pressure differ; in the grinding rate of metal level middle section often greater than its neighboring area; therefore after grinding finishes; shown in label 160, can form the phenomenon of dishization (Dishing) on metal level 150 surfaces usually, and influence the manufacturing and the productive rate of subsequent element.
Summary of the invention
In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of intraconnections manufacture method, can eliminate the dish effect that cmp produces.According to intraconnections manufacture method of the present invention, provide a grinding to stop layer, be applicable to double-insert process.When carrying out the first cmp processing procedure, stop layer as first grinding endpoint with above-mentioned grinding, next, again to grind metal level later as second grinding endpoint via the first cmp processing procedure, carry out the second cmp processing procedure in addition again, can effectively solve the problem of the carbonization phenomenon of layer on surface of metal whereby.Advanced low-k materials that the material that above-mentioned grinding stops layer can be silicon nitride, nitrogen oxidation silicon, carbonization silicon, silicon, form with the CVD processing procedure and specific organic material.
In addition, in the present invention, above-mentioned grinding stops the hard cover screen (hard mask) that layer can be used as anti-reflecting layer (anti-reflective layer) and define pattern.
For obtaining above-mentioned purpose, the present invention proposes a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc, comprises the following steps: to provide the semiconductor-based end, and forms metal wire in the semiconductor-based end; Form dielectric layer in substrate, and cover metal wire; Form grinding in dielectric layer and stop layer; Then, define dielectric layer, form to run through and grind the mosaic texture that stops layer and dielectric layer and connect metal wire with damascene process; Stop layer in grinding and go up the inwall formation barrier layer that reaches mosaic texture; Form metal level in above-mentioned barrier layer, and fill up mosaic texture; Next, stop layer as first grinding endpoint with grinding, carry out the first cmp processing procedure, worn being positioned at ground barrier layer and the metal level that stops layer top; As second grinding endpoint, carry out the second cmp processing procedure with layer on surface of metal, worn grinding stops layer; Form sealant at last to cover metal level and dielectric layer.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A-1D be show conventional art inlay lead section processing procedure;
Fig. 2 A-2F shows according to the described lead section processing procedure of inlaying of the embodiment of the invention.
The figure number explanation:
100, the semiconductor-based end of 200-;
110,210-metal wire;
120,230-dielectric layer;
130,250A, 250B-mosaic texture;
140,260-barrier layer;
150,270-metal level;
160,280-dish effect;
240-grinds and stops layer;
Stop layer on the 240A-;
Stop layer under the 240B-;
220,290-sealant.
Embodiment
Below will introduce the step according to the described intraconnections processing procedure of the embodiment of the invention, be to be example to inlay the lead processing procedure at this.
Fig. 2 A-2F shows according to the described lead section processing procedure of inlaying of the embodiment of the invention.At first, consult Fig. 2 A, semiconductor substrate 200 is provided.
Secondly, utilize metallization process (for example, single damascene process) to form a metal wire 210 on the semiconductor-based end 200, the scope of above-mentioned metal wire 210 thickness is between 2000 dust to 6000 dusts.Then form a sealant 220 again, in order to cover the surface of substrate 200 and metal wire 210.The function of above-mentioned sealant 220 is to prevent that metal wire 210 from electron mobility effect (electro-mlgration) taking place, its material can be silicon nitride (SiN), nitrogen oxidation silicon (SiON), carbonization silicon (SiC), silicon carboritride (SiCN), silicon hydronitrogen (SiNH) etc., and thickness is about between 100 dust to 900 dusts.
Then, form a dielectric layer 230 in sealant 220 surfaces.Wherein, dielectric layer 230 can be simple layer or is made of the heterozygosis low-resistance matter dielectric material of multilayer, and it can optionally be adjusted.Then, form grinding in dielectric layer 230 surfaces and stop layer 240, its material can be silicon nitride (SiN), nitrogen oxidation silicon (SiON), carbonization silicon (SiC), silicon (SiO
2), with the formed advanced low-k materials of CVD method, or specific organic material etc., thickness can be between 300 dust to 1500 dusts.
In addition, grind and to stop layer 240 and can be plural layer, it comprise stop on one layer 240A and under stop a layer 240B.On to stop layer 240A as follows with the combination that stops down layer 240B: on stop to stop under layer 240A/ layer 240B the material combination can be silicon nitride (SiN) 240A/ silicon (SiO
2) 240B, silicon nitride (SiN) 240A/ nitrogen oxidation silicon (SiON) 240B, carbonization silicon (SiC) 240A/ silicon (SiO
2) 240B, silicon nitride (SiN) 240A/ low-k material 240B, carbonization silicon (SiC) 240A/ low-k material 240B etc.Stop in the layer 240 in grinding, on stop layer 240A grinding rate stop a layer 240B under being higher than.Therefore, the grinding by the control sandwich construction stops the problem that layer 240 grinding rate can effectively overcome the carbonization effect.
In addition, grind and to stop layer 240 and can be used as the hardcoat that is used for defining mosaic texture in the successive process and admire (hard mask) and anti-reflecting layer (Anti-Reflection Coating).
Consult Fig. 2 B, again with damascene process definition dielectric layer 230, formation one runs through dielectric layer 230 and grinds the dual-damascene structure 250A that stops layer 240 and connection metal wire 210 and inlay irrigation canals and ditches 250B.
Secondly, consult Fig. 2 C, form barrier layer 260 with physics or chemical vapour deposition technique in dielectric layer 230 and dual- damascene structure 250A, 250B inwall earlier.Then, form the preferable metal level of a conductivity 270 with chemical vapour deposition technique, and dual- damascene structure 250A, 250B are filled up in barrier layer 260 surfaces.Wherein, the material of metal level 270 can be the preferable copper of conductivity, aluminium, tungsten, aluminium copper etc., in the present embodiment, is example with the copper metal.
Then, consult Fig. 2 D, after metal level 270 forms, stop layer 240 as grinding endpoint, utilize chemical mechanical milling method (CMP) to carry out planarization, excess metal layer 270 beyond dual-damascene structure 250A and the 250B and barrier layer 260 are removed with grinding.As mentioned above; because each regional grinding rate and pressure differ, in the grinding rate of metal level middle section often greater than its neighboring area, therefore after grinding finishes; shown in label 280, can form the phenomenon of dishization (Dishing) usually on metal level 270 surfaces.
Next, consult Fig. 2 E, carry out secondary cmp processing procedure, as grinding endpoint, because the result of dish effect, account for that to stop layer 240 in the grinding of metal level 270 both sides higher with respect to metal level 270 with remaining metal level 70 surfaces this moment, therefore, after carrying out secondary cmp processing procedure, grinding can be stopped layer 240 and remove, and make metal level 270 surfaces reach the effect of planarization.
At last, shown in Fig. 2 F, form sealant (sealinglayer) 290 on metal level 270 and dielectric layer 230, its material can be silicon nitride (SiN), nitrogen oxidation silicon (SiON), carbonization silicon (SiC), silicon carboritride (SiCN) etc., and thickness is about between 100 dust to 600 dusts.So as to covering metal level 270 and dielectric layer 230 fully, finished the processing procedure of intraconnections.
According to the described intraconnections manufacture method of the embodiment of the invention, except the dish effect that can improve conventional art, stop layer 240 setting by grinding, can reduce the electromigration of metal level 270.Moreover, because effectively improved behind the cmp processing procedure in the dish effect that metal level took place, make layer on surface of metal reach the effect of planarization, so formed sealant of subsequent step, be able to reach good degree of adhesion with metal level, and, can avoid (outgas) effect of giving vent to anger of dielectric layer because sealant and metal level reach the result of good degree of adhesion.In addition, according to the described intraconnections manufacture method of the embodiment of the invention, except above-mentioned advantage, owing to need not increase extra instrument, and integrate easily, significantly improved traditional intraconnections manufacturing technology.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope defined.
Claims (14)
1, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc is characterized in that: comprise the following steps:
The semiconductor substrate is provided, and forms a metal wire in the above-mentioned semiconductor-based end;
Form a dielectric layer in above-mentioned substrate, and cover above-mentioned metal wire;
Form a grinding and stop layer in above-mentioned dielectric layer;
Define above-mentioned dielectric layer with damascene process, form and run through the mosaic texture that above-mentioned grinding stops layer and dielectric layer and connects above-mentioned metal wire;
Form a barrier layer and stop the inwall that layer upward reaches above-mentioned mosaic texture in above-mentioned grinding;
Form a metal level in above-mentioned barrier layer, and fill up above-mentioned mosaic texture;
Stop layer as first grinding endpoint with above-mentioned grinding, carry out the first cmp processing procedure, wornly be positioned at an above-mentioned barrier layer and the metal level that above-mentioned grinding stops layer top;
As second grinding endpoint, carry out the second cmp processing procedure with above-mentioned layer on surface of metal, worn above-mentioned grinding stops layer; And
Form one first sealant to cover above-mentioned metal level and dielectric layer.
2, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: more comprise the following steps:
Between above-mentioned metal wire and dielectric layer, form one second sealant.
3, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 2 is characterized in that: wherein above-mentioned grinding stops layer and comprises and stop layer on one and stop layer once.
4, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 3 is characterized in that: the grinding rate that stops layer on wherein above-mentioned is higher than and stops layer under above-mentioned.
5, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 4 is characterized in that: the material that stops layer on wherein above-mentioned is selected from one of nitrogenize sand and carbonization silicon.
6, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 4 is characterized in that: the wherein above-mentioned material that stops layer down is selected from silicon, nitrogen oxidation silicon, reaches one of low-k material.
7, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: wherein the material of above-mentioned metal level is selected from copper, aluminium, reaches one of tungsten.
8, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: the material that wherein above-mentioned grinding stops layer is a silicon nitride.
9, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: the material that wherein above-mentioned grinding stops layer is a nitrogen oxidation silicon.
10, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: the material that wherein above-mentioned grinding stops layer is a carbonization silicon.
11, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: the material that wherein above-mentioned grinding stops layer is a silicon.
12, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1, it is characterized in that: wherein the thickness range of above-mentioned metal wire is between 2000 dust to 6000 dusts.
13, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1, it is characterized in that: wherein the thickness range of above-mentioned sealant is between 100 dust to 900 dusts.
14, a kind of intraconnections manufacture method of eliminating effect of chemical and mechanical grinding disc according to claim 1 is characterized in that: wherein above-mentioned grinding stops the thickness range of layer between 300 dust to 1500 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101728 CN1433061A (en) | 2002-01-14 | 2002-01-14 | Making process of intraconnection with no effect of chemical and mechanical grinding disc |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101728 CN1433061A (en) | 2002-01-14 | 2002-01-14 | Making process of intraconnection with no effect of chemical and mechanical grinding disc |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1433061A true CN1433061A (en) | 2003-07-30 |
Family
ID=27627365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02101728 Pending CN1433061A (en) | 2002-01-14 | 2002-01-14 | Making process of intraconnection with no effect of chemical and mechanical grinding disc |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1433061A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373587C (en) * | 2003-09-04 | 2008-03-05 | 南亚科技股份有限公司 | Method internal connector producing process and metal silicide layer removing method |
| CN102615584A (en) * | 2011-01-31 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical grinding method |
| CN104599989A (en) * | 2015-01-05 | 2015-05-06 | 武汉新芯集成电路制造有限公司 | Wafer integrating lead process and buried type color filer |
| CN110328561A (en) * | 2018-03-30 | 2019-10-15 | 长鑫存储技术有限公司 | The preparation method of chemical and mechanical grinding method, system and metal plug |
-
2002
- 2002-01-14 CN CN 02101728 patent/CN1433061A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373587C (en) * | 2003-09-04 | 2008-03-05 | 南亚科技股份有限公司 | Method internal connector producing process and metal silicide layer removing method |
| CN102615584A (en) * | 2011-01-31 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical grinding method |
| CN104599989A (en) * | 2015-01-05 | 2015-05-06 | 武汉新芯集成电路制造有限公司 | Wafer integrating lead process and buried type color filer |
| CN110328561A (en) * | 2018-03-30 | 2019-10-15 | 长鑫存储技术有限公司 | The preparation method of chemical and mechanical grinding method, system and metal plug |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1419277A (en) | Method for making double inlaying latch by using metal hard shielding layer | |
| CN1120241A (en) | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD | |
| CN1343372A (en) | Air gap dielectric in self-aligned via structures | |
| CN101079408A (en) | Double-inlay structure and its making method | |
| CN1815711A (en) | Interconnect structure and method of forming the same | |
| CN1106033C (en) | Flatening method for forming dielectric layer between layers | |
| CN2726116Y (en) | Structure for improving adhesivity between etching stop layer and metal layer | |
| CN1815708A (en) | Interconnect structure with low-resistance inlaid copper/barrier and method for manufacturing the same | |
| US6645863B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
| CN1606148A (en) | Method of selectively making uniform copper interconnect layer using plating technology | |
| CN1750249A (en) | Semiconductor device in IC circuit and method for producing it | |
| CN102324401B (en) | Method for manufacturing copper interconnection structure | |
| CN101055421A (en) | Method for forming double inserted structure | |
| CN1238892C (en) | Method for mfg. double inlaid structure | |
| CN1433061A (en) | Making process of intraconnection with no effect of chemical and mechanical grinding disc | |
| CN101471324B (en) | Ultra-low K interconnection structure and method of manufacturing the same | |
| CN1692481A (en) | Semiconductor device | |
| CN1447413A (en) | Method of mfg. semiconductor device by using double-ripple tech | |
| CN1421915A (en) | Manufacture of double-embedded structure | |
| CN1237598C (en) | Method for forming metal capacitor in inlaying mfg. process | |
| CN1055788C (en) | Method for making internal connecting wires within semiconductor device | |
| CN101661897B (en) | Interconnector structure and manufacturing method thereof | |
| CN1610090A (en) | Double-mosaic producing process capable of simplifing production | |
| CN1173395C (en) | Method of producing intraconnecting copper wire in coverage layer | |
| CN1392605A (en) | Method for producing mosaic inner connection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |