CN1428852A - Semiconductor device and its production method - Google Patents
Semiconductor device and its production method Download PDFInfo
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- CN1428852A CN1428852A CN01144815A CN01144815A CN1428852A CN 1428852 A CN1428852 A CN 1428852A CN 01144815 A CN01144815 A CN 01144815A CN 01144815 A CN01144815 A CN 01144815A CN 1428852 A CN1428852 A CN 1428852A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention relates to a semiconductor device and its making method. Its making method includes the following steps: firstly, electrically connecting electronic element on first base plate, then connecting said first base plate on semiconductor chip or second base plate, after the semiconductor chip is connected on the second base plate, electrically connecting first base plate, second base plate and chip, then making the above-mentioned material undergo the processes of die-pressing, sphere-planting and cutting so as to can obtain the invented product.
Description
Technical field
The present invention relates to a kind of semiconductor device and method for making thereof, refer to a kind of semiconductor device and method for making thereof that is integrated with as the electronic component of passive component especially.
Background technology
General semiconductor device is changed to and promotes its performance, normal add passive component is for example arranged electronic component in semiconductor device.For example United States Patent (USP) the 5th, 264, No. 730, the 5th, 311, No. 405, the 5th, 811, No. 880, the 5th, 825, No. 628, and the 6th, 316, No. 828 etc., promptly disclose to have passive component is set on the substrate of ball grid array (BGA) packaging part, to promote the technology contents of the whole electrical functionality of packaging part.
The substrate that this kind has the semiconductor device of passive component disposes as Fig. 9, preferably will be for example passive component such as resistance or electric capacity 40 connect the position of adjacent chips 20 on the ground loop (Ground Ring) 13 that places substrate 10 and power ring (the Power Ring) 12, be the best passive component 40 is placed respectively simultaneously in abutting connection with four corners of chip 20.
But the collocation form of this kind substrate 10 is because the adding of passive component 40, to cause the layout gap P of the wire bond pad (Bond Finger) 11 between this passive component 40 to be forced to become the 0.125mm of fine clearance (Fine Pitch), make the significantly increase that causes manufacturing cost by for example traditional 0.150mm shrinkage limit.
In addition, the setting of above-mentioned passive component 40 also can cause the wiring of substrate 10 for avoiding passive component 40 its wiring zone and space all to be restricted equally, and then the global design of influence and substrate; Otherwise, for taking the wiring on the substrate 10 into account, passive component 40 quantity is set and the position also is restricted equally, cause the performance boost of semiconductor device also to produce bottleneck.
Moreover, in the time of passive component 40 must being placed near the periphery beyond the corner of chip 20 if adapt to actual demand, then Chang Yin has lead 30 to walk around the top of passive component 40 by the weld pad (Bond Pad) 21 of chip 20 and be electrically connected on the corresponding wire bond pad 11 of substrate 10, make easy generation as shown in figure 10 lead 30 touch the angle edge of passive component 40 and cause short circuit phenomenon, and then the reliability of the yield of influence and routing and product.Though this kind easily produces the shortcoming of short circuit phenomenon and can be solved by the materials that in advance passive component 40 lining one decks insulated, yet the technologic increase of this kind also can bring the skyrocketing of production cost.
For solving above-mentioned problems, United States Patent (USP) the 5th, 670, though providing a kind of for No. 824 is incorporated into passive component on one sheet material, be placed on the structure of chip below again, but the integrated passive component plate of this kind causes its cost very expensive owing to can't use passive components such as traditional resistance or electric capacity, so be difficult to accord with the demands of the market, and can't produce in a large number.
In addition, though No. the 89121891st, TaiWan, China patent application also propose as shown in figure 11 passive component 40 directly is electrically connected at structure on the chip 40, but this kind structure must form the gluing pad 22 of passive component 40 in advance on chip 20, and on this gluing pad 22, carry out welding block bottom metal metallization processes (Under Bumping Metalization), electrically connect with welding agent (Solder Paste) with passive component 40, and cause process complications, and cause the significantly increase of manufacturing cost.
This patent proposes a kind of directly placing on the chip 20 passive component 40 is glutinous as shown in figure 12 in addition, again this passive component 40 is electrically connected to the structure of power ring 12 and ground loop 13 on the substrate 10 respectively with lead 42,43, yet the contact jaw (Terminal) of the passive component 40 of this kind structure is smooth inadequately because of the surface, and be difficult to utilize the bonding equipment of conventional package technology to carry out bonding wire, simultaneously, its contact jaw promptly also can't carry out bonding wire if do not carry out gold-plated processing.Therefore, this kind structure also because of be difficult under existing equipment and technology framework, to carry out volume production so, and can't suit the demand in market.
Summary of the invention
In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can be when adding the electronic component of passive component for example, and substrate need not to use the wire bond pad layout of fine clearance, and can reduce production costs.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can be when adding the electronic component of passive component for example, the wires design of substrate and electronic component quantity is set and the position all need not be limited.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can not produce lead and touch electronic component and cause short circuit phenomenon when add the electronic component of passive component for example.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can need not use expensive integrated electronic component plate, and can effectively save manufacturing expense when add the electronic component of passive component for example.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can be when adding the electronic component of passive component for example, the gluing pad of electronic component need not be set on chip in advance, also need not on this gluing pad, apply the technology of welding block bottom metalization, and can simplify manufacture process and reduce cost.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof, it can be when adding the electronic component of passive component for example, do not have and be difficult to utilize existing bonding wire equipment on electronic component, to carry out the puzzlement of bonding wire, and can under existing technology framework, carry out volume production.
For reaching above-mentioned purpose, semiconductor device of the present invention comprises: the electronic component with first surface and second surface; First substrate with first surface and second surface, wherein, the second surface of this electronic component is electrically connected on the first surface of this first substrate; Semiconductor chip with first surface and second surface; Second substrate with first surface and second surface, wherein, the second surface of this semiconductor chip connects on the first surface that places this second substrate, this mounting has the second surface of first substrate of electronic component to connect to place by on this semiconductor chip and the formed structure of this second substrate simultaneously, for example connect on the first surface that places this semiconductor chip, or on the first surface of this second substrate, or other appropriate position; Electrically connect many leads of the first surface of the first surface of first surface, this first substrate of this semiconductor chip and this second substrate; This electronic component, this first substrate, this semiconductor chip and the packing colloid of this lead on the first surface of this second substrate are covered; And plant a plurality of soldered balls on the second surface of this second substrate.
The method for making of semiconductor device of the present invention then comprises the following steps: to prepare to have respectively first substrate, electronic component, semiconductor chip and second substrate of first surface and second surface; The second surface of electronic component is electrically connected on the first surface of this first substrate; Connect put semiconductor chip second surface on the first surface of second substrate; This second surface that is loaded with first substrate of electronic component connect place, for example connect on the first surface that places this semiconductor chip by on this semiconductor chip and the formed structure of second substrate, or on the first surface of this second substrate, or other appropriate position; The many leads of burn-oning make between the first surface of the first surface of first surface, this first substrate of this semiconductor chip and this second substrate and can form the electric connection state; With this electronic component, this first substrate, this semiconductor chip, and this lead be coated on the first surface of this second substrate with packing colloid; And planting soldered ball on the second surface of this second substrate.
Above-mentioned semiconductor device and method for making thereof also can apply to use on the semiconductor device of lead frame, and wherein, this second surface that is loaded with first substrate of electronic component connects on the first surface that places semiconductor chip.
Semiconductor device and method for making thereof by the invention described above, people desire by the electronic component that adds passive component such as resistance or electric capacity for example on semiconductor device when promoting its performance, need not change the design of substrate or chip again, promptly the footpath can utilize existing spare part, raw material, technology, technology, and machinery equipment etc. is soft, after hardware facility is made the substrate that mounting has electronic component, again in Jiang the encapsulating structure that is arranged at semiconductor device, just can be more cheap far beyond prior art at cost, but the product yield gets the effect of obtaining the electrical functionality of strengthening semiconductor device immediately under the situation that promotes.
Description of drawings
Describe embodiments of the invention in detail below in conjunction with accompanying drawing, but but practical range of the present invention is not the content that only is confined to embodiment.
Figure 1A and 1B show front view and the vertical view that can be used for first substrate of the present invention respectively;
Fig. 2 A and 2B show that respectively electronic component of the present invention is electrically connected at front view and the vertical view on first substrate;
Fig. 3 A and 3B show that respectively semiconductor chip of the present invention connects front view and the vertical view that places on second substrate;
Fig. 4 A and 4B show that respectively first substrate that is loaded with electronic component of the present invention connects front view and the vertical view that places on the semiconductor chip and finish routing;
Fig. 5 shows the front view of finishing mold pressing and planting the semiconductor device of ball of the present invention;
Fig. 6 A and 6B are the schematic diagrames that shows other embodiment of routing mode of the present invention respectively;
Fig. 7 is the schematic diagram that shows another embodiment of the present invention;
Fig. 8 A is the structure vertical view that the demonstration another embodiment of the present invention is not carried out mould pressing process as yet;
Fig. 8 B is that the embodiment of displayed map 8A finishes mold pressing and plants the schematic diagram of ball;
Fig. 9 shows existing substrate configuration schematic diagram with semiconductor device of passive component;
Figure 10 shows existing lead short circuit schematic diagram with semiconductor device of passive component;
Figure 11 shows another existing structural representation with semiconductor device of passive component;
Figure 12 shows another existing structural representation with semiconductor device of passive component.
Symbol description among the figure:
10,10 ' substrate, second substrate, 11,52 power supply wire bond pads
12 power rings, 13 ground loops
14,14 ', 22,44,56 first surfaces
100 chip carriers, 20 semiconductor chips, chip
21 weld pads, 22 gluing pads
23,45,57 second surfaces
30,31,32,32 ', 33,34 ', 42,43 leads
40 passive components, 41 electronic components
50 first substrates, 53 ground connection wire bond pads
54 power supply weld pads, 55 ground connection weld pads
60, more than 70 soldered ball of 60 ' packing colloid
70 ' a plurality of lead foots
Embodiment
Semiconductor device of the present invention comprises electronic component 41, first substrate 50, semiconductor chip 20, second substrate 10, many leads 30,31,32,33,34, packing colloid 60 and a plurality of soldered balls 70 as shown in Figure 5.
Wherein, this electronic component 41 has first surface 44 and second surface 45, and this electronic component 41 can be for example passive component such as resistance or electric capacity or other electronic component that is fit to simultaneously.The second surface 45 of this electronic component 41 welds on the first surface 56 of being located at first substrate 50 by for example melt back welding existing modes such as (Reflow), makes to be electrically connected at power supply weld pad 54 and the ground connection weld pad 55 that is formed on this first surface 56.
This semiconductor chip 20 also has first surface 22 and second surface 23, and its second surface 23 connects on the first surface 14 that places second substrate 10 existing mode such as for example to stick together.This mounting has first substrate 50 of electronic component 41 can select to connect on the first surface 22 that places this semiconductor chip 20 by existing mode such as for example sticking together with its second surface 57.
The many leads 30 of conduction such as gold thread (Gold Wire) for example, 31,32,33,34 are welded and make the first surface 22 that is electrically connected at this semiconductor chip 20 respectively, the first surface 56 of this first substrate 50, and between the first surface 14 of this second substrate 10, wherein, as Fig. 4 B and shown in Figure 5, lead 30 electrically connects on the first surface 22 of semiconductor chips 20 signal pad (Signal Pad) in the formed weld pad 21 to the first surface 14 of second substrate 10 on the formed signal bond wires pad (Signal Finger) 11,31 in lead electrically connect that the institute to the first surface 56 of first substrate 50 of the power source pad (Power Pad) in the formed weld pad 21 on the first surface 22 of semiconductor chip 20 forms and the power supply wire bond pad (Power Finger) 52 of these power supply weld pad 54 electric connections on, lead 32 then electrically connects formed power ring 12 on the first surface 14 of formation on the first surface 56 of this first substrate 50 and this power supply wire bond pad 52 another power supply wire bond pad 52 to second substrates 10 in parallel.
Similarly, lead 33 electrically connect that the institute to the first surface 56 of first substrate 50 of the ground mat (Ground Pad) in the formed weld pad 21 on the first surface 22 of semiconductor chips 20 forms and the ground connection wire bond pad (Ground Finger) 53 of these ground connection weld pad 55 electric connections on, lead 34 then electrically connects formed ground loop 13 on the first surface 14 of formation on the first surface 56 of this first substrate 50 and this ground connection wire bond pad 53 another ground connection wire bond pad 53 to second substrates 10 in parallel.
This electronic component 41 of 60 linings of the packing colloid of tool protective effect, first substrate 50, semiconductor chip 20 and lead 30,31,32,33,34 are on the first surface 14 of this second substrate 10.Then be implanted with on the second surface 15 of this second substrate 10 and can make semiconductor device of the present invention and the extraneous a plurality of soldered balls (Solder Ball) 70 that electrically connect.
Above-mentioned first substrate 50 that is loaded with electronic component 41 also must be shown in Fig. 8 A and Fig. 8 B, select to connect place second substrate 10 ' first surface 14 ' on, to reduce the whole height of this semiconductor device.Wherein, by the first surface 22 that is welded in semiconductor chip 20 respectively, second substrate 10 ' first surface 14 ' and the first surface 56 of first substrate 50 between many leads 30,35,36, can reach and electrically connect semiconductor chip 20, second substrate 10 ' and the purpose of first substrate 50 (electronic component 41).
In addition, above-mentioned first substrate 50, semiconductor chip 20, and second side connecting conductor formula between the substrate 10 also can select as shown in Figure 6A mode, be about to the lead 32 and 34 of former Fig. 5, change respectively by the power source pad in the formed weld pad 21 on the first surface 22 of this semiconductor chip 20 certainly be electrically connected to the lead 32 on the formed power ring 12 on the first surface 14 of second substrate 10 ', and the ground mat in the formed weld pad 21 is electrically connected to the lead 34 on the formed ground loop 13 on the first surface 14 of second substrate 10 ' replaced on the first surface 22 of this semiconductor chip 20, will still can reach equal effect.
Again, side connecting conductor formula between above-mentioned first substrate 50, semiconductor chip 20 and second substrate 10 also must be selected the pattern shown in Fig. 6 B for use, also be about to the lead 31 and 33 of former Fig. 5, change respectively, also can reach equal effect by as shown in Figure 6A lead 32 ' and 34 ' replaced.
The form that the connected mode of the lead among the embodiment shown in above-mentioned Fig. 8 A figure and Fig. 8 B also must be considered Fig. 6 A for example or Fig. 6 B in light of actual conditions is carried out equivalence and is changed, and its details will no longer be given unnecessary details.
Moreover technological thought of the present invention also must apply to use on the semiconductor device of lead frame, as shown in Figure 7.Wherein, first substrate 50 that this mounting has an electronic component 41 connects on the first surface 22 that places semiconductor chip 20 by existing mode such as for example sticking together with its second surface 57, and this semiconductor chip 20 then connects and places on the chip carrier 100 by existing mode such as for example sticking together with its second surface 23.Many 30,31,32,33,34 in leads weld and make the first surface of the first surface 22 that is electrically connected at this semiconductor chip 20, first substrate 50 respectively and be disposed at a plurality of lead foots 70 of semiconductor chip 20 peripheries ' the inner between.The packing colloid 60 of tool protective effect ' lining live this electronic component 41, first substrate 50, semiconductor chip 20, chip carrier 100, many leads 30,31,32,33,34 and a plurality of lead foot 70 ' partly inboard.In addition, this lead also can adopt aforementioned equivalent connected mode as Fig. 6 A or Fig. 6 B, and still must reach identical effect.
The method for making of semiconductor device of the present invention comprises following each step as shown in Figure 5.
At first, preparation one has first substrate 50 of first surface 56 and second surface 57, shown in Figure 1A and Figure 1B.Wherein, be formed with a plurality of power supply wire bond pads 52, ground connection wire bond pad 53, power supply weld pad 54 and ground connection weld pad 55 on the first surface 56 of this first substrate 50, this power supply wire bond pad 52 and ground connection wire bond pad 53 are respectively with parallel connection paired mode and power supply weld pad 54 and ground connection weld pad 55 formation electric connection states simultaneously.
The inferior for example second surface 45 of the electronic component 41 of passive component such as resistance or electric capacity welds on the first surface 56 of being located at first substrate 50 in existing modes such as for example melt back welding, shown in Fig. 2 A and Fig. 2 B, make to be electrically connected at power supply weld pad 54 and the ground connection weld pad 55 that is formed on this first surface 56.
Again with for example stick together etc. existing mode connect put semiconductor chip 20 second surface 23 on the first surface 14 of second substrate 10, shown in Fig. 3 A and Fig. 3 B.
Again this mounting there is the second surface 57 of first substrate 50 of electronic component 41 to connect on the first surface 22 that places this semiconductor chip 20 existing mode such as for example to stick together, and the many for example leads 30,31,32,33,34 of conduction such as gold thread (Gold Wire) of burn-oning, shown in Fig. 4 A and Fig. 4 B, form the electric connection state between the first surface 14 with the first surface 56 of the first surface 22 that makes this semiconductor chip 20, this first substrate 50 and this second substrate 10.The detailed annexation of this lead 30,31,32,33,34 is illustrated in the aforementioned relevant embodiment of semiconductor device of the present invention, so repeat no more in this.
Then carry out the mold pressing step, be covered these electronic components 41, first substrate 50, semiconductor chip 20 and many leads 30,31,32,33,34 on the first surface 14 of second substrate 10 with the packing colloid 60 that makes the tool protective effect.At last, on the second surface 15 of this second substrate 10, plant the soldered ball 70 of a plurality of for example tin balls again, can electrically connect with the external world via this soldered ball 70 to make made semiconductor device, as shown in Figure 5.
The connected mode of above-mentioned lead also can be selected foregoing form as Fig. 6 A or Fig. 6 B for use, still all can reach identical effect.
In addition, first substrate 50 that above-mentioned mounting has an electronic component 41 also as previously mentioned, with the mode shown in Fig. 8 B connect place second substrate 10 ' first surface 14 ' on, to reduce the whole height of semiconductor device.
Moreover the method for making of above-mentioned semiconductor device also must apply to the making of the semiconductor device of use lead frame as shown in Figure 7.Wherein, the method for making of the semiconductor device of this use lead frame only must add to connect in existing method for making puts the step of first substrate 50 on semiconductor chip 20 that is loaded with electronic component 41, and add the steps such as lead of drawing on the first surface 56 of weldering by first substrate 50 and get final product, so will repeat no more its details at this.
On the substrate that the method for making of above-mentioned semiconductor device also must be applied to arrange with matrix form (Matrix), be beneficial to carry out mass-produced occasion again.Wherein, this first substrate 50 can be made the form of arranged in advance, treats that electronic component 41 welds respectively to be located at promptly to be cut list (Singulation) behind its correspondence position and handle, to form independent first substrate 50 that is loaded with electronic component 41.Simultaneously, this second substrate 10 also can similarly be made the form of arranged, to put semiconductor chip 20 and above-mentioned independent first substrate 50 that is loaded with electronic component 41 connecing respectively, and the lead of burn-oning, carry out mold pressing, plant ball after, cut again and single can be finished semiconductor device of the present invention.
The above; only in order to instantiation of the present invention to be described; but be not in order to limit practical range of the present invention; such as those skilled in the art still all should be contained by the protection range of this patent not breaking away from all equivalence changes of being finished under disclosed spirit and the technological thought or modifying.
Claims (19)
1. semiconductor device comprises:
Electronic component with first surface and second surface;
First substrate with first surface and second surface, the second surface of this electronic component are electrically connected on the first surface of this first substrate;
Semiconductor chip with first surface and second surface;
Second substrate with first surface and second surface, the second surface of this semiconductor chip connects on the first surface that places this second substrate, and this mounting has the second surface of first substrate of this electronic component then to connect to place by on this semiconductor chip and the formed structure of this second substrate;
Electrically connect many leads of the first surface of the first surface of first surface, this first substrate of this semiconductor chip and this second substrate;
This electronic component, this first substrate, this semiconductor chip and the packing colloid of this lead on the first surface of this second substrate are covered; And
Plant a plurality of soldered balls on the second surface of this second substrate.
2. semiconductor device according to claim 1 is characterized in that: this mounting has the second surface of first substrate of this electronic component to connect on the first surface that places this semiconductor chip.
3. semiconductor device according to claim 1 is characterized in that: this mounting has the second surface of first substrate of this electronic component to connect on the first surface that places this second substrate.
4. according to each described semiconductor device among the claim 1-3, it is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface of first surface, this semiconductor chip of the first surface that electrically connects this first substrate respectively and this semiconductor chip and this second substrate and this first substrate and this second substrate.
5. according to each described semiconductor device among the claim 1-3, it is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface that electrically connects this first substrate respectively and this semiconductor chip and this semiconductor chip and this second substrate.
6. according to each described semiconductor device among the claim 1-3, it is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface that electrically connects this first substrate respectively and this second substrate and this semiconductor chip and this second substrate.
7. according to each described semiconductor device among the claim 1-3, it is characterized in that: this electronic component is a passive component.
8. according to each described semiconductor device among the claim 1-3, it is characterized in that: this electronic component is to be located on the first surface of this first substrate with the weldering of melt back welding manner.
9. the method for making of a semiconductor device comprises the following steps:
Prepare to have respectively first substrate, electronic component, semiconductor chip and second substrate of first surface and second surface;
The second surface of this electronic component is electrically connected on the first surface of this first substrate;
Connect put this semiconductor chip second surface on the first surface of this second substrate;
Having the second surface of first substrate of this electronic component to connect this mounting places by on this semiconductor chip and the formed structure of this second substrate;
The many leads of burn-oning make between the first surface of the first surface of first surface, this first substrate of this semiconductor chip and this second substrate and form the electric connection state;
With this electronic component, this first substrate, this semiconductor chip, and this lead be coated on the first surface of this second substrate with packing colloid; And
Planting soldered ball on the second surface of this second substrate.
10. according to the method for making of the described semiconductor device of claim 9, it is characterized in that: this mounting has the second surface of first substrate of this electronic component to connect on the first surface that places this semiconductor chip.
11. the method for making according to the described semiconductor device of claim 9 is characterized in that: this mounting has the second surface of first substrate of this electronic component to connect on the first surface that places this second substrate.
12. the method for making according to each described semiconductor device among the claim 9-11 is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface of first surface, this semiconductor chip of the first surface that electrically connects this first substrate respectively and this semiconductor chip and this second substrate and this first substrate and this second substrate.
13. the method for making according to each described semiconductor device among the claim 9-11 is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface that electrically connects this first substrate respectively and this semiconductor chip and this semiconductor chip and this second substrate.
14. the method for making according to each described semiconductor device in the claim 9-11 item is characterized in that: this lead comprises the lead of the first surface of the first surface of the first surface of the first surface that electrically connects this first substrate respectively and this second substrate and this semiconductor chip and this second substrate.
15. the method for making according to each described semiconductor device in the claim 9-11 item is characterized in that: this electronic component is a passive component.
16. the method for making according to each described semiconductor device in the claim 9-11 item is characterized in that: this electronic component is to be located on the first surface of this first substrate with the weldering of melt back welding manner.
17. a semiconductor device comprises:
Electronic component with first surface and second surface;
Substrate with first surface and second surface, the second surface of this electronic component are electrically connected on the first surface of this substrate;
Semiconductor chip with first surface and second surface, this mounting have the second surface of the substrate of this electronic component to connect on the first surface that places this semiconductor chip;
Second surface for this semiconductor chip connects the chip carrier of putting;
Be disposed at a plurality of lead foots of this semiconductor chip periphery;
Electrically connect the first surface of this semiconductor chip, the first surface of this substrate and the many leads of this lead foot the inner; And
The inboard packing colloid partly of this electronic component, this substrate, this semiconductor chip, this chip carrier, this lead and this lead foot is lived in lining.
18. semiconductor device according to claim 17 is characterized in that: this electronic component is a passive component.
19. according to claim 17 or 18 described semiconductor devices, it is characterized in that: this electronic component is to be located on the first surface of this substrate with the weldering of melt back welding manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN011448156A CN1216423C (en) | 2001-12-26 | 2001-12-26 | Semiconductor device and its production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN011448156A CN1216423C (en) | 2001-12-26 | 2001-12-26 | Semiconductor device and its production method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1428852A true CN1428852A (en) | 2003-07-09 |
| CN1216423C CN1216423C (en) | 2005-08-24 |
Family
ID=4677841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN011448156A Expired - Lifetime CN1216423C (en) | 2001-12-26 | 2001-12-26 | Semiconductor device and its production method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1216423C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456464C (en) * | 2005-06-09 | 2009-01-28 | 恩益禧电子股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN102344109A (en) * | 2010-08-02 | 2012-02-08 | 日月光半导体制造股份有限公司 | Packaging structure and manufacturing method thereof |
-
2001
- 2001-12-26 CN CN011448156A patent/CN1216423C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456464C (en) * | 2005-06-09 | 2009-01-28 | 恩益禧电子股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| US7687803B2 (en) | 2005-06-09 | 2010-03-30 | Nec Electronics Corporation | Semiconductor device and method for manufacturing semiconductor device |
| CN102344109A (en) * | 2010-08-02 | 2012-02-08 | 日月光半导体制造股份有限公司 | Packaging structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1216423C (en) | 2005-08-24 |
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