CN1438684A - Semiconductor chip package method and its package structure - Google Patents
Semiconductor chip package method and its package structure Download PDFInfo
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- CN1438684A CN1438684A CN02110855A CN02110855A CN1438684A CN 1438684 A CN1438684 A CN 1438684A CN 02110855 A CN02110855 A CN 02110855A CN 02110855 A CN02110855 A CN 02110855A CN 1438684 A CN1438684 A CN 1438684A
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The method includes the following steps: (1) The substrate is prepared. The bonding pad of lead wires is setup on its upper surface and the bounding pad of solder balls as well as the bounding pad of the lugs is setup on its undersurface. (2) The first chip is pasted on the upper surface of the substrate. (3) The bounding pad on the first chip is connected to the bonding pad of lead wires on its upper surface through metal wires. (4) The plastic package is formed on the side, where the first chip is pasted. (5) The metal lugs are generated on the second chip. (6) The second chip is pasted on the undersurface, making the lugs on the second chip connect to the bounding pad of the lugs. (7) Pins are soldered on the solder balls. The invention also provides the structure of encapsulating the semiconductor chips.
Description
Technical field
The present invention relates to semiconductor packaging, relate in particular to a kind of method for packing of highdensity ball grid array.
Background technology
In the conventional semiconductor packages technology, a kind of method for packing of the ball grid array that is well known is arranged, for example U.S. Pat 5216278 has disclosed this technology, and its device for a kind of high pin provides a kind of effective solution.
Sketch this known method for packing below with reference to Fig. 6 to Fig. 9.Fig. 6 is the generalized section of traditional ball grid array package structure; Fig. 7 is the cut-away section schematic diagram of traditional ball grid array package structure; Fig. 8 is the chip-packaging structure structural representation during plastic packaging not as yet; Fig. 9 is the schematic diagram of internal communication mode in the encapsulating structure of detailed displayed map 6.Shown in Fig. 6-9, this encapsulating structure comprises substrate 101 and semiconductor chip 102, and in the mill, the semiconductor chip 102 general bonding agents 103 (not shown among Fig. 6, as to see also Fig. 9) that adopt are fixed on the surface of substrate 101.As shown in Figure 9, chip 102 is connected to lead pad 105 on substrate 101 upper surfaces by metal lead wire 104.The via hole 107 of this lead pad 105 by having the coat of metal 1 06 and the solder ball pads 105 of substrate 101 lower surfaces ' be connected.The solder ball pads 105 of substrate 101 lower surfaces ' on be pasted with soldered ball pin 108.Post a side of chip 102 at substrate 101, use a kind of thermosetting resin, adopt the method for injection moulding to form one deck plastic-sealed body 109, thereby finish the encapsulation of chip 102.
Above-mentioned Fig. 6 extremely encapsulating structure shown in Figure 9 generally can only encapsulate monolithic chip.Along with the raising that packaging density is required, industry has occurred as Figure 10-encapsulating structure shown in Figure 12, and it is on the basis of the ball grid array package structure of Fig. 6 to Fig. 9, on the surface of first semiconductor chip 202, paste again second semiconductor chip 202 '.Second chip 202 ' connection the same with first chip 202, link to each other with lead pad 205 on substrate 201 upper surfaces by metal lead wire.Equally, substrate 201 be pasted with first and second chips 202 and 202 ' a side, use thermosetting resin, form a plastic-sealed body 209.
This stacked encapsulating structure has solved the problem of two or more Chip Packaging in a packaging body, has improved the density of encapsulation.Yet, this encapsulating structure, in manufacture process since adopted surface adhesion chip 202 at semiconductor chip 202 ' method, bonding agent takes place in bonding process easily to stain, pollute chip surface.And this packaged type has requirement to the size of semiconductor chip, promptly stacked superincumbent second chip 202 ' can not be greater than first chip 202.
Summary of the invention
Therefore, the object of the present invention is to provide a kind ofly through improved semiconductor die package method, the encapsulating structure that produces through this method has thinner profile, and, to the size of chip without limits.
In addition, it is a kind of through improved semiconductor chip package that another object of the present invention is to provide, and this encapsulating structure has thinner profile, and, to the size of chip without limits.
According to above-mentioned purpose of the present invention, the semiconductor die package method that provides comprises the following steps:
A. prepare a substrate, be provided with lead pad at the upper surface of this substrate, lower surface is provided with solder ball pads; In addition, on the lower surface of substrate, also be provided with projection pad projection pad;
B. with first chip attach to the upper surface of described substrate;
C. with the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire;
D. post a side of described first chip at described substrate, form a plastic-sealed body;
E. on second chip, generate one group of metal coupling;
F. with described second chip attachment to the lower surface of described substrate, the metal coupling on described second chip is connected with projection pad projection pad on the described base lower surface;
G. on the solder ball pads of described base lower surface, weld the soldered ball pin.
Aforesaid semiconductor die package method, described step b-d can exchange with the order of step e-f.
Aforesaid semiconductor die package method in step f, adopts the method for the heating that refluxes that the metal coupling of described second chip is melted, to be welded on the projection pad projection pad on the described base lower surface.
Aforesaid semiconductor die package method behind described step f, also is included in the slit of metal coupling of described second chip and charges into the end towards glue.
According to another object of the present invention, the semiconductor package that provides comprises:
Substrate is provided with lead pad at the upper surface of this substrate, and lower surface is provided with solder ball pads;
First chip pastes on the upper surface of described substrate, the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire;
Plastic-sealed body is formed at the side that described substrate posts described first chip;
On the lower surface of described substrate, also be provided with projection pad projection pad; Described encapsulating structure also comprises:
Second chip has one group of metal coupling on it, described second chip attachment is at the lower surface of described substrate, and the metal coupling on described second chip is connected with projection pad projection pad on the described base lower surface;
The soldered ball pin is welded on the solder ball pads of described base lower surface.
Aforesaid semiconductor chip package also comprises second chip that the polylith structure is identical.
Aforesaid semiconductor chip package adopts the method for the heating that refluxes that the metal coupling of described second chip is melted, to be welded on the projection pad projection pad on the described base lower surface.
Aforesaid semiconductor chip package has charged into the end towards glue in the slit of the metal coupling of described second chip.
The present invention also provides another kind of semiconductor die package method, comprises the following steps:
A. prepare a substrate, the projection pad all is set, on lower surface, also be provided with solder ball pads at the upper surface and the lower surface of this substrate;
B. on first chip, generate one group of metal coupling;
C. with first chip attachment to the upper surface of described substrate, the metal coupling on described first chip is connected with projection pad on the described base lower surface;
D. on second chip, generate one group of metal coupling;
E. with described second chip attachment to the lower surface of described substrate, the metal coupling on described second chip is connected with projection pad on the described base lower surface;
F. on the solder ball pads of described base lower surface, weld the soldered ball pin.
Aforesaid semiconductor die package method is provided with lead pad on the upper surface of the described substrate for preparing, described method for packing also comprises:
With the 3rd chip attach to the upper surface of described first chip;
With the pad on described the 3rd chip respectively with described upper surface of base plate on described line line pad link to each other by metal lead wire;
Post a side of described the 3rd chip at described substrate, form a plastic-sealed body.
Aforesaid semiconductor die package method also is included in the side that described substrate posts described first chip, forms a plastic-sealed body.
Aforesaid semiconductor die package method in step c and e, adopts the method for the heating that refluxes that the metal coupling of described first chip and second chip is melted, to be welded on the projection pad on described upper surface of base plate and the lower surface.
Aforesaid semiconductor die package method also is included in the slit of metal coupling of described first chip and second chip and charges into the end towards glue.
The present invention also provides another kind of semiconductor package, comprising:
Substrate all is provided with the projection pad at the upper surface and the lower surface of this substrate, also is provided with solder ball pads on lower surface;
First chip has one group of metal coupling on it, described first chip attachment is to the upper surface of described substrate, and the metal coupling on described first chip is connected with projection pad on the described upper surface of base plate;
Second chip has one group of metal coupling on it, described second chip attachment is at the lower surface of described substrate, and the metal coupling on described second chip is connected with projection pad on the described base lower surface;
The soldered ball pin is welded on the solder ball pads of described base lower surface.
Aforesaid semiconductor chip package, the upper surface of described substrate is provided with lead pad, described encapsulating structure also comprises the 3rd chip, described the 3rd chip attach to the upper surface of described first chip, the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire.
Aforesaid semiconductor chip package adopts the method for the heating that refluxes that the metal coupling of described first chip and second chip is melted, to be welded on the projection pad on described upper surface of base plate and the lower surface.
Aforesaid semiconductor chip package has charged into the end towards glue in the slit of the metal coupling of described second chip.
Aforesaid semiconductor chip package also comprises first chip and second chip that the polylith structure is identical.
From top structure as can be seen, feature of the present invention is to have utilized substrate to carry out the encapsulation of semiconductor cake sheet in the space on two surfaces up and down simultaneously, thereby realizes thinner encapsulating structure.
Description of drawings
Below in conjunction with accompanying drawing, describe embodiments of the invention in detail, with it feature of the present invention, purpose and effect can be described better.In the accompanying drawing:
Fig. 1 is the generalized section of semiconductor chip package of the present invention;
The schematic diagram of the semiconductor chip package after each step that Fig. 2 A-E shows semiconductor die package method of the present invention is respectively finished;
Fig. 3 shows internal communication mode in the encapsulating structure of Fig. 1;
The schematic diagram of the semiconductor chip package after each step that Fig. 4 A-F shows another embodiment of semiconductor die package method of the present invention is finished;
The schematic diagram of the semiconductor chip package after each step that Fig. 5 A-E shows another embodiment of semiconductor die package method of the present invention is finished;
Fig. 6 is the generalized section of traditional ball grid array package structure;
Fig. 7 is the cut-away section schematic diagram of traditional ball grid array package structure;
Fig. 8 is the traditional die encapsulating structure structural representation during plastic packaging not as yet;
Fig. 9 is the schematic diagram of internal communication mode in the encapsulating structure of detailed displayed map 4;
Figure 10 is the generalized section of traditional multichip packaging structure;
Figure 11 is the cut-away section schematic diagram of traditional multichip packaging structure;
Figure 12 is traditional multichip packaging structure structural representation during plastic packaging not as yet.
Embodiment
At first consult Fig. 1 and Fig. 3 and describe semiconductor chip package of the present invention.Fig. 1 is the generalized section of semiconductor chip package of the present invention; Fig. 3 shows the internal communication mode in the encapsulating structure of Fig. 1.
As shown in Figure 1, semiconductor chip package of the present invention is to improve on the basis of traditional ball grid array package structure as shown in Figure 4.Therefore, this encapsulating structure includes substrate 1 and semiconductor chip 2 equally, also adopts the mode identical with traditional structure, promptly adopts bonding agent 3 (as shown in Figure 3) that semiconductor chip 2 is fixed on the upper surface of substrate 1.Bonding agent 3 can adopt epoxy resin adhesive.
Encapsulating structure of the present invention and traditional difference be, encapsulating structure of the present invention also comprise another chip 2 '.Below for clarity sake, the chip 2 that is pasted on substrate 1 upper surface is called first chip, with chip 2 ' be called second chip.Second chip 2 ' on generate one group of metal coupling 10 arranged, with second chip 2 ' on have metal coupling 10 one side towards substrate 1, paste on the lower surface of substrate 1.Simultaneously, on the lower surface of substrate 1, be provided with projection pad 11, projection pad 11 is according to the requirement that connects like this, respectively with second chip 2 ' on metal coupling 10 be connected.
When second chip 2 ' size when big, can second chip 2 ' the slit of metal coupling 10 in charge into resin 12, be also referred to as the end towards glue, so that metal coupling 10 is played a protective role.
As mentioned above, because method for packing of the present invention is second chip 2 ' the be pasted on lower surface of substrate 1, and, second chip 2 ' adopted the form of metal coupling with the electric connection mode of substrate 1, therefore, can make encapsulating structure of the present invention become littler and thinner.For the encapsulating structure of needs encapsulation polylith chip, can on the lower surface of substrate 1, paste the polylith structure chip identical with second chip.
The method for packing of semiconductor chip of the present invention below structure chart 2A-E is described.
At first, prepare a substrate 1, its structure is provided with lead pad 5 at the upper surface of this substrate 1 shown in Fig. 2 A, and lower surface is provided with solder ball pads, and lead pad 5 is connected by the via hole with coat of metal with solder ball pads; In addition, on the lower surface of substrate 1, also be provided with projection pad (not shown, can referring to Fig. 1).Secondly, first chip 2 is pasted on the upper surface of substrate 1.Bonding method can adopt epoxy resin, first chip 2 is bonded on the upper surface of substrate 1, and carry out baking-curing.
Then, utilize metal lead wire 5, the pad on first chip 2 is linked to each other with lead pad 5 on substrate 1 upper surface respectively, the two ends that are about to metal lead wire 5 are welded to respectively on the lead pad 5 of the pad of first chip 2 and substrate 1.Structure after this step is shown in Fig. 2 B.
Then, post a side of first chip, adopt traditional epoxy resin injection moulding process, form plastic-sealed body 9 at substrate 1.Structure after this step is shown in Fig. 2 C.
After first chip 2 being bonded on the substrate 1 with plastic packaging, begin to prepare second chip 2 ', earlier second chip 2 ' on, utilize known method, this chip 2 ' the surface on, use methods such as plating or deposition, generate one group of metal coupling, then, use the mode of high temperature reflux weldering, make the metal coupling fusing of second chip,, metal coupling is linked to each other with projection pad on substrate 1 lower surface second chip 2 ' mount on the lower surface of substrate 1.Structure after this step is shown in Fig. 2 D.
At last, on the solder ball pads on the lower surface of substrate 1, welding soldered ball pin 8.This welding also can adopt the method for the heating that refluxes to realize.
In addition, if second chip 2 ' size bigger, can also be with behind second chip 2 ' be welded on substrate 1 lower surface, in the slit of the metal coupling of second chip, charge into resin (being also referred to as the end), with protection metal coupling 10 towards glue.
In the above embodiments, first chip is the upper surface that pastes substrate in the mode of ball grid array, and second chip is the lower surface that pastes substrate in the mode of flip chip bonding.In a further embodiment, first chip also can paste the upper surface of substrate in the mode of flip chip bonding.Show each step of this embodiment by production order as Fig. 5 A-5F.In the embodiment shown in fig. 5, on the upper surface of substrate 501, two chips (being called first chip 502 and the 3rd chip 502 ＂) have been mounted, second chip 502 ' paste on the lower surface of substrate 501 in the mode of flip chip bonding in the mode of flip chip bonding.And, on first chip 502 and the 3rd chip 502 ＂, be provided with plastic-sealed body 509.In Fig. 5, though the projection pad is not shown, should be appreciated that upper surface and the lower surface at substrate 501 all is provided with the projection pad, the projection pad of upper surface can be realized and being electrically connected of the solder ball pads of lower surface by the via hole with coat of metal.
Fig. 6 A-6E shows another embodiment of the present invention.Present embodiment is to have increased by the 3rd chip on the basis of Fig. 5, be about to first chip 602 mounts substrate 601 in the mode of flip chip bonding upper surface, then, mode (utilizing metal lead wire) with ball grid array is pasted the 3rd chip 602 ＂ on the surface of first chip 602, then as above embodiment is the same for second chip, mounts the lower surface of substrate 601 in the mode of flip chip bonding.In addition, on first chip 602 and the 3rd chip 602 ＂, plastic-sealed body 609 is set, to protect the first and the 3rd chip.
According to by specific embodiments of the invention, the present invention has been done detailed description above.But should be appreciated that the description here should not be regarded as limitation of the present invention.Be familiar with present technique field person, understood thought of the present invention and spirit after, can make some variation or modification on this basis, and not need creative work.For example, the upper surface of above-mentioned substrate all is relative with lower surface; Pasting the order of first chip and second chip also can exchange.In the embodiment shown in fig. 8, the quantity of the chip of pasting by the flip chip bonding mode can increase, and the installation site can be the upper surface of substrate, also can be the lower surface of substrate.On the chip that every flip chip bonding mode is pasted, another chip block is upward pasted in the mode of metal lead wire in its surface more in theory.Therefore, protection scope of the present invention should be limited by appending claims.
Claims (18)
1, a kind of semiconductor die package method comprises the following steps:
A. prepare a substrate, be provided with lead pad at the upper surface of this substrate, lower surface is provided with solder ball pads; In addition, on the lower surface of substrate, also be provided with projection pad projection pad;
B. with first chip attach to the upper surface of described substrate;
C. with the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire;
D. post a side of described first chip at described substrate, form a plastic-sealed body;
E. on second chip, generate one group of metal coupling;
F. with described second chip attachment to the lower surface of described substrate, the metal coupling on described second chip is connected with projection pad projection pad on the described base lower surface;
G. on the solder ball pads of described base lower surface, weld the soldered ball pin.
2. semiconductor die package method as claimed in claim 1 is characterized in that, described step b-d can exchange with the order of step e-f.
3. semiconductor die package method as claimed in claim 1 or 2 is characterized in that, in step f, adopts the method for the heating that refluxes that the metal coupling of described second chip is melted, to be welded on the projection pad projection pad on the described base lower surface.
4. semiconductor die package method as claimed in claim 1 or 2 is characterized in that, behind described step f, also is included in the slit of metal coupling of described second chip and charges into the end towards glue.
5. semiconductor package comprises:
Substrate is provided with lead pad at the upper surface of this substrate, and lower surface is provided with solder ball pads;
First chip pastes on the upper surface of described substrate, the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire;
Plastic-sealed body is formed at the side that described substrate posts described first chip;
It is characterized in that,
On the lower surface of described substrate, also be provided with projection pad projection pad; Described encapsulating structure also comprises:
Second chip has one group of metal coupling on it, described second chip attachment is at the lower surface of described substrate, and the metal coupling on described second chip is connected with projection pad projection pad on the described base lower surface:
The soldered ball pin is welded on the solder ball pads of described base lower surface.
6. semiconductor chip package as claimed in claim 5 is characterized in that, also comprises second chip that the polylith structure is identical.
7. semiconductor chip package as claimed in claim 5 is characterized in that, adopts the method for the heating that refluxes that the metal coupling of described second chip is melted, to be welded on the projection pad projection pad on the described base lower surface.
8. semiconductor chip package as claimed in claim 5 is characterized in that, has charged into the end towards glue in the slit of the metal coupling of described second chip.
9. a semiconductor die package method comprises the following steps:
A. prepare a substrate, the projection pad all is set, on lower surface, also be provided with solder ball pads at the upper surface and the lower surface of this substrate;
B. on first chip, generate one group of metal coupling;
C. with first chip attachment to the upper surface of described substrate, the metal coupling on described first chip is connected with projection pad on the described base lower surface;
D. on second chip, generate one group of metal coupling;
E. with described second chip attachment to the lower surface of described substrate, the metal coupling on described second chip is connected with projection pad on the described base lower surface;
F. on the solder ball pads of described base lower surface, weld the soldered ball pin.
10. semiconductor die package method as claimed in claim 9 is characterized in that, on the upper surface of the described substrate for preparing lead pad is set, and described method for packing also comprises:
With the 3rd chip attach to the upper surface of described first chip;
With the pad on described the 3rd chip respectively with described upper surface of base plate on described line line pad link to each other by metal lead wire;
Post a side of described the 3rd chip at described substrate, form a plastic-sealed body.
11. semiconductor die package method as claimed in claim 9 is characterized in that, also is included in the side that described substrate posts described first chip, forms a plastic-sealed body.
12. semiconductor die package method as claimed in claim 9, it is characterized in that, in step c and e, adopt the method for the heating that refluxes that the metal coupling of described first chip and second chip is melted, to be welded on the projection pad on described upper surface of base plate and the lower surface.
13. semiconductor die package method as claimed in claim 9 is characterized in that, also is included in the slit of metal coupling of described first chip and second chip and charges into the end towards glue.
14. a semiconductor package is characterized in that, comprising:
Substrate all is provided with the projection pad at the upper surface and the lower surface of this substrate, also is provided with solder ball pads on lower surface;
First chip has one group of metal coupling on it, described first chip attachment is to the upper surface of described substrate, and the metal coupling on described first chip is connected with projection pad on the described upper surface of base plate;
Second chip has one group of metal coupling on it, described second chip attachment is at the lower surface of described substrate, and the metal coupling on described second chip is connected with projection pad on the described base lower surface;
The soldered ball pin is welded on the solder ball pads of described base lower surface.
15. semiconductor chip package as claimed in claim 14, it is characterized in that, the upper surface of described substrate is provided with lead pad, described encapsulating structure also comprises the 3rd chip, described the 3rd chip attach to the upper surface of described first chip, the pad on described first chip respectively with described upper surface of base plate on described lead pad link to each other by metal lead wire.
16. as claim 14 or 15 described semiconductor chip packages, it is characterized in that, adopt the method for the heating that refluxes that the metal coupling of described first chip and second chip is melted, to be welded on the projection pad on described upper surface of base plate and the lower surface.
17. as claim 14 or 15 described semiconductor chip packages, it is characterized in that, in the slit of the metal coupling of described second chip, charged into the end towards glue.
18, as claim 14 or 15 described semiconductor chip packages, it is characterized in that, also comprise first chip and second chip that the polylith structure is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021108552A CN1257540C (en) | 2002-02-10 | 2002-02-10 | Semiconductor chip package method and its package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021108552A CN1257540C (en) | 2002-02-10 | 2002-02-10 | Semiconductor chip package method and its package structure |
Publications (2)
| Publication Number | Publication Date |
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| CN1438684A true CN1438684A (en) | 2003-08-27 |
| CN1257540C CN1257540C (en) | 2006-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021108552A Expired - Lifetime CN1257540C (en) | 2002-02-10 | 2002-02-10 | Semiconductor chip package method and its package structure |
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| Country | Link |
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| CN (1) | CN1257540C (en) |
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| CN101609825A (en) * | 2008-06-18 | 2009-12-23 | 三星电子株式会社 | Prefabricated lead frame and utilize its bonding method |
| CN103515252A (en) * | 2012-06-21 | 2014-01-15 | 新科金朋有限公司 | Semiconductor device and method of forming an embedded SOP fan-out package |
| CN105932017A (en) * | 2016-05-19 | 2016-09-07 | 苏州捷研芯纳米科技有限公司 | Ultrathin 3D-packaged semiconductor device and processing method thereof and semi-finished product in processing method |
| WO2016145852A1 (en) * | 2015-03-16 | 2016-09-22 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and chip packaging structure |
| CN106571350A (en) * | 2015-10-12 | 2017-04-19 | 三星电子株式会社 | Data storage device and electronic device including the same |
| CN106744647A (en) * | 2016-12-20 | 2017-05-31 | 苏州晶方半导体科技股份有限公司 | MEMS chip encapsulating structure and method for packing |
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2002
- 2002-02-10 CN CNB021108552A patent/CN1257540C/en not_active Expired - Lifetime
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| CN101609825A (en) * | 2008-06-18 | 2009-12-23 | 三星电子株式会社 | Prefabricated lead frame and utilize its bonding method |
| CN103515252A (en) * | 2012-06-21 | 2014-01-15 | 新科金朋有限公司 | Semiconductor device and method of forming an embedded SOP fan-out package |
| CN103515252B (en) * | 2012-06-21 | 2018-01-30 | 新科金朋有限公司 | Form the semiconductor devices and method of embedded SOP fan-out packages |
| US10217702B2 (en) | 2012-06-21 | 2019-02-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SoP fan-out package |
| WO2016145852A1 (en) * | 2015-03-16 | 2016-09-22 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and chip packaging structure |
| US10276540B2 (en) | 2015-03-16 | 2019-04-30 | China Wafer Level Csp Co., Ltd. | Chip packaging method and chip packaging structure |
| CN106571350A (en) * | 2015-10-12 | 2017-04-19 | 三星电子株式会社 | Data storage device and electronic device including the same |
| CN106571350B (en) * | 2015-10-12 | 2021-07-02 | 三星电子株式会社 | Data storage device and electronic device including the same |
| CN105932017A (en) * | 2016-05-19 | 2016-09-07 | 苏州捷研芯纳米科技有限公司 | Ultrathin 3D-packaged semiconductor device and processing method thereof and semi-finished product in processing method |
| CN106744647A (en) * | 2016-12-20 | 2017-05-31 | 苏州晶方半导体科技股份有限公司 | MEMS chip encapsulating structure and method for packing |
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| CN1257540C (en) | 2006-05-24 |
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