CN1423402A - Control device for zero-voltage conversion step-up power factor correcting circuit - Google Patents
Control device for zero-voltage conversion step-up power factor correcting circuit Download PDFInfo
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- CN1423402A CN1423402A CN01132303A CN01132303A CN1423402A CN 1423402 A CN1423402 A CN 1423402A CN 01132303 A CN01132303 A CN 01132303A CN 01132303 A CN01132303 A CN 01132303A CN 1423402 A CN1423402 A CN 1423402A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
A control device for zero-voltage conversion step-up power factor correcting circuit includes main source/drain voltage detection circuit, PWM comparator circuit and main assistant drive pulse distribution circuit; after detected by its detecting circuit, the VDSMAIN outputs ZVS, when VDSMAIN is low, ZVS is at low or high level, conversion of which is decided by logic circuit properties in main assistance drive pulse distribution circuit;PWM comparator circuit generates DRV signal with duty ratio of D2 and the pulse distribution circuit realizes making up assist drive signal VTzvt and main drive signal VTmain, so to satisfy sum of VGSZVT=DRV.ZVS and VGSMain=DRV.ZVS:VGSZVT+VGsmain=DRV.
Description
Technical field
This explanation relates to the control circuit that zero-voltage conversion step-up power factor is proofreaied and correct (ZVT Boost PFC) circuit, is specifically related to be responsible for and assist the distribution control of pipe driving pulse duty ratio.
Background technology
Improve switching frequency can deperm size of devices and weight, therefore be one of important directions of electronic power switch converter technique development always, yet when high switching frequency, EMI problem when the main diode of BoostPFC circuit turn-offs and the switching loss problem of main switch become more serious, the hard switching technology is obviously incompatible, therefore proposed ZVT Boost pfc circuit and control technology thereof, U.S. Unitrode company has developed special integrated circuit UC3855A/B for this circuit.
Fig. 1 is a ZVT Boost pfc circuit schematic diagram.This circuit comprises a Boost pfc circuit, by rectifier bridge, and main inductance L, main MOSFET pipe VTmain, main diode VD1, output filter capacitor Co constitutes; And a resonant capacitance Cr branch road, one VD3 assists MOSFET to manage the branch road that the VTzvt series connection constitutes by resonant inductance Lr, and these two branch roads all are connected in parallel on the drain-source utmost point two ends of VTmain; In the second branch road, one of Lr terminates at the drain electrode of VTmain, the anode of another termination VD3, and the negative electrode of VD3 connects the drain electrode of VTzvt, and the source electrode of VTzvt connects the source electrode of VTmain; Also be connected to a diode VD2 between the negative electrode of the anode of VD3 and VD1, the anode of VD2 connects the VD3 anode, and the negative electrode of VD2 connects the VD3 negative electrode;
The auxilliary pipe of first conducting VTzvt before VTmain is responsible in conducting, make Lr, Cr resonance, the electric current of VD1 is limited by Lr, and linear transitions is to Lr place branch road, improved the electromagnetic interference (EMI) problem that reverse recovery caused of VD1, when the Cr two ends, when promptly the drain-source terminal voltage resonance of VTmain arrived zero, conducting VTmain turn-offed VTzvt simultaneously, VTmain is that no-voltage is opened like this, is called the ZVT method.
Fig. 2 is the theory diagram of the special integrated circuit UC3855A/B of Unitrode company exploitation.This chip adopts Average Current Control Method, mainly contains outer voltage, current inner loop, and driving pulse distributes parts such as link.Outer voltage wherein, current inner loop has constituted the control loop of ZVTBoost pfc circuit.
Fig. 3 is the person in charge that provides of UC3855A/B chip and PWM (pulse-width modulation) the driving pulse schematic diagram of auxilliary pipe.Wherein modulating wave is the output CAO of electric current loop, for analyzing its operation principle, might as well be made as a direct current level, and carrier wave is triangular wave CT; The crest of CT is t0 constantly in the one-period, and trough is t1 constantly, and next crest is t2 constantly, and therefore [t0, t1] is the trailing edge of CT, and [t1, t2] is the rising edge of CT, and in UC3855A/B, if the cycle of CT is Ts, then [t0, t1] is 6%Ts; The intersection point of CAO and CT is respectively t3, t4; V
GS ZVTBe auxilliary pipe driving pulse, its conducting duty ratio is D
ZVT, V
GS MAINFor being responsible for driving pulse, its conducting duty ratio is D
MAIN, the conducting duty ratio sum of the person in charge and auxilliary pipe is D1.
The characteristics of summing up above-mentioned driving pulse distribution are as follows:
1. auxilliary pipe is in t0 conducting constantly;
2.D
ZVT＜6％Ts；
3.D1＞6％Ts；
By analyzing the operation principle of ZVT Boost pfc circuit, can obtain following formula:
D1＝(Vco-Vac(t))/Vco
---Vac (t) expression exchanges the instantaneous value of input Vac after rectification;
---Vco represents output voltage, i.e. voltage in the load;
Like this, because of being subjected to the restriction of characteristics 3, the maximum of Vac can not be too high, and as when Vco gets 400VDC, the maximum of Vac can not be higher than 400* (1-6%)=376VDC, and the effective value of Vac can not be higher than 376/1.414=266Vac.So only can satisfy the basic demand (220VAC+20%) of electrical network, also confirmed by the circuit design debugging in the test, when input voltage increased again, the control ring of UC3855A/B chip must be adjusted and not come over, and analysis chart 2 as can be known, CAO may be lower than 1V, thereby the blockade driving pulse causes driving pulse to be lost, and this has caused input current to vibrate in the peak value section, inductance L is sent ear-piercing noise, and this cannot accept in product.Certainly we can solve by improving Vco, but this need increase the voltage stress of power device, in fact 400VDC is not had allowance (to be generally 500V as being responsible for auxilliary pipe for suitable power device substantially, main diode is generally 600V, output filter capacitor is generally 450V), wish that Vco also is less than 400VDC during actual the use, so just do not satisfied the basic demand of electrical network.Retrieve domestic and international patent, do not see solution as yet at above problem.And to select ZVT Boost pfc circuit for use, just must fundamentally address these problems.
Summary of the invention
Technical problem to be solved by this invention is exactly to overcome the deviation that exists in the control of ZVT Boost pfc circuit main control chip in the prior art, cause the AC-input voltage peak value can not too high shortcoming, input current peak value section vibration when the AC-input voltage peak value that exists in the solution prior art is high, the noisy problem of inductance L.
Illustrate in the background technology part: the intersection point of modulating wave CAO and carrier wave CT is respectively t3, t4, if Dui Ying duty ratio is D2 during this period of time, the principle that produces from the PWM driving pulse as can be seen, the driving pulse duty ratio sum of the person in charge that D2 needs just and auxilliary pipe.The main points of technical solution of the present invention are that the conducting of VTzvt is constantly postponed till t3 by t0, conducting VTmain again when VTzvt turn-offs, VTmain turn-offs when t4, so just satisfies the ZVT condition, and makes that the conducting duty ratio sum of VTmain and VTzvt is D2 but not D1.Can realize by logical circuit; This part logical circuit also can be built with the discrete element device, also can be integrated in the control chip and go.
Technical solution of the present invention is as follows: the present invention includes and be responsible for drain-source terminal voltage testing circuit, PWM comparator circuit and be responsible for auxilliary pipe driving pulse distributor circuit; Be responsible for drain-source terminal voltage V
DSMAINOutput detection signal ZVS after being responsible for the detection of drain-source terminal voltage testing circuit works as V
DS MAINWhen low, ZVS is a low level, otherwise is high level; The conversion value of high-low level is by the logical circuit characteristic decision of being responsible in the auxilliary pipe driving pulse distributor circuit; The PWM comparator circuit, producing duty ratio is the DRV signal of D2; Be responsible for auxilliary pipe driving pulse distributor circuit and realize constructing auxilliary pipe drive signal VTzvt and being responsible for drive signal VTmain, satisfy following three conditions from DRV:
A, auxilliary pipe drive pulse signal: V
GSZVT=DRVZVS,
B, person in charge drive pulse signal: V
GSMAIN=DRV Z VS,
C, both sums: V
GSZVT+ V
GSMAIN=DRV.
Adopt technical scheme of the present invention, when Vco dropped to 380VDC, input line voltage maximum still can surpass 275VAC (220VAC+25%), even peak value surpasses 380VDC, circuit also can operate as normal, and input current is without any vibration, and boost inductance does not have noise.And adopt same main circuit and sample circuit structure, former UC3855A/B control circuit scheme Vco during for 400VDC input line voltage maximum can only arrive 266VAC, high the more described problem of background technology part will appear.
Description of drawings Fig. 1 is a ZVT Boost pfc circuit schematic diagram.Fig. 2 is the theory diagram of the special integrated circuit UC3855A/B of Unitrode company exploitation.Fig. 3 is the person in charge that provides of UC3855A/B chip and the PWM driving pulse of auxilliary pipe.Fig. 4 is a theory diagram of the present invention.Fig. 5 is a kind of realization physical circuit figure of the present invention.Fig. 6 is the circuit theory diagrams of 103 (a) partial function among a kind of Fig. 5 of realization.
Embodiment
Fig. 1, Fig. 2, Fig. 3 are in the partly existing corresponding explanation of background technology.
Fig. 4 is for realizing theory diagram of the present invention: be responsible for drain-source terminal voltage testing circuit 101, V
DS MAINFor being responsible for the drain-source terminal voltage, ZVS is its detection signal, works as V
DS MAINWhen low, ZVS is a low level, otherwise is high level, and the conversion value of high-low level is by the logical circuit characteristic decision of being responsible in the auxilliary pipe driving pulse distributor circuit 103; It is the DRV signal of D2 that PWM comparator circuit 102 produces duty ratio; Be responsible for auxilliary pipe driving pulse distributor circuit 103 and be the circuit of realization, satisfy following three conditions from DRV structure auxilliary pipe drive signal VTzvt and person in charge's drive signal VTmain:
1, auxilliary pipe drive signal: V
GSZVT=DRVZVS,
2, be responsible for drive signal: V
GSMAIN=DRV Z VS,
3, both sums: V
GSZVT+ V
GSMAIN=DRV.
Fig. 5 is for realizing a kind of physical circuit schematic diagram of the present invention: be responsible for drain-source terminal voltage testing circuit 101 and be implemented as follows: diode cathode connects person in charge's drain terminal, and anode meets ZVS, and accessory power supply Vcc meets ZVS through resistance, and electric capacity is connected across between ZVS end and the ground;
Have only Schmidt's comparator in the PWM comparator circuit 102, inverting input meets modulating wave CAO, and in-phase input end is carried ripple CT, and output signal is DRV;
Being responsible for auxilliary pipe driving pulse distributor circuit 103 (a) comprising: two inputs of the first NAND gate NAND1 meet ZVS and DRV respectively, the output of the first NAND gate NAND1 connects two inputs of the second NAND gate NAND2, and the second NAND gate NAND2 is output as the driving pulse of auxilliary pipe; Two inputs of the 3rd NAND gate NAND3 meet output and the DRV of the first NAND gate NAND1 respectively, and the output of the 3rd NAND gate NAND3 connects two inputs of the 4th NAND gate NAND4, and the 4th NAND gate NAND4 is output as the person in charge's driving pulse; First electric capacity is connected across between the output and ground of the first NAND gate NAND1, and second electric capacity is connected across between the output and ground of the 3rd NAND gate NAND3.Described 2 electric capacity are the anti-shake usefulness of filtering, and capacitance can be obtained smaller.The accessory power supply Vcc that is responsible for drain-source terminal voltage testing circuit 101 provides a level conversion to ZVS, therefore preferably identical with the auxilliary logic chip power supply of managing among driving pulse distributor circuit 103 (a) of the person in charge, the withstand voltage Vco that is greater than of diode reverse of described person in charge's drain-source terminal voltage testing circuit 101.
Fig. 6 is circuit theory Figure 103 (b) of 103 (a) partial function among a kind of Fig. 5 of realization: first with the door AND1 two inputs meet ENA signal and DRV respectively, two inputs of the first NAND gate NAND1 all meet ZVS, two inputs of the second NAND gate NAND2 all connect the output of the first NAND gate NAND1, second with two inputs of door AND2 connect respectively first with the door output of AND1 and the output of the first NAND gate NAND1, the 3rd with two inputs of door AND3 connect respectively first with the door output of AND1 and the output of the second NAND gate NAND2, and the 3rd be output as the driving pulse of auxilliary pipe with door AND3, and the second NAND gate NAND2 is output as the person in charge's driving pulse.First resistance be connected across first and the door AND1 output and ground between, second resistance is connected across between the output and ground of the first NAND gate NAND1, described two resistance are the anti-shake usefulness of filtering, resistance value can obtain bigger.
103 (a) are with the difference of two kinds of circuit of 103 (b); before a kind of realizations simple, as long as a slice 4 tunnel NAND gate, though the back a kind of both needed and; need NAND gate again; more complicated, but can integrated ENA signal, when the ENA signal is low level; block driving pulse; it is too high to can be used for output voltage in conjunction with other circuit, and input current is excessive, short circuit or the like protection.
If the circuit 103 (a) that the control loop of described UC3855 (A/B) part and the technical program can be proposed or (b) be integrated into single chip is very succinct.Even but do not have integrated at present, also can utilize the control loop (providing CT and CAO signal, identical) of UC3854 (A/B) to add the control circuit that the driving pulse distributor circuit described in this programme constitutes ZVT Boost pfc circuit with the control loop principle of UC3855 (A/B).Consider from the convenient angle of using, (its duty ratio is D3 can also directly to drive output with UC3854 (A/B), be [t1, the t4] among Fig. 3) replace DRV, just the output DRV with PWM comparator circuit 102 parts among Fig. 4 directly uses UC3854 (A/B) to drive the output replacement.Can see, the line voltage peak value is higher when importing, require D2＜6% o'clock, D3 can＜6%, control ring can adjust, can not cause confusion, certainly this can bring new problem, and promptly during the civil power zero passage, the current waveform distortion is more serious, the problem of input current peak value section vibration when the relative voltage peak value is high, but acceptable.
Claims (5)
1, a kind of control device of zero-voltage conversion step-up power factor correcting circuit comprises and is responsible for drain-source terminal voltage testing circuit (101), PWM comparator circuit (102) and is responsible for auxilliary pipe driving pulse distributor circuit (103); Be responsible for drain-source terminal voltage V
DS MAINOutput detection signal ZVS after being responsible for drain-source terminal voltage testing circuit (101) detection works as V
DS MAINWhen low, ZVS is a low level, otherwise is high level; The conversion value of high-low level is by the logical circuit characteristic decision of being responsible in the auxilliary pipe driving pulse distributor circuit (103); PWM comparator circuit (102), producing duty ratio is the DRV signal of D2; Be responsible for the lead signal circuit of auxilliary pipe driving pulse distributor circuit (103) realization, satisfy following three condition: a, auxilliary pipe drive pulse signal: V from DRV structure auxilliary pipe drive signal VTzvt and person in charge's drive signal VTmain
GSZVT=DRVZVS, b, person in charge drive pulse signal: V
GSMAIN=DRV Z VS, both sums of c: V
GSZVT+ V
GSMAIN=DRV.
2, the control device of a kind of zero-voltage conversion step-up power factor correcting circuit according to claim 1, it is characterized in that described Guan Fuguan driving pulse distributor circuit (103) comprising: two inputs of the first NAND gate NAND1 meet ZVS and DRV respectively, the output of the first NAND gate NAND1 connects two inputs of the second NAND gate NAND2, and the second NAND gate NAND2 is output as the driving pulse of auxilliary pipe; Two inputs of the 3rd NAND gate NAND3 meet output and the DRV of the first NAND gate NAND1 respectively, and the output of the 3rd NAND gate NAND3 connects two inputs of the 4th NAND gate NAND4, and the 4th NAND gate NAND4 is output as the person in charge's driving pulse.
3, the control device of a kind of zero-voltage conversion step-up power factor correcting circuit according to claim 2, it is characterized in that described Guan Fuguan driving pulse distributor circuit (103) also comprises: first electric capacity is connected across between the output and ground of the first NAND gate NAND1, and second electric capacity is connected across between the output and ground of the 3rd NAND gate NAND3; Described 2 electric capacity are the anti-shake usefulness of filtering.
4, the control device of a kind of zero-voltage conversion step-up power factor correcting circuit according to claim 1, it is characterized in that described Guan Fuguan driving pulse distributor circuit (103) comprising: first with the door AND1 two inputs meet ENA signal and DRV respectively, two inputs of the first NAND gate NAND1 all meet ZVS, two inputs of the second NAND gate NAND2 all connect the output of the first NAND gate NAND1, second with two inputs of door AND2 connect respectively first with the door output of AND1 and the output of the first NAND gate NAND1, the 3rd with two inputs of door AND3 connect respectively first with the door output of AND1 and the output of the second NAND gate NAND2, and the 3rd be output as the driving pulse of auxilliary pipe with door AND3, and the second NAND gate NAND2 is output as the person in charge's driving pulse.
5, the control device of a kind of zero-voltage conversion step-up power factor correcting circuit according to claim 4, it is characterized in that described Guan Fuguan driving pulse distributor circuit (103) also comprises: first resistance be connected across first and the door AND1 output and ground between, second resistance is connected across between the output and ground of the first NAND gate NAND1, and described two resistance are the anti-shake usefulness of filtering.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011323035A CN100349371C (en) | 2001-11-22 | 2001-11-22 | Control device for zero-voltage conversion step-up power factor correcting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011323035A CN100349371C (en) | 2001-11-22 | 2001-11-22 | Control device for zero-voltage conversion step-up power factor correcting circuit |
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| CN1423402A true CN1423402A (en) | 2003-06-11 |
| CN100349371C CN100349371C (en) | 2007-11-14 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425798B (en) * | 2007-10-30 | 2011-09-07 | 比亚迪股份有限公司 | Dynamic current equalizing method and device for parallel IGBT |
| CN110649802A (en) * | 2019-08-22 | 2020-01-03 | 东莞理工学院 | Single-stage resonant AC-DC power factor correction conversion device and correction method thereof |
| CN112865510A (en) * | 2021-01-18 | 2021-05-28 | 华中科技大学 | Pulse width period control system and method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI565204B (en) * | 2015-05-21 | 2017-01-01 | Dynamic detection regulator boost power factor correction control device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3097886B2 (en) * | 1993-04-15 | 2000-10-10 | サンケン電気株式会社 | Step-up chopper type switching power supply |
| US5543704A (en) * | 1994-06-08 | 1996-08-06 | Telefonaktiebolaget Lm Ericsson | Pulse width modulated DC-to-DC boost converter |
| US6051961A (en) * | 1999-02-11 | 2000-04-18 | Delta Electronics, Inc. | Soft-switching cell for reducing switching losses in pulse-width-modulated converters |
| US6169668B1 (en) * | 1999-10-27 | 2001-01-02 | Space Systems/Loral, Inc. | Zero voltage switching isolated boost converters |
| SE520419C2 (en) * | 2000-03-24 | 2003-07-08 | Emerson Energy Systems Ab | Cutting circuit for zero voltage switch |
| CN1144347C (en) * | 2001-05-16 | 2004-03-31 | 艾默生网络能源有限公司 | Zero-voltage zero-current soft-switch converter |
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- 2001-11-22 CN CNB011323035A patent/CN100349371C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425798B (en) * | 2007-10-30 | 2011-09-07 | 比亚迪股份有限公司 | Dynamic current equalizing method and device for parallel IGBT |
| CN110649802A (en) * | 2019-08-22 | 2020-01-03 | 东莞理工学院 | Single-stage resonant AC-DC power factor correction conversion device and correction method thereof |
| CN112865510A (en) * | 2021-01-18 | 2021-05-28 | 华中科技大学 | Pulse width period control system and method |
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| CN100349371C (en) | 2007-11-14 |
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