CN1405865A - Method for manufacturing film transistor plane indicator - Google Patents
Method for manufacturing film transistor plane indicator Download PDFInfo
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- CN1405865A CN1405865A CN 01133182 CN01133182A CN1405865A CN 1405865 A CN1405865 A CN 1405865A CN 01133182 CN01133182 CN 01133182 CN 01133182 A CN01133182 A CN 01133182A CN 1405865 A CN1405865 A CN 1405865A
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Abstract
The manufacturing procedures includes following steps. (1) The first mask restricts the figure of the first metal layer/grid electrode insulation layer/non-silicon crystal layer. (2) The second mask restricts the formation of the passivation layer and the etching stopper. (3) The third mask restricts the formation of the source/drain electrode. (4) The fourth mask restricts the formation of the figure element electrode. The invented manufacturing process only needs to apply the said four masks so as to simplify the process for manufacturing the plain diaply of the thin film transistors.
Description
Technical field
The present invention relates to a kind of manufacture method of flat-panel screens, particularly relate to a kind of manufacture method of Thin Film Transistor-LCD.
Background technology
Figure 1A to Fig. 1 D shows the existing method of manufacturing thin film transistor that is used for LCD.With reference to Figure 1A, at first, be shaped as a gate electrode 2 in a transparency carrier 1 upper limit, form an insulating barrier 3 cover gate electrodes 2 again.Then, on insulating barrier 3, form amorphous silicon (amorphoussilicon) layer 40 and silicon nitride layer 50 in regular turn.With reference to Figure 1B, limit etches both silicon nitride layer 50, to form an etch stop layer (etching stopper) 5.With reference to Fig. 1 C, on etch stop layer 5 and amorphous silicon layer 40, form a doped silicon layer 6 (for example mixing the amorphous silicon layer of n type impurity) again.With reference to Fig. 1 D, then form a metal level, limit etch metal layers again and formation source/drain electrode 7,8 forms a protective layer 9 at last.In etching process, part metals layer and etched the removing of doped silicon layer 6 meetings, and etch stop layer 5 avoids suffering etching to destroy in order to protection amorphous silicon layer 40.
Although above-mentioned conventional method is arranged in order to make thin-film transistor, the process for making of thin-film transistor still has improved space.
Summary of the invention
The object of the present invention is to provide a kind of method of manufacturing thin film transistor, only need the manufacture craft of four road photomasks, simplify the manufacture method of thin-film transistor thus.
The object of the present invention is achieved like this, and a kind of manufacture method of film transistor plane indicator promptly is provided, and comprising: a substrate (a) is provided, forms one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn on aforesaid substrate; (b) limit the figure of above-mentioned semiconductor layer, first insulating barrier and first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed on an end of above-mentioned scan line; (c) form a protective layer, be covered on above-mentioned scan line, gate pad, grid and the substrate; (d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad, and above-mentioned semiconductor layer is exposed in above-mentioned first, second and third opening; (e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn; (f) pattern of above-mentioned second conductive layer of qualification and above-mentioned doped silicon layer, to form a holding wire, an and formation one source pole and a drain electrode above above-mentioned grid, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned source electrode contacts with the semiconductor layer of above-mentioned grid by above-mentioned first and second openings respectively with the doped silicon layer of drain electrode, and above-mentioned holding wire is perpendicular to above-mentioned scan line; (g) pattern of semiconductor layer and insulating barrier in the above-mentioned gate pad of qualification removes above-mentioned semiconductor layer and insulating barrier in above-mentioned the 3rd opening, and above-mentioned first conductive layer is exposed in above-mentioned the 3rd opening; (h) form a transparent electrode layer on aforesaid substrate, and cover above-mentioned source electrode, drain electrode and above-mentioned gate pad; And (i) limit above-mentioned transparent electrode layer, to form a pixel electrode.
The present invention also provides a kind of manufacture method of film transistor plane indicator, comprising: a substrate (a) is provided, forms one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn on aforesaid substrate; (b) limit the figure of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line; (c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate; (d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening above above-mentioned gate pad; (e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn; (f) limit the pattern of above-mentioned second conductive layer and above-mentioned doped silicon layer, above above-mentioned grid, form an island structure, and above-mentioned doped silicon layer is respectively by above-mentioned first and second openings and contact with the semiconductor layer of above-mentioned grid; (g) pattern of the semiconductor layer and first insulating barrier in the above-mentioned gate pad of qualification is exposed in above-mentioned the 3rd opening above-mentioned first conductive layer; (i) on aforesaid substrate, form a transparent electrode layer, and cover above-mentioned second conductive layer; And (j) limit above-mentioned transparent electrode layer, above-mentioned second conductive layer and above-mentioned doped silicon layer, in above-mentioned island structure, form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned channel is positioned at above-mentioned grid top, above-mentioned transparent electrode layer also forms a pixel electrode, and couples above-mentioned drain electrode.
The present invention also provides a kind of manufacture method of Thin Film Transistor-LCD, comprising: a substrate (a) is provided, forms one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn on aforesaid substrate; (b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line; (c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate; (d) pattern of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad; (e) form one second conductive layer, limit the pattern of above-mentioned second conductive layer, on above-mentioned protective layer, form a holding wire, the vertical above-mentioned scan line of above-mentioned holding wire; (f) on above-mentioned holding wire and above-mentioned protective layer, form a doped silicon layer and a transparent electrode layer in regular turn, and above-mentioned doped silicon layer is connected with the semiconductor layer of above-mentioned grid via above-mentioned first and second openings; (g) limit above-mentioned transparent electrode layer and above-mentioned doped silicon layer, above above-mentioned grid, limit and form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned transparent electrode layer also forms a pixel electrode, above-mentioned pixel electrode is connected with above-mentioned drain electrode, and above-mentioned source electrode is electrically connected with above-mentioned holding wire; And (h) limit the semiconductor layer and first insulating barrier in the above-mentioned gate pad of etching, above-mentioned first conductive layer is exposed in above-mentioned the 3rd opening.
The present invention also provides a kind of manufacture method of film transistor plane indicator, comprising: a substrate (a) is provided, forms one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn on aforesaid substrate; (b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line; (c) on aforesaid substrate, form a protective layer and one second conductive layer in regular turn, and cover above-mentioned gate pad and grid; (d) pattern of above-mentioned second conductive layer of qualification and above-mentioned protective layer forms a holding wire on substrate, form one first opening and one second opening on above-mentioned grid, forms one the 3rd opening on above-mentioned gate pad; (e) form a doped silicon layer and a transparent electrode layer in regular turn on above-mentioned holding wire, above-mentioned grid and aforesaid substrate, and above-mentioned doped silicon layer contacts with above-mentioned semiconductor layer via above-mentioned first opening and above-mentioned second opening; And the pattern that (f) limits above-mentioned transparent electrode layer, above-mentioned doped layer and above-mentioned second conductive layer; above above-mentioned grid, form a drain electrode and an one source pole; being defined as a channel between above-mentioned drain electrode and the above-mentioned source electrode is exposed in the above-mentioned channel above-mentioned protective layer; above-mentioned transparent electrode layer also forms a pixel electrode, and above-mentioned pixel electrode is connected with above-mentioned drain electrode.
Furtherly, its principal character is: utilize the 1st road photomask to limit the pattern of amorphous silicon layer/gate insulator/the first metal layer; Utilize the 2nd road photomask to form protective layer (passivation layer) and island etch stop layer (etching stopper); Utilize the 3rd road photomask to limit source/drain (Source/Drain); Utilize last one photomask to limit again and form pixel electrode.
The advantage of the inventive method is that its manufacture craft only needs to use four road photomasks, to simplify the manufacturing process of film transistor plane indicator.
Description of drawings
Figure 1A～1D is the existing manufacturing process cutaway view of thin-film transistor in the flat-panel screens;
Fig. 2 A～2D is the manufacturing process top view of first embodiment of the invention;
Fig. 3 A～3D is the manufacturing process cutaway view of first embodiment of the invention;
Fig. 4 A～4D is the manufacturing process cutaway view of second embodiment of the invention;
Fig. 5 A～5D is the manufacturing process top view of third embodiment of the invention;
Fig. 6 A～6D is the manufacturing process cutaway view of third embodiment of the invention;
Fig. 7 A～7D is the manufacturing process top view of fourth embodiment of the invention;
Fig. 8 A～8D is the manufacturing process cutaway view of fourth embodiment of the invention;
Fig. 9 A～9C is the manufacturing process top view of fifth embodiment of the invention;
Figure 10 A～10C is the manufacturing process cutaway view of fifth embodiment of the invention.
Embodiment
Various preferable manufacturing process will be described in detail in following first embodiment to the, five embodiment.
Embodiment one:
Fig. 2 A～2D is the manufacturing process top view of first embodiment of the invention.Fig. 3 A～3D is the manufacturing process cutaway view of first embodiment of the invention.Among Fig. 3 A～3D, the I district is the zone at thin-film transistor place, corresponding among Fig. 2 A～2D along the section of A-A ' direction; The II district is the zone at gate pad (gate pad) structure place, corresponding among Fig. 2 A～2D along the section of B-B ' direction.Hereinafter with reference to Fig. 2 A～2D and Fig. 3 A～3D manufacture method of the present invention is described.
With reference to Fig. 2 A and Fig. 3 A, at first, on a transparency carrier 100, form one first conductive layer 101, an insulating barrier 102 in regular turn, reach semi-conductor layer 103.Limit the pattern of semiconductor layer 103, insulating barrier 102 and first conductive layer 101 again, to form one scan line DL, a gate pad DLp and a grid DLg.Gate pad DLp is formed at the end of scan line DL, and the side of grid DLg self-scanning line DL extends, and the semiconductor layer 103 of grid DLg is as the channel layer of thin-film transistor.Generally speaking, substrate 100 can be glass substrate or quartz base plate, and semiconductor layer 103 can be amorphous silicon layer, and insulating barrier 102 can be silicon oxide layer, and first conductive layer 101 is metal level, forms a gate electrode.
With reference to Fig. 2 B and Fig. 3 B, then, form a protective layer 104, be covered on above-mentioned scan line DL, grid DLg, gate pad DLp and the substrate 100.Limit the pattern of protective layer 104 again, on grid DLg, form the first opening op1 and the second opening op2,, make semiconductor layer 103 by exposing among the first opening op1, the second opening op2 and the 3rd opening op3 at gate pad DLp the 3rd opening op3.In this embodiment, protective layer 104 is by silicon nitride (SiNx) or the organic polymer material is constituted.
With reference to Fig. 2 C and Fig. 3 C, on substrate 100, form a doped silicon layer 105 and one second conductive layer 106 in regular turn.Limit the pattern of second conductive layer 106 and doped silicon layer 105,, be defined as a channel (channel) 110 between source S and the drain D, and expose semiconductor layer 103 therein to form a holding wire SL and on grid DLg, to form an one source pole S and a drain D.
The doped silicon layer 105 in source/drain electrode (S, D) electrically contacts by semiconductor layer 103 formations of first and second openings (op1, op2) with grid DLg respectively.Holding wire SL is perpendicular to scan line DL.
With reference to Fig. 2 D and Fig. 3 D, semiconductor layer 103 among the etch-gate polar cushion DLp and insulating barrier 102 are exposed among the 3rd opening op3 first conductive layer 101 of gate pad DLp.Then, a transparent electrode layer 107 is formed on the substrate 100, and covers source S, drain D and gate pad DLp.At last, limit the figure of transparent electrode layer 107, forming a pixel electrode layer PL who couples drain D respectively, with a dummy signal lines layer FS who covers source S and holding wire SL, and transparent electrode layer 107 electrically contacts with first conductive layer, 101 formations among the gate pad DLp.
In this embodiment, transparent electrode layer 107 is the ITO layer.It should be noted that: second conductive layer 106 of source/drain electrode (S, D) respectively has a sidewall in channel 110, and transparent electrode layer 107 covers the sidewall of second conductive layer 106 in channel 110.
Embodiment two:
The manufacture craft top view of second embodiment of the invention is identical with Fig. 2 A～2D sign.Fig. 4 A～4D has shown the manufacturing process cutaway view of second embodiment of the invention.First embodiment and the second embodiment maximum different are also to form an insulating barrier 202 on semiconductor layer 103, in order to protection semiconductor layer 103.In a second embodiment, identical with first embodiment name is used identical label.
With reference to Fig. 2 A and Fig. 4 A, on substrate 100, form one first conductive layer 101, one first insulating barrier 102, semi-conductor layer 103 and one second insulating barrier 202 in regular turn, and limit its pattern, to form one scan line DL, a gate pad DLp and a grid DLg.In this embodiment, second insulating barrier 202 can be silicon nitride layer.
With reference to Fig. 2 B and Fig. 4 B, form a protective layer 104 and cover on scan line DL, grid DLg, gate pad DLp and the substrate 100.Limit the pattern of the protective layer 104 and second insulating barrier 202 again; on grid DLg, form the first opening op1 and the second opening op2; at gate pad DLp the 3rd opening op3, make semiconductor layer 103 by exposing among the first opening op1, the second opening op2 and the 3rd opening op3.
With reference to Fig. 2 C and Fig. 4 C figure, on substrate 100, form a doped silicon layer 105 and one second conductive layer 106 in regular turn.Limit the pattern of second conductive layer 106 and doped silicon layer 105, forming a holding wire SL, and on grid DLg, form an one source pole S and a drain D, be defined as a channel (channel) 110 between source S and the drain D, and in wherein exposing second insulating barrier 202.
When etching second conductive layer 106 and doped silicon layer 105, be positioned at the protective layer 104 and second insulating barrier 202 between the first opening op1 and the second opening op2, as an etch stop layer (etch stop; Or be called island etch stop layer IS), avoid suffering that in order to the semiconductor layer 103 (being channel layer) of protection grid DLg etching destroys.
With reference to Fig. 2 D and Fig. 4 D, limit the semiconductor layer 103 of gate pad DLp and the pattern of first insulating barrier 102 earlier, remove the semiconductor layer 103 and first insulating barrier 102 among the 3rd opening op3, to expose first conductive layer 101 among the gate pad DLp.Then, on substrate 100, form transparent electrode layer 107, and cover source S, drain D and gate pad DLp.At last, limit the figure of transparent electrode layer 107, form a pixel electrode layer PL who couples drain D, and a dummy signal lines layer FS who covers source S and holding wire SL, and transparent electrode layer 107 and electrically contact with first conductive layer, 101 formations of gate pad DLp.
In this embodiment, on semiconductor layer 103, also form the thin silicon nitride (i.e. second insulating barrier 202) of one deck, avoid semiconductor layer 103 to be exposed to for a long time in the air thus and oxidation.
Embodiment three:
Fig. 5 A～5D shows the manufacture craft top view of third embodiment of the invention.Fig. 6 A～6D shows the manufacturing process cutaway view of third embodiment of the invention.Among Fig. 6 A～6D, the I district is the zone at thin-film transistor place, corresponding among Fig. 5 A～5D along the section of A-A ' direction; The zone at II district gate pad (gate pad) structure place, corresponding among Fig. 5 A～5D along the section of B-B ' direction.Be applied to the method for manufacturing thin film transistor of flat-panel screens hereinafter with reference to Fig. 5 A～5D and Fig. 6 A～6D explanation the present invention.
With reference to Fig. 5 A and Fig. 6 A, with Fig. 5 B and Fig. 6 B, on substrate 100 with first conductive layer 101, first insulating barrier 102, semiconductor layer 103 and protective layer 104, limit scan line DL, gate pad DLp with grid DLg.On grid DLg and gate pad DLp, form first, second, third opening op1, op2, op3 more respectively, semiconductor layer 103 is exposed.Its manufacturing process is described identical with first embodiment, so do not given unnecessary details at this.
Refer again to Fig. 5 C and Fig. 6 C, on substrate 100, form a doped silicon layer 105 and one second conductive layer 106.Then, limit the pattern of second conductive layer 106 and doped silicon layer 105, above grid, form an island structure, and form a holding wire SL in addition.Holding wire SL is perpendicular to scan line DL, and doped silicon layer 105 electrically contacts by semiconductor layer 103 formations of first, second opening (op1, op2) with grid DLg.
With reference to Fig. 5 D and Fig. 6 D, the semiconductor layer 103 among the qualification gate pad DLp and the pattern of first insulating barrier 102 are exposed among the 3rd opening op3 of gate pad DLp first conductive layer 101 earlier.Form a transparent electrode layer 107 again on substrate 100, it covers second conductive layer 106.Afterwards, limit transparent electrode layer 107, second conductive layer 106, with the pattern of doped silicon layer 105, in island structure, to form an one source pole S and a drain D.Be defined as a channel 110 between source electrode and the drain electrode, and channel 110 is positioned at directly over the grid DLg.In addition, transparent electrode layer 107 forms a pixel electrode PL, and is connected with drain D.Transparent electrode layer 107 also covers the source S among holding wire SL and the grid DLg.In addition, transparent electrode layer 107 is covering gate polar cushion DLp also, and contacts with first conductive layer 101 among the gate pad DLp by the 3rd opening op3.
In this embodiment, transparent electrode layer 107 is the ITO layer, and transparent electrode layer 107 do not cover second metal level, 106 sidewalls in the channel 110, therefore can dwindle the channel size in the thin-film transistor.
Embodiment four:
Fig. 7 A～7D shows the manufacture craft top view of fourth embodiment of the invention.Fig. 8 A～8D shows the manufacturing process cutaway view of fourth embodiment of the invention.Among Fig. 8 A～8D, the I district is the zone at thin-film transistor place, corresponding among Fig. 7 A～7D along the section of A-A ' direction; The zone at II district gate pad (gate pad) structure place, corresponding among Fig. 7 A～7D along the section of B-B ' direction.Hereinafter with reference to Fig. 7 A～7D and Fig. 8 A～8D present embodiment is described.
With reference to Fig. 7 A and Fig. 8 A, with Fig. 7 B and Fig. 8 B, on substrate 100 with first conductive layer 101, first insulating barrier 102, semiconductor layer 103 and protective layer 104, limit scan line DL, gate pad DLp with grid DLg.Form first, second, third opening op1, op2, op3 more respectively on grid DLg and gate pad DLp, semiconductor layer 103 is exposed, its manufacturing process is described identical with first embodiment, so do not given unnecessary details at this.In addition, also can form one second insulating barrier (not icon) on the semiconductor layer 103, with protection semiconductor layer 103.
With reference to Fig. 7 C figure and Fig. 8 C, on protective layer 104, form one second metal level 106, and limit the figure of holding wire SL, holding wire SL vertical scan line DL.
With reference to Fig. 7 D and Fig. 8 D, on substrate 100, form a doped layer 105 and a transparent electrode layer 107 in regular turn, and cover gate DLg and holding wire SL.Limit the pattern of transparent electrode layer 107 and doped layer 105 again, above grid, limit a drain D and one source pole S, form a channel 110 between drain D and source S.In addition, the TK1 of first of transparent electrode layer 107 covers holding wire SL, and links to each other with source S, and the doped silicon layer 105 in the source S contacts with semiconductor layer 103 via the first opening op1.The second part TK2 of transparent electrode layer 107 forms a pixel electrode PL, and links to each other with drain D, and the doped silicon layer 105 of drain D is electrically connected with semiconductor layer 103 formations via the second opening op2.
At last, remove the semiconductor layer 103 and first insulating barrier 102 in the 3rd opening, to expose first conductive layer 101 among the gate pad DLp.
Embodiment five:
Fig. 9 A～9C shows the manufacture craft top view of fifth embodiment of the invention.Figure 10 A～10C shows the manufacturing process cutaway view of fifth embodiment of the invention.Among Figure 10 A～10C, the I district is the zone at thin-film transistor place, corresponding among Fig. 9 A～9C along the section of A-A ' direction; The II district is the zone at gate pad (gatepad) structure place, corresponding among Fig. 9 A～9C along the section of B-B ' direction.Hereinafter with reference to Fig. 9 A～9C and Figure 10 A～10C manufacture method of the present invention is described.
With reference to Fig. 9 A and Figure 10 A, at first, on a substrate 100, form one first conductive layer 101, an insulating barrier 102 in regular turn, reach semi-conductor layer 103.Limit semiconductor layer 103, insulating barrier 102, and the pattern of first conductive layer 101 again, to form one scan line DL, a gate pad DLp and a grid DLg.Gate pad DLp is formed on the end of scan line DL, and the side of grid DLg self-scanning line DL is extended.Semiconductor layer 103 on the grid DLg is as the channel layer of thin-film transistor.
With reference to Fig. 9 B and Figure 10 B, on substrate 100, form a protective layer 104 and one second conductive layer 106 in regular turn, limit the pattern of second conductive layer 106 and protective layer 104 again, make it cover scan line DL, grid DLg and gate pad DLp.Second conductive layer 106 and protective layer 104 also form a holding wire SL on substrate 100, and holding wire SL vertical scan line DL.In addition; remove second conductive layer 106 and the protective layer 104 of part; on grid DLg, form the first opening op1 and the second opening op2, on gate pad DLp, form the 3rd opening op3, make semiconductor layer 103 by exposing among the first opening op1, the second opening op2 and the 3rd opening op3.
With reference to Fig. 9 C and Figure 10 C, on substrate 100, form a doped silicon layer 305 and a transparent electrode layer 107, doped silicon layer 305 is electrically connected with semiconductor layer 103 via the first opening op1 and the second opening op2.Limit the pattern of etching transparent electrode layer 107 and doped silicon layer 305 again, above grid DLg, form an one source pole S and a drain D.Be defined as a channel 110 between source S and drain D.The first part T1 of transparent electrode layer 107 is positioned on the holding wire SL, and the second portion T2 of transparent electrode layer 107 covers source S, and the third part T3 of transparent electrode layer 107 forms a pixel electrode PL, and covers drain D.At last, remove the semiconductor layer 103 and first insulating barrier 102 among the 3rd opening op3, first conductive layer 101 of gate pad DLp is exposed.
By the foregoing description one to embodiment five, the present invention proposes the manufacture method of novel film transistor plane indicator, only needs to use 4 road photomasks (embodiment five only needs 3 road photomasks) in manufacture craft.Main manufacture craft comprises: (1) forms the first metal layer/gate insulator/amorphous silicon layer; (2) form protective layer (passivation) and etch stop layer (etching stopper); (3) form source/drain (Source/Drain); (4) form pixel electrode; So can simplify the manufacturing process of film transistor plane indicator.
Though abovely disclosed the present invention in conjunction with preferred embodiment; right its is not in order to limit the present invention; any skilled personnel can do a little changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be with being as the criterion that claim was defined.
Claims (14)
1. the manufacture method of a film transistor plane indicator comprises:
(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;
(b) limit the figure of above-mentioned semiconductor layer, first insulating barrier and first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed on an end of above-mentioned scan line;
(c) form a protective layer, be covered on above-mentioned scan line, gate pad, grid and the substrate;
(d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad, and above-mentioned semiconductor layer is exposed in above-mentioned first, second and third opening;
(e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn;
(f) pattern of above-mentioned second conductive layer of qualification and above-mentioned doped silicon layer, to form a holding wire, an and formation one source pole and a drain electrode above above-mentioned grid, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned source electrode contacts with the semiconductor layer of above-mentioned grid by above-mentioned first and second openings respectively with the doped silicon layer of drain electrode, and above-mentioned holding wire is perpendicular to above-mentioned scan line;
(g) pattern of semiconductor layer and insulating barrier in the above-mentioned gate pad of qualification removes above-mentioned semiconductor layer and insulating barrier in above-mentioned the 3rd opening, and above-mentioned first conductive layer is exposed in above-mentioned the 3rd opening;
(h) form a transparent electrode layer on aforesaid substrate, and cover above-mentioned source electrode, drain electrode and above-mentioned gate pad; And
(i) limit above-mentioned transparent electrode layer, to form a pixel electrode.
2. manufacture method as claimed in claim 1, wherein, in step (i), above-mentioned transparent electrode layer also is formed on the above-mentioned holding wire, above-mentioned transparent electrode layer contacts with first conductive layer of above-mentioned gate pad via above-mentioned the 3rd opening, and above-mentioned pixel electrode layer couples above-mentioned drain electrode.
3. manufacture method as claimed in claim 1 wherein, in step (b), also forms one second insulating barrier on above-mentioned semiconductor layer, to avoid above-mentioned semiconductor layer to be exposed in the air and oxidation.
4. manufacture method as claimed in claim 3, wherein, in step (d), above-mentioned first, second and the 3rd opening also run through above-mentioned second insulating barrier, make above-mentioned semiconductor layer be exposed to above-mentioned first, second and the 3rd opening.
5. manufacture method as claimed in claim 1, wherein, second conductive layer of above-mentioned source electrode and drain electrode respectively has a sidewall and is exposed in the above-mentioned channel, and above-mentioned transparency conducting layer covers the above-mentioned sidewall of second metal level in the above-mentioned channel.
6. manufacture method as claimed in claim 1, wherein, second conductive layer of above-mentioned source electrode and drain electrode respectively has a sidewall and is exposed in the above-mentioned channel, and above-mentioned transparency conducting layer does not cover the above-mentioned sidewall of second metal level in above-mentioned source electrode and the drain electrode.
7. the manufacture method of a film transistor plane indicator comprises:
(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;
(b) limit the figure of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;
(c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate;
(d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening above above-mentioned gate pad;
(e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn;
(f) limit the pattern of above-mentioned second conductive layer and above-mentioned doped silicon layer, above above-mentioned grid, form an island structure, and above-mentioned doped silicon layer is respectively by above-mentioned first and second openings and contact with the semiconductor layer of above-mentioned grid;
(g) pattern of the semiconductor layer and first insulating barrier in the above-mentioned gate pad of qualification is exposed in above-mentioned the 3rd opening above-mentioned first conductive layer;
(i) on aforesaid substrate, form a transparent electrode layer, and cover above-mentioned second conductive layer; And
(j) limit above-mentioned transparent electrode layer, above-mentioned second conductive layer and above-mentioned doped silicon layer, in above-mentioned island structure, form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned channel is positioned at above-mentioned grid top, above-mentioned transparent electrode layer also forms a pixel electrode, and couples above-mentioned drain electrode.
8. manufacture method as claimed in claim 7; wherein; in step (a), also form one second insulating barrier; in step (b), limit the pattern of above-mentioned second insulating barrier; and when step (c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second, with the 3rd opening in.
9. manufacture method as claimed in claim 7, wherein, in step (f), above-mentioned second metal level also forms a holding wire, and in step (j), above-mentioned transparent electrode layer also forms a dummy signal lines layer and covers above-mentioned holding wire.
10. the manufacture method of a Thin Film Transistor-LCD comprises:
(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;
(b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;
(c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate;
(d) pattern of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad;
(e) form one second conductive layer, limit the pattern of above-mentioned second conductive layer, on above-mentioned protective layer, form a holding wire, the vertical above-mentioned scan line of above-mentioned holding wire;
(f) on above-mentioned holding wire and above-mentioned protective layer, form a doped silicon layer and a transparent electrode layer in regular turn, and above-mentioned doped silicon layer is connected with the semiconductor layer of above-mentioned grid via above-mentioned first and second openings;
(g) limit above-mentioned transparent electrode layer and above-mentioned doped silicon layer, above above-mentioned grid, limit and form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned transparent electrode layer also forms a pixel electrode, above-mentioned pixel electrode is connected with above-mentioned drain electrode, and above-mentioned source electrode is electrically connected with above-mentioned holding wire; And
(h) semiconductor layer and first insulating barrier in the above-mentioned gate pad of qualification etching is exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.
11. manufacture method as claimed in claim 10 is further comprising the steps of:
In step (a), also form one second insulating barrier;
In step (b), limit the pattern of above-mentioned second insulating barrier;
When step (c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second and the 3rd opening; And
In step (h), second insulating barrier in the above-mentioned gate pad of etching, semiconductor layer and first insulating barrier are exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.
12. the manufacture method of a film transistor plane indicator comprises:
(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;
(b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;
(c) on aforesaid substrate, form a protective layer and one second conductive layer in regular turn, and cover above-mentioned gate pad and grid;
(d) pattern of above-mentioned second conductive layer of qualification and above-mentioned protective layer forms a holding wire on substrate, form one first opening and one second opening on above-mentioned grid, forms one the 3rd opening on above-mentioned gate pad;
(e) form a doped silicon layer and a transparent electrode layer in regular turn on above-mentioned holding wire, above-mentioned grid and aforesaid substrate, and above-mentioned doped silicon layer contacts with above-mentioned semiconductor layer via above-mentioned first opening and above-mentioned second opening; And
(f) limit the pattern of above-mentioned transparent electrode layer, above-mentioned doped layer and above-mentioned second conductive layer; above above-mentioned grid, form a drain electrode and an one source pole; being defined as a channel between above-mentioned drain electrode and the above-mentioned source electrode is exposed in the above-mentioned channel above-mentioned protective layer; above-mentioned transparent electrode layer also forms a pixel electrode, and above-mentioned pixel electrode is connected with above-mentioned drain electrode.
13. manufacture method as claimed in claim 12 comprises that also a step (g) limits the semiconductor layer and first insulating barrier of the above-mentioned gate pad of etching, to expose above-mentioned first conductive layer.
14. manufacture method as claimed in claim 13 is further comprising the steps of:
In step (a), also form one second insulating barrier;
In step (b), limit the pattern of above-mentioned second insulating barrier;
When step (c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second, with the 3rd opening in; And
In step (g), second insulating barrier in the above-mentioned gate pad of etching, semiconductor layer and first insulating barrier are exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.
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| CN 01133182 CN1240117C (en) | 2001-09-20 | 2001-09-20 | Method for manufacturing film transistor plane indicator |
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| CN 01133182 CN1240117C (en) | 2001-09-20 | 2001-09-20 | Method for manufacturing film transistor plane indicator |
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| CN1405865A true CN1405865A (en) | 2003-03-26 |
| CN1240117C CN1240117C (en) | 2006-02-01 |
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