CN100392507C - Film transistor display assembly capable of reducing light leakage current and mfg. method thereof - Google Patents
Film transistor display assembly capable of reducing light leakage current and mfg. method thereof Download PDFInfo
- Publication number
- CN100392507C CN100392507C CNB2005100765930A CN200510076593A CN100392507C CN 100392507 C CN100392507 C CN 100392507C CN B2005100765930 A CNB2005100765930 A CN B2005100765930A CN 200510076593 A CN200510076593 A CN 200510076593A CN 100392507 C CN100392507 C CN 100392507C
- Authority
- CN
- China
- Prior art keywords
- amorphous silicon
- metal
- data line
- grid
- district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The present invention relates to a display component which comprises a grid electrode formed on a base plate, a grid electrode insulation layer covered on the grid electrode, a grid electrode amorphous silicon region, a source electrode metal region, a drain electrode metal region, a data wire metal region, a protective layer and a conducting layer, wherein the grid electrode amorphous silicon region is formed on the grid electrode insulation layer and is correspondingly positioned above the grid electrode, the source electrode metal region and the drain electrode metal region are formed on the grid electrode amorphous silicon region, the data wire metal region is formed above the grid electrode insulation layer, the data wire metal region and the drain electrode metal region are separated by an interval, the protective layer is formed on the grid electrode insulation layer and is covered on the source electrode metal region, the drain electrode metal region and the data wire metal region, the protective layer comprises a first via and a second via so that the partial surface of the data wire metal region and the partial surface of the drain electrode metal region are respectively exposed, the conducting layer is formed on the protective layer and is covered on the first via and the second via, and the conducting layer is electrically connected with the data wire metal region and the drain electrode metal region.
Description
[technical field]
The invention relates to a kind of display module and manufacture method thereof, and particularly relevant for a kind of film transistor display assembly and manufacture method thereof that reduces light leakage current.
[background technology]
General display module for example is that tft liquid crystal display module (TFT LCD) is when making, mostly adopt five road light shield processing procedures, wherein amorphous silicon (Amorphous Silicon, a-Si) layer is a kind of photaesthesia material, behind irradiation, be easy to generate photocurrent, and the shortcoming of light electric leakage is arranged.
Please refer to Fig. 1, it illustrates a kind of cut-away section synoptic diagram with the formed TFT LCD assembly of traditional five road light shield processing procedures.Utilize traditional five formed arrays of road light shield processing procedure (Array), comprise grid (made) 11, gate insulator (silicon nitride) 13, grid amorphous silicon layer 15, n type amorphous silicon layer (n+a-Si) 16 and source electrode (made) 17 on the substrate, as shown in Figure 1 by second metal level by the first metal layer.And the substrate below also has a backlight module so that the light source of display module to be provided.Though when five road light shield processing procedures of design TFT assembly, considered the photaesthesia characteristic of amorphous silicon, and make amorphous silicon layer 15 pattern can in contract in the scope of grid 11 (that is grid amorphous silicon layer 15 can be blocked by grid 11 fully) to reduce the light electric leakage, (part light reflects between first, second metal level yet part light still can shine grid amorphous silicon layer 15 via reflection paths, shown in the arrow among Fig. 1), and produce light leakage current.
When following processing procedure progress to four road light shield, wherein a kind of four road light shield manufacture modes are to make the amorphous silicon layer and second metal level under with one deck light shield, therefore the existence of amorphous silicon layer is all arranged under all have the pattern of second metal level, that is to say and to contract in the first metal layer in the pattern with amorphous silicon layer.When the light of backlight module when second metal level is injected at the rear of the first metal layer forward, light will directly be beaten at amorphous silicon layer by layer, and produce than the made higher light leakage current of structure of five road light shield processing procedures.
[summary of the invention]
In view of this, purpose of the present invention is providing a kind of display module and manufacture method thereof exactly, to reduce the light leakage current of display module.
According to purpose of the present invention; system proposes a kind of display module, comprises at least: a grid (gateelectrode), a gate insulator (gate insulating layer), a grid amorphous silicon region, one source pole metal area (source metal region), a drain metal district (drain metalregion), a data line metal area (data-line (DL) metal region), a protective seam (passivation layer) and a conductive layer.Grid system is formed on the substrate gate insulator series of strata cover gate.Grid amorphous silicon fauna is formed on the gate insulator and is positioned at the grid top accordingly.A source metal district and a drain metal fauna are formed on the grid amorphous silicon region; Data line metal fauna is formed at gate insulator top, and data line metal area and the drain metal fauna spacing of being separated by.The protection series of strata are formed on the gate insulator; and covering source metal district, drain metal district and data line metal area; and protective seam comprises one first interlayer hole (first via) and one second interlayer hole (second via), with the part surface that exposes the data line metal area respectively and the part surface in drain metal district.The conduction series of strata are formed on the protective seam and cover first interlayer hole and second interlayer hole, to electrically connect data line metal area and drain metal district.
According to purpose of the present invention, be the manufacture method that proposes a kind of display module, comprise that at least step is as follows:
Form a grid on a substrate;
Form a gate insulator with cover gate;
Form a grid amorphous silicon region on gate insulator and be positioned at grid top accordingly;
Form one source pole metal area, a drain metal district and a data line metal area in the top of gate insulator, and data line metal area and the drain metal fauna spacing of being separated by;
Form a protective seam on gate insulator and cover source metal district, this drain metal district and data line metal area;
Form one first interlayer hole (first via) and one second interlayer hole (second via) in the protective seam place, with the part surface that exposes the data line metal area respectively and the part surface in drain metal district; With
Form a conductive layer on protective seam and cover first interlayer hole and second interlayer hole, to electrically connect data line metal area and drain metal district.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
[description of drawings]
Fig. 1 illustrates a kind of cut-away section synoptic diagram with the formed TFT LCD assembly of traditional five road light shield processing procedures.
Fig. 2 A～2I illustrates the manufacture method of the film transistor display assembly of first embodiment of the invention.
Fig. 3 A～3H, it illustrates the manufacture method of the film transistor display assembly of second embodiment of the invention.
[embodiment]
The present invention is the processing procedure of improvement display module (for example being the TFT display module), and electrode and data line are disconnected, and utilizes transparency electrode to do bridge joint again, make electrode can in contract in grid the minimizing light leakage current.
Below be to do detailed description of the present invention with embodiment.Wherein, first and second embodiment illustrates respectively and utilizes five road light shield processing procedures and four road light shield processing procedures to make the film transistor display assembly and the manufacture method thereof that can reduce the light electric leakage.Yet, the scope of those embodiment desire protection can't limit of the present invention.The pattern that technology of the present invention is not limited among the embodiment to be narrated.In addition, when drawing diagram, omit unnecessary assembly, with the clear embodiments of the invention that show.
First embodiment
Please refer to Fig. 2 A～2I, it illustrates the manufacture method of the film transistor display assembly of first embodiment of the invention.In first embodiment, be to utilize five road light shield processing procedures to make display module.
At first, provide a substrate 20, and on substrate 20, form a first metal layer 21, shown in Fig. 2 A.Then, patterning the first metal layer 21 forms a gate insulator (gate insulating layer) 22 and cover gate 211, shown in Fig. 2 B again to form grid (gate electrode) 211 on substrate 20.
Then, on this gate insulator, form an amorphous silicon layer (a-Si Layer) 23, on amorphous silicon layer 23, form a doped amorphous silicon layer (for example being the n+ amorphous silicon layer) 24 again, shown in Fig. 2 C.Then, patterning doped amorphous silicon layer 24 and amorphous silicon layer 23, to form a doping grid amorphous silicon region (doped g-aSi region) 241 and one grid amorphous silicon region (g-aSi region) 231, and grid amorphous silicon region 231 and doping grid amorphous silicon region 241 are to be positioned at grid 211 tops accordingly, shown in Fig. 2 D.
After, form one second metal level 25 in gate insulator 22 tops, and second metal level, 25 cover gate amorphous silicon regions 231 and doping grid amorphous silicon region 241, shown in Fig. 2 E.
Then, patterning second metal level 25, to form source metal district (source metalregion) 251, drain metal district (drain metal region) 252 and data line metal area (data-line (DL) metal region) 253, and has a passage (channel region) 26 between the source metal district 251 of the spacing of being separated by and the drain metal district 252, shown in Fig. 2 F.
Then, form a protective seam (passivation layer) 27 on gate insulator 22 and cover source metal district 251, drain metal district 252 and data line metal area 253, shown in Fig. 2 G.
Then, form one first interlayer hole (first via), 271 and 1 second interlayer hole (second via) 272 in protective seam 27 places, with the part surface that exposes data line metal area 253 respectively and the part surface in drain metal district 252, shown in Fig. 2 H.
At last, form a conductive layer 29 again on protective seam 27, conductive layer 29 also covers first interlayer hole 271 and second interlayer hole 272, to electrically connect data line metal area 253 and drain metal district 252, shown in Fig. 2 I.The material of conductive layer 29 for example be tin indium oxide (indium tinoxide, ITO).
Fig. 2 I also is the diagrammatic cross-section of the film transistor display assembly of first embodiment of the invention.In first embodiment, be to make data line metal area 253 and drain metal district 252 isolated (promptly disconnecting second metal level 25), again with conductive layer 29 for example ITO do bridge joint.When light from substrate 20 belows to front irradiation, because grid amorphous silicon region 231 has been recessed in the grid 211, data line metal area 253 and drain metal district 252 do not have second metal level 25 can cause reflection yet, and the ITO that is used for electrically connecting data line metal area 253 and drain metal district 252 also is transparent material, so light can directly pass through (shown in the arrow among Fig. 2 I), can not produce problem (as shown in Figure 1) as the conventional metals reflection.Therefore, use the manufacture method of five road light shields of first embodiment and made TFT display module, can effectively reduce the phenomenon of light leakage current.
Second embodiment
Please refer to Fig. 3 A～3H, it illustrates the manufacture method of the film transistor display assembly of second embodiment of the invention.In a second embodiment, be to utilize four road light shield processing procedures to make display module.In addition, identical with first embodiment in a second embodiment assembly system continues to use identical label.
At first, provide a substrate 20, and on substrate 20, form a first metal layer 21, as shown in Figure 3A.Then, patterning the first metal layer 21 forms a gate insulator (gate insulating layer) 22 and cover gate 211, shown in Fig. 3 B again to form grid (gate electrode) 211 on substrate 20.Then, on this gate insulator, form an amorphous silicon layer (a-SiLayer) 23, on amorphous silicon layer 23, form a doped amorphous silicon layer (for example being the n+ amorphous silicon layer) 24 again, shown in Fig. 3 C.
After, form one second metal level 25 on doped amorphous silicon layer 24, shown in Fig. 3 D.Then, patterning second metal level 25, doped amorphous silicon layer 24 and amorphous silicon layer 23, to form source metal district 251, drain metal district 252, data line metal area 253, a doping grid amorphous silicon region (doped g-aSi region) 241, one doping data line amorphous silicon region (doped DL-aSiregion) 242, grid amorphous silicon region 231 and data line amorphous silicon region 232, shown in Fig. 3 E.
In Fig. 3 E, have a passage 26 between source metal district 251 and the drain metal district 252, and source metal district 251 and drain metal district 252 are the place, top that is formed at grid 211 accordingly; And data line metal area 253 and drain metal district 252 are the spacing of being separated by, and 232 of data line amorphous silicon regions are formed at the below of data line metal area 253 and corresponding with the width of data line metal area 253.
Then, form a protective seam (passivation layer) 27 on gate insulator 22 and cover source metal district 251, drain metal district 252 and data line metal area 253, shown in Fig. 3 F.
Then; form one first interlayer hole (first via), 271,1 second interlayer hole (second via), 272 and 1 the 3rd interlayer hole (third via) 273 in protective seam 27 places; to expose the part surface in data line metal area 253, drain metal district 252 and source metal district 251 respectively, shown in Fig. 3 G.
At last; on protective seam 27, form a conductive layer 29 again; conductive layer 29 also covers first interlayer hole 271, second interlayer hole 272 and the 3rd interlayer hole 273; and this second interlayer hole 272 of drain metal district 252 and 251 tops, source metal district and the 3rd interlayer hole 273 are electrically isolated, shown in Fig. 3 H.The material of conductive layer 29 for example be tin indium oxide (indium tin oxide, ITO)
Fig. 3 H is the diagrammatic cross-section of the film transistor display assembly of second embodiment of the invention.In a second embodiment, also make data line metal area 253 and drain metal district 252 isolated (promptly disconnecting second metal level 25), again with conductive layer 29 for example ITO do bridge joint.During bridge joint, be to make data line metal area 253 and drain metal district 252 electrically connect, but 251 in drain metal district 252 and source metal district are electrically isolated.When light from substrate 20 belows to front irradiation, because grid amorphous silicon region 231 has been recessed in the grid 211, data line metal area 253 and drain metal district 252 do not have second metal level 25 can cause reflection yet, and the ITO that is used for electrically connecting data line metal area 253 and drain metal district 252 also is transparent material, so light can directly pass through (shown in the arrow among Fig. 3 H), can not produce problem (as shown in Figure 1) as the conventional metals reflection.Therefore, use the manufacture method of four road light shields of second embodiment and made TFT display module, can effectively reduce the phenomenon of light leakage current.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (16)
1. display module comprises at least:
One grid is to be formed on the substrate;
One gate insulator is to cover this grid;
One grid amorphous silicon region be to be formed on this gate insulator and to be positioned at this grid top accordingly, and the area of this grid amorphous silicon region is less than the area of this grid that is positioned at the below;
An one source pole metal area and a drain metal district are to be formed on this grid amorphous silicon region;
One data line metal area is to be formed at this gate insulator top, and this data line metal area and this drain metal fauna spacing of being separated by;
One protective seam, system is formed on this gate insulator and covers this source metal district, this drain metal district and this data line metal area, and this protective seam comprises one first interlayer hole and one second interlayer hole, with the part surface in the part surface that exposes this data line metal area respectively and this drain metal district; With
One conductive layer is to be formed on this protective seam and to cover this first interlayer hole and this second interlayer hole to electrically connect this data line metal area and this drain metal district.
2. display module according to claim 1 is characterized in that, between this source metal district, this drain metal district and this grid amorphous silicon region doping grid amorphous silicon region is arranged more.
3. display module according to claim 1 is characterized in that, more comprises a data line amorphous silicon region, and this data line metal fauna is formed on this data line amorphous silicon region.
4. display module according to claim 3 is characterized in that, has more a doping data line amorphous silicon region between this data line metal area and this data line amorphous silicon region.
5. display module according to claim 3 is characterized in that, this protective seam more comprises one the 3rd interlayer hole, to expose the part surface in this source metal district.
6. display module according to claim 5 is characterized in that this conductive layer also covers the 3rd interlayer hole, and this second interlayer hole is electrically isolated with the 3rd interlayer hole system.
7. display module according to claim 1 is characterized in that, this gate insulator is a silicon nitride layer.
8. display module according to claim 1 is characterized in that, this conductive layer is an indium tin oxide layer.
9. the manufacture method of a display module comprises step at least:
Form a grid on a substrate;
Form a gate insulator to cover this grid;
Form a grid amorphous silicon region on this gate insulator and be positioned at this grid top accordingly, and the area of this grid amorphous silicon region is less than the area of this grid that is positioned at the below;
Form one source pole metal area, a drain metal district and a data line metal area in the top of this gate insulator, and this data line metal area and this drain metal fauna spacing of being separated by;
Form a protective seam on this gate insulator and cover this source metal district, this drain metal district and this data line metal area;
Form one first interlayer hole and one second interlayer hole in this protective seam place, with the part surface in the part surface that exposes this data line metal area respectively and this drain metal district; With
Form a conductive layer on this protective seam and cover this first interlayer hole and this second interlayer hole, to electrically connect this data line metal area and this drain metal district.
10. manufacture method according to claim 9 is characterized in that, the step that forms this grid comprises:
Form a first metal layer on this substrate; With
This first metal layer of patterning is to form this grid.
11. manufacture method according to claim 10 is characterized in that, the step that forms this grid amorphous silicon region comprises:
Form an amorphous silicon layer on this gate insulator;
Form a doped amorphous silicon layer on this amorphous silicon layer; And
This doped amorphous silicon layer of patterning and this amorphous silicon layer are to form a doping grid amorphous silicon region and this grid amorphous silicon region.
12. manufacture method according to claim 11 is characterized in that, the step that forms this source metal district, this drain metal district and this data line metal area comprises:
Form one second metal level in the top of this gate insulator; And
This second metal level of patterning is to form this source metal district, this drain metal district and this data line metal area;
Wherein, have a passage between this source metal district and this drain metal district, and this data line metal area and this drain metal fauna spacing of being separated by.
13. manufacture method according to claim 10 is characterized in that, the step that forms this grid amorphous silicon region and this source metal district of formation, this drain metal district, this data line metal area comprises:
Form an amorphous silicon layer on this gate insulator;
Form a doped amorphous silicon layer on this amorphous silicon layer;
Form one second metal level on this doped amorphous silicon layer; And
This second metal level of patterning, this doped amorphous silicon layer and this amorphous silicon layer are to form this source metal district, this drain metal district, this data line metal area, a doping grid amorphous silicon region, a doping data line amorphous silicon region, this grid amorphous silicon region and a data line amorphous silicon region;
Wherein, has a passage between this source metal district and this drain metal district, and this data line metal area and this drain metal fauna spacing of being separated by, this data line amorphous silicon region then are formed at the below of this data line metal area and corresponding with the width of this data line metal area.
14. manufacture method according to claim 13 is characterized in that, this source metal district and this drain metal fauna are formed at the place, top of this grid accordingly.
15. manufacture method according to claim 14 is characterized in that, more forms one the 3rd interlayer hole in this protective seam place, to expose the part surface in this source metal district.
16. manufacture method according to claim 15 is characterized in that, this conductive layer more covers the 3rd interlayer hole, and this second interlayer hole of this drain metal district and top, this source metal district is electrically isolated with the 3rd interlayer hole system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100765930A CN100392507C (en) | 2005-06-09 | 2005-06-09 | Film transistor display assembly capable of reducing light leakage current and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100765930A CN100392507C (en) | 2005-06-09 | 2005-06-09 | Film transistor display assembly capable of reducing light leakage current and mfg. method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1687839A CN1687839A (en) | 2005-10-26 |
| CN100392507C true CN100392507C (en) | 2008-06-04 |
Family
ID=35305881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100765930A Active CN100392507C (en) | 2005-06-09 | 2005-06-09 | Film transistor display assembly capable of reducing light leakage current and mfg. method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100392507C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107300812B (en) * | 2017-05-12 | 2021-08-06 | 惠科股份有限公司 | Display panel, manufacturing method of display panel and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1165568A (en) * | 1995-10-03 | 1997-11-19 | 精工爱普生株式会社 | Active matrix substrate |
| US6061105A (en) * | 1998-04-16 | 2000-05-09 | International Business Machines Corporation | LCD with via connections connecting the data line to a conducting line both before and beyond the sealing material |
| JP2000206571A (en) * | 1998-12-31 | 2000-07-28 | Samsung Electronics Co Ltd | Thin film transistor substrate for liquid crystal display device and its production |
| US6144422A (en) * | 1996-12-28 | 2000-11-07 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor having a vertical structure and a method of manufacturing the same |
| CN1405865A (en) * | 2001-09-20 | 2003-03-26 | 友达光电股份有限公司 | Method for manufacturing film transistor plane indicator |
| WO2004019123A1 (en) * | 2002-08-24 | 2004-03-04 | Koninklijke Philips Electronics N.V. | Manufacture of electronic devices comprising thin-film circuit elements |
-
2005
- 2005-06-09 CN CNB2005100765930A patent/CN100392507C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1165568A (en) * | 1995-10-03 | 1997-11-19 | 精工爱普生株式会社 | Active matrix substrate |
| US6144422A (en) * | 1996-12-28 | 2000-11-07 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor having a vertical structure and a method of manufacturing the same |
| US6061105A (en) * | 1998-04-16 | 2000-05-09 | International Business Machines Corporation | LCD with via connections connecting the data line to a conducting line both before and beyond the sealing material |
| JP2000206571A (en) * | 1998-12-31 | 2000-07-28 | Samsung Electronics Co Ltd | Thin film transistor substrate for liquid crystal display device and its production |
| CN1405865A (en) * | 2001-09-20 | 2003-03-26 | 友达光电股份有限公司 | Method for manufacturing film transistor plane indicator |
| WO2004019123A1 (en) * | 2002-08-24 | 2004-03-04 | Koninklijke Philips Electronics N.V. | Manufacture of electronic devices comprising thin-film circuit elements |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1687839A (en) | 2005-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100669270B1 (en) | Display device and photoelectric conversion device | |
| CN100510867C (en) | Liquid crystal display and fabricating method thereof | |
| JP4737956B2 (en) | Display device and photoelectric conversion element | |
| US20110317121A1 (en) | Flat display device integrated with photovoltaic cell | |
| KR20140047649A (en) | Liquid crystal display | |
| CN101086564A (en) | Display substrate and repairing method | |
| EP2261730B1 (en) | Pixel designs of improving the aperture ratio in an LCD | |
| CN102315165B (en) | Edge electric field type liquid crystal display array substrate and manufacture method thereof | |
| CN103605241A (en) | Liquid crystal display panel | |
| CN101097368A (en) | Array substrate for liquid crystal display device and method of fabricating the same | |
| CN101216626B (en) | Liquid crystal display panel | |
| KR100984359B1 (en) | Thin film transistor array panel | |
| TW200405102A (en) | Opto-electronic apparatus and manufacturing method of semiconductor apparatus | |
| KR20070020675A (en) | Liquid crystal display | |
| CN104659106A (en) | Thin film transistor and manufacturing method thereof | |
| CN106298809A (en) | Thin-film transistor array base-plate and preparation method thereof, liquid crystal indicator | |
| CN201876642U (en) | Pixel structure | |
| JPH07101268B2 (en) | Thin film transistor array | |
| CN101470307B (en) | LCD and manufacturing method thereof | |
| CN100392507C (en) | Film transistor display assembly capable of reducing light leakage current and mfg. method thereof | |
| CN100444405C (en) | Double grid film electric crystal and pixel structure and its producing method | |
| CN100559598C (en) | Dot structure, display floater, electrooptical device and method for repairing and mending thereof | |
| CN100552519C (en) | The dot structure of semi-penetrate reflection type liquid crystal display array substrates and manufacture method | |
| CN100524779C (en) | Thin film transistor module base board and its making method | |
| WO2023102974A1 (en) | Display panel and method for manufacturing display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |