CN1400671A - Schottky-barrier diode and its manufacture - Google Patents
Schottky-barrier diode and its manufacture Download PDFInfo
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- CN1400671A CN1400671A CN02127231A CN02127231A CN1400671A CN 1400671 A CN1400671 A CN 1400671A CN 02127231 A CN02127231 A CN 02127231A CN 02127231 A CN02127231 A CN 02127231A CN 1400671 A CN1400671 A CN 1400671A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10338—Indium gallium phosphide [InGaP]
Abstract
A Schottky barrier diode and its manufacturing method. The conventional problem of there being no improvements in shrinkage of a chip, due to the existence of a mesa etching layer and a thick polyimide layer or the like, and characteristics is unable to be improved due to a distance between electrodes, and etching is difficult to control in a Schottky junction section in the manufacture. The present invention can realize a compound semiconductor planar type Schottky barrier diode. By forming an InGaP layer and an n not +-type ion implanted region in the surface of a substrate, there is no need to form the mesa and the polyimide layer. Since the distance between electrodes can be shortened, chip shrinking can be realized and high-frequency characteristics can be improved. When forming a Schottky electrode, since GaAs is not etched and results in the manufacture of a Schottky barrier diode with good reproducibility.
Description
Technical field
The present invention relates to the Schottky barrier diode and the manufacture method thereof of the compound semiconductor of high-frequency circuit employing, particularly by adopting planar configuration to realize the Schottky barrier diode and the manufacture method thereof of the compound semiconductor of operating space and chip size miniaturization.
Background technology
Surging along with the expansion of worldwide mobile phone market and digital satellite broadcasting receiver demand is to the rapid growth that needs of high-frequency device.As its element, consider and handle the high frequency field-effect transistors that utilized GaAs (GaAs) of using more, developing described switching circuit itself integrated single chip microwave integrated circuit (MMIC) and local oscillation FET thereupon.
And the GaAs Schottky barrier diode also uses etc. because of the base station, and demand increases.
Fig. 9 has represented the profile of existing Schottky barrier diode operating space part.
At n
+Lamination n on the type GaAs substrate 21
+Type epitaxial loayer 22 (5 * 10
18Cm
-3) about 6 μ m, again the n type epitaxial loayer 23 (1.3 * 10 that becomes the action layer
17Cm
-3) pile up for example about 3500 .
The ground floor metal level that becomes Ohmic electrode 28 is at n
+The AuGe/Ni/Au that ohm engages on the type epitaxial loayer 22.The second layer metal layer is Ti/Pt/Au, and the figure of this second layer metal layer has two kinds of anode-side and cathode sides.Form schottky junction in anode-side and n type epitaxial loayer 23.Following handle has the anode-side second layer metal layer of this schottky junction zone 31a to call Schottky electrode 31.Schottky electrode 31 also becomes the underlayer electrode of the 3rd layer of Au coating that forms anode bond pad, and both sides' figure is overlapping fully.The second layer metal layer of cathode side contacts and becomes the base electrode of the 3rd layer of Au coating that forms cathode pad with Ohmic electrode, the same with anode-side, both sides' figure is overlapping fully.Schottky electrode 31 since its figure end position must be configured in polyimide layer above, so overlap 16 μ m Bututs to cathode side at schottky junction zone 31a periphery.Substrate beyond the schottky junction portion is a cathode potential, and the part that the GaAs of anode electrode 34 and cathode potential intersects is to insulate to be provided with polyimide layer 30.This cross section area reaches 1300 μ m
2About, so owing to parasitic capacitance is necessary the thickness that its spacing distance is made about 6～7 μ m is relaxed parasitic capacitance greatly.Polyimides is because of its low-k and can be formed thicker character and be used and make interlayer insulating film.
Figure 10 is the plane graph of the Schottky barrier diode of the existing compound semiconductor of expression.
In the substantial middle of chip, on n type epitaxial loayer 23, form schottky junction zone 31a.This zone is the circle of the about 10 μ m of diameter, is the evaporation second metal level Ti/Pt/Au successively on the Schottky contacts hole 29 of exposing n type epitaxial loayer 23.Being provided with ground floor metal level Ohmic electrode 28 surrounds the periphery of circular schottky junction zone 31a.Ohmic electrode 28 is with AuGe/Ni/Au evaporation gained in turn, is located at nearly half zone of chip.And for the taking-up of electrode, the second layer metal layer is contacted with Ohmic electrode 28 becomes underlayer electrode.
The underlayer electrode of anode-side and cathode side is for the 3rd layer Au coating and establish.Anode-side is located at schottky junction zone 31a and partly engages necessary Minimum Area, and cathode side is patterned in the shape that circular schottky junction zone 31a periphery is surrounded.And for the induction composition that reduces the high frequency characteristics key element is necessary many fixed engagement line, therefore will account for chip approximately half zone as engaging zones.
And be provided with Au coating and underlayer electrode overlapping.Here engage the fixed engagement line, take out electrode by stitch shape.Anode bond pad portion is 40 * 60 μ m
2, cathode pad portion is 240 * 70 μ m
2Utilize stitch shape to engage the connection of carrying out and once can connect two closing lines, so even the little induction composition that also can reduce the high frequency characteristics parameter of bonding area helps to improve high frequency characteristics.
Figure 11 has represented the manufacture method of existing Schottky barrier diode to Figure 15.
Among Figure 11 by mesa etching with n
+Type epitaxial loayer 22 exposes, and adheres to the ground floor metal level and forms Ohmic electrode 28.
Promptly at n
+Pile up the n about 6 μ m on the GaAs substrate 21
+Type epitaxial loayer 22 (5 * 10
18Cm
-3), on it, pile up the n type epitaxial loayer 23 (1.3 * 10 about 3500
17Cm
-3).Then whole is covered with oxide-film 25, the photo-mask process of selectively windowing of the resist layer on the Ohmic electrode of being scheduled to 28.Then with this resist layer as mask oxide-film 25 etchings of predetermined Ohmic electrode 28 parts, and the mesa transistor that carries out n type epitaxial loayer 23 is etched with and exposes n
+Type epitaxial loayer 22.
Be the ground floor metal level three layers of vacuum evaporation lamination in turn of AuGe/Ni/Au then.Remove resist layer afterwards, stay metal level in predetermined Ohmic electrode 28 parts.Then pass through alloying heat treatment at n
+Form Ohmic electrode 28 on the type epitaxial loayer 22.
Figure 12 forms Schottky contacts hole 29.On whole, form new resist layer, the photoetching process that predetermined schottky junction zone 31a is partly windowed selectively.Remove resist layer after oxide-film 25 etchings that will expose, be formed on the Schottky contacts hole 29 that n type epitaxial loayer 23 exposes in predetermined schottky junction zone 31a portion.
Figure 13 forms the polyimide layer 30 of insulation usefulness.The plating polyimides is provided with thick polyimide layer 30 for several times on whole.Form new resist layer on whole, the photoetching process of windowing selectively stays predetermined polyimide layer 30 parts.Remove the polyimides that exposes by Wet-type etching then.Remove resist layer afterwards and make polyimide layer 30 be solidified into 6～7 μ m thickness.
Figure 14 is etched in the n type epitaxial loayer 23 that exposes in the Schottky contacts hole 29, forms Schottky electrode 31.
With the oxide-film 25 around the Schottky contacts hole 29 is mask etching n type epitaxial loayer 23.As previously mentioned, form polyimide layer 30 under the state that exposes on n type epitaxial loayer 23 surfaces after contact hole 29 forms.Schottky junction must form on the GaAs surface of cleaning, so Schottky electrode will be to n type epitaxial loayer 23 surface etchings before forming.And in order to ensure 2500 of the optimum thickness of action layer, accurate control temperature and time, from 3500 left and right thickness Wet-type etching to 2500 .
Vacuum evaporation Ti/Pt/Au in turn afterwards forms the Schottky electrode 31 of underlayer electrode of double as anode electrode and the underlayer electrode of cathode electrode 35 usefulness.
Figure 15 becomes the Au coating of anode electrode 34 and cathode electrode 35.
The underlayer electrode of predetermined anode electrode 34 and cathode electrode 35 parts exposed and carry out electrolytic gold plating after other cover with resist layer.This moment, resist layer became mask, only exposed the part of underlayer electrode and adhered to plating Au formation anode electrode 34, cathode electrode 35.On whole, underlayer electrode is set, carries out ion(ic) etching by the Ar plasma after removing resist layer, prune the underlayer electrode that do not plate the Au part and the figure that forms anode and cathode electrode 34,35 shapes.At this moment also what are pruned to plate the Au part, but owing to the thickness that has about 6 μ m, so out of question.
And then the back side made back side overlap joint and evaporation AuGe/Ni/Au in turn, and carry out alloying heat treatment, form the Ohmic electrode 28 at the back side.
The compound semiconductor Schottky barrier diode just changes the back operation of assembling before finish during operation over to.The semiconductor chip of wafer-like is cut apart, and is separated into semiconductor chip one by one, and this semiconductor chip is fixed on after framework (not shown) goes up, and with closing line the anode of semiconductor chip and cathode pad is connected with the lead-in wire (not shown) of regulation.Closing line engages with golden fine rule, with known stitch shape and connects.Transmit mould mould dress afterwards, carry out resin-encapsulated.
Existing Schottky barrier diode substrate is for also taking out the structure of cathode electrode from the back side, the machine that can corresponding use at n more
+On the type GaAs substrate n is set
+The type epitaxial loayer is for its upper strata of characteristic of guaranteeing to stipulate is provided with 1.3 * 10
17Cm
-3About n type epitaxial loayer.
So Schottky electrode exposes the clean surface of n type epitaxial loayer, evaporation metal and forms schottky junction because will guarantee the characteristic of stipulating.Ohmic electrode is for reducing to take out resistance, the n in its lower floor
+The type epitaxial loayer forms ohm knot.
Here in the existing structure problem points shown below is arranged.The first, for must forming table top, formation Ohmic electrode 28 exposes n
+Type epitaxial loayer 22.The thickness that n type epitaxial loayer 23 has about 3500 is for making the n below it
+Type epitaxial loayer 22 exposes must do the mesa transistor etching.Substrate surface is provided with the oxide-film 25 that is used for protective substrate, and the mesa transistor etching is the photoresist mask to be set and to carry out etching on its surface, but the being adjacent to property of oxide-film 25 surfaces and resist can produce deviation.The etching meeting is too to horizontal expansion when carrying out Wet-type etching under this state, sometimes essential oxide-film 25 also etching, as long as it is just unstable to expose the shape of GaAs table top.Therefore the Ohmic electrode 28 of being located at the table top peristome is when forming, the periphery shape limit etc. of collapsing also takes place in photoresist, the result is exactly that the shape of the Ohmic electrode 28 peeled off degenerates, and GaAs is etched near the schottky junction, and the problem of baneful influence takes place characteristic is produced sometimes.
The second, anode electrode 34 nearly all is located on the GaAs of cathode potential, and it is big that the parasitic capacitance here becomes.The area of cross section reaches 1300 μ m
2So, must reduce parasitic capacitance with thick interlayer dielectric.Form thick interlayer dielectric for imbedding table top, the polyimide layer 30 of 6～7 μ m must be set.For the electrode that takes out schottky junction zone 31a is provided with peristome at polyimide layer 30, by etching to thick polyimide layer 30, and the purpose of the substep coating of consideration polyimide layer 30 top electrodes, its peristome is made taper.But because the deviation of membranous deviation of polyimide layer 30 and polyimide layer 30 and being adjacent to property of resist layer, the angle of this taper deviation between 30～45 degree is very big.Therefore the spacing distance of the schottky junction of operating space zone 31a and Ohmic electrode 28 must be guaranteed about 7 μ m when considering taper.But spacing distance that should each knot works to series resistance, thus stop the raising that improves high frequency characteristics when spacing distance is big, and then also be the reason that the chip miniaturization can not be advanced.
The 3rd, owing near schottky junction and ohm knot, have taper, parasitic capacitance is increased, be the reason that makes characteristic degradation.
Also have, there is following problem in existing manufacture method.
The first, schottky junction is to form schottky junction on the n of the superiors type epitaxial loayer 23, for optimum thickness 2500 of the withstand voltage and resistance of guaranteeing to consider the action layer, is that the n type epitaxial loayer 23 about 3500 is etched to 2500 formation.At this moment etching is owing to be Wet-type etching, so not only to the unusual difficulty but also require to use etching solution in the fresh keeping time of regulation of the control of the amplitude of wafer in time and temperature and the etching solution, vibration velocity etc.Thereby each wafer has deviation when utilizing this method, the extremely difficult raising of seeking the reproducibility and the high frequency characteristics of operating space characteristic.
The second, adopted the mesa transistor etching that mesa structure just must the expense process number, produce bad sometimes by resist layer and being adjacent to sexual deviation of oxide-film.And form operation and the Au coating that takes out electrode is set on polyimide layer as the polyimide layer of interlayer dielectric and form the while such as operation and all need, make manufacturing process complicated, not only time-consuming but also inefficiency.
Because its substrate price of compound semiconductor itself is just high, so be necessary to reduce chip size inhibition cost in order to rationalize.It is inevitable promptly to reduce chip size, also wishes to cut down the cost of material itself.And requirement further improves high frequency characteristics simultaneously.Simplification and the efficient activity of further seeking manufacturing process also are important topics.
Summary of the invention
The present invention develops in view of the above problems, and it comprises: compound semiconductor substrate; Be located on the substrate a smooth conductivity type epitaxial loayer and the protection epitaxial loayer stable compound semiconductor layer; One conductive high concentration ion implanted region territory, it is located at the compound semiconductor layer surface; First electrode becomes ohm knot on high concentration ion injection zone surface; Second electrode forms schottky junction with epi-layer surface; Metal level takes out first and second electrode.By Ohmic electrode being set on the high concentration ion injection zone surface that is arranged at substrate surface, and not table top and polyimide layer and Au coating.Realize the compound semiconductor planar type Schottky barrier diode like this, also can reduce the area of action part,, help to improve high frequency characteristics by reducing parasitic capacitance and resistance so can help the miniaturization of chip size and reduce cost.
The manufacture method of Schottky barrier diode can also be provided, it comprises following operation: the epitaxial loayer of lamination one conductivity type and stable compound semiconductor layer on non-doped compound semiconductor substrate, and the compound semiconductor layer surface under the first predetermined electrode forms the operation of the high concentration ion injection zone of a conductivity type; Make the operation that ohm knot forms first electrode on high concentration ion injection zone surface; On compound semiconductor layer, form the Schottky contacts hole, form the operation that becomes second electrode of schottky junction with described epi-layer surface; Form the operation of the metal level that contacts with first and second electrode respectively.The simplification and the efficient activity of manufacturing process can be realized, and high frequency characteristics can be improved.
Description of drawings
Fig. 1 is the profile that is used to illustrate semiconductor device of the present invention;
Fig. 2 is the top figure that is used to illustrate semiconductor device of the present invention;
Fig. 3 is the top figure that is used to illustrate semiconductor device of the present invention;
Fig. 4 is the top figure that is used to illustrate semiconductor device of the present invention;
Fig. 5 is the profile that is used to illustrate manufacturing method for semiconductor device of the present invention;
Fig. 6 is the profile that is used to illustrate manufacturing method for semiconductor device of the present invention;
Fig. 7 is the profile that is used to illustrate manufacturing method for semiconductor device of the present invention;
Fig. 8 is the profile that is used to illustrate manufacturing method for semiconductor device of the present invention;
Fig. 9 is the profile that is used to illustrate existing semiconductor device;
Figure 10 is the top figure that is used to illustrate existing semiconductor device;
Figure 11 is the profile that is used to illustrate existing manufacturing method for semiconductor device;
Figure 12 is the profile that is used to illustrate existing manufacturing method for semiconductor device;
Figure 13 is the profile that is used to illustrate existing manufacturing method for semiconductor device;
Figure 14 is the profile that is used to illustrate existing manufacturing method for semiconductor device;
Figure 15 is the profile that is used to illustrate existing manufacturing method for semiconductor device.
Embodiment
Describe embodiments of the invention in detail with reference to accompanying drawing 1 to accompanying drawing 8.
Schottky barrier diode of the present invention comprises: compound semiconductor substrate 1, high concentration epitaxial loayer 2, epitaxial loayer 3, stable compound semiconductor layer 4, high concentration ion injection zone 7, the first electrodes 8, the second electrodes 11, metal level 14,15.
Fig. 1 is the profile of expression operating space part.
InGaP layer 4 surface of high concentration ion injection zone 7 below Ohmic electrode 8 arrive n
+Type epitaxial loayer 2, roughly overlapping along circular Schottky electrode 11 periphery settings with Ohmic electrode 8, exposing from Ohmic electrode 8 with Schottky electrode 11 adjacent parts, Schottky electrode 11 is 1 μ m with the spacing distance of high concentration ion injection zone 7.Promptly replace the existing mesa structure that adopts to keep the constant high concentration ion injection zone 7 that is provided with on the surface of planar structure, can not establish table top and realize ohm knot.
First electrode is that Ohmic electrode 8 is the ground floor metal levels that contact with high concentration ion injection zone 7, and evaporation AuGe/Ni/Au partly is carved into round-shaped Butut with schottky junction in turn, with the spacing distance of the Schottky electrode 11 of adjacency be 2 μ m.
Second electrode is that Schottky electrode 11 is that Butut is the circle of diameter 10 μ m Pt/Ti/Pt/Au or the Ti/Pt/Au second layer metal layer of evaporation in turn, forms schottky junctions with the n type epitaxial loayer 3 of InGaP layer 4 lower floor.
The n type epitaxial loayer 3 that forms operating space is 2500 because of best its thickness of characteristic that must obtain regulation such as withstand voltage.Here by n type epitaxial loayer 3 is protected in that InGaP layer 4 is set on the n type epitaxial loayer 3 before forming Schottky electrode 11 by InGaP layer 4, to obtain n type epitaxial loayer 3 and the good quality and high precision schottky junction of 2500 .InGaP layer 4 is non-doping, produces electric capacity so can be suppressed at the schottky junction side surface part that is formed by the second layer metal layer.
Metal level is the evaporated metal layer that becomes the 3rd layer Ti/Pt/Au formation of anode electrode 14 and cathode electrode 15.Anode electrode 14 contacts and extend to the anodic bonding zone with Schottky electrode 11 becomes anode bond pad 14a.By the GaAs insulation of nitride film 5 with Ohmic electrode 8 or cathode potential.
Be provided with below the 14a of anode bond pad portion and inject boron etc. and the zone 6 (is the insulating zone to call this in the following text) of insulating.Can insulate by insulating zone 6 cathode potential GaAs and the anode electrode 14 that arrives non-Doped GaAs substrate, directly wire-bonded portion is fixed on the substrate so can not establish polyimides and nitride film.
Fig. 2 and Fig. 3 have represented compound semiconductor Schottky barrier diode plane graph of the present invention.Fig. 2 is the skeleton diagram of graphics chip, and Fig. 3 is the enlarged drawing of operating space part.This figure is first embodiment of the invention, is that schottky junction is one a situation.
Be provided with the Schottky electrode 11 that forms schottky junction on the n type epitaxial loayer 3 in the chip substantial middle.This electrode is the circle of the about 10 μ m of diameter, with second layer metal layer Pt/Ti/Pt/Au or Ti/Pt/Au in turn evaporation obtain.Only central, circular part directly contacts with GaAs, is provided with the anode electrode 14 that the 3rd layer of evaporated metal layer form and extends anode bond pad 14a is set for taking out this electrode.
Be provided with below the anode bond pad 14a and inject B
+The insulating zone 6 of ion.Just can directly not be fixed on anode bond pad 14a on the substrate like this, can reduce bad, the parasitic capacitance of eliminating welding disk when engaging by dielectric film.
The part that dots is an Ohmic electrode 8.Circular Schottky electrode 11 outsides are got up contact with high concentration ion injection zone 7 (not shown)s.Ohmic electrode 8 is the AuGe/Ni/Au ground floor metal level of evaporation in turn.With the roughly overlapping setting of high concentration ion injection zone 7, cathode pad 15a is set for the taking-up electrode is provided with the cathode electrode 15 of the 3rd layer of evaporated metal layer formation and extends.Be to reduce the induction composition of high frequency characteristics key element, the taking-up of cathode electrode must many fixed engagement line, therefore accounting for half zone of chip as engaging zones.
By stitch shape joint closing line is fixed on anode and the last taking-up of cathode pad 14a, 15a electrode.The area of anode bond pad 14a portion is 60 * 70 μ m, and cathode pad 15a portion is 180 * 70 μ m.Engage 2 closing lines of a binding energy connection in the connection stitch shape, so even the little induction composition that also can reduce the high frequency characteristics parameter of bonding area helps to improve high frequency characteristics.
As shown in Figure 3, the cross section of cathode potential GaAs and anode electrode is the zone for representing with oblique line only, and this part area is about 100 μ m.With existing 1300 μ m mutually specific energy be contracted to about 1/13, so can replace the interlayer dielectric polyimides with thin nitride film 5.
The invention is characterized in that the GaAs epitaxial loayer is provided with InGaP layer 4, InGaP layer 4 surface of Ohmic electrode 8 contacts are provided with high concentration ion injection zone 7.Schottky electrode 11 and Ohmic electrode 8 are located at the GaAs surface like this, realize the planar structure of Schottky barrier diode.
Because needn't consider the contraposition deviation that the mesa shape deviation causes, so the spacing distance of Schottky electrode 11 and Ohmic electrode 8 can significantly shorten.Most of zone below the anode electrode 14 is provided with insulating zone 6, and the cross section area of the GaAs of cathode potential and anode electrode 14 is 100 μ m
2About, with existing relatively be its area of 1/13.Therefore needn't suppress parasitic capacitance by strengthening thickness (spacing distance), can replace polyimides, also needn't consider the conical section of polyimides with thin nitride film.
The spacing distance that is exactly schottky junction zone and Ohmic electrode specifically can reduce to 2 μ m by 7 μ m.And with the spacing distance of high concentration ion injection zone 7 are 1 μ m, at this moment high concentration ion injection zone 7 is mobile routes of charge carrier, the effect roughly the same with Ohmic electrode 8 is arranged, so can be reduced to 1/7 with existing than spacing distance.The spacing distance of Schottky electrode 11 and Ohmic electrode 8 works to series resistance, so just can reduce resistance more as long as can dwindle spacing distance, can increase substantially high frequency characteristics.
Help the chip miniaturization like this, existing size 0.27 * 0.31mm in the chip size
2Be contracted to 0.25 * 0.25mm
2As size have the configuration pad necessity and when assembling treatable chip size limited, therefore 0.25mm is square is the limit of present situation, but can significantly be contracted to about 1/10 as operating space, therefore the degree of freedom in action of configuration zone becomes very big as described later.
Fig. 4 is the second embodiment of the present invention, and expression is provided with the situation of a plurality of Schottky electrodes.
Structure of the present invention also can be established a plurality of Schottky electrodes 11.For example, help to reduce resistance as long as just become parallel connection as figure configuration Schottky electrode 11.
And as long as the diameter in Schottky contacts hole 19 diminished and dispose a plurality of, the area in total Schottky contacts hole 19 is identical and compare with one situation of configuration, the spacing distance of the center in Schottky contacts hole 19 and high concentration ion injection zone 7 can further reduce, and at high concentration ion injection zone 7 the carrier traps effect is arranged.The value of cathode resistor diminishes like this, and the advantage that can further improve high frequency characteristics is arranged.
Fig. 5 to Fig. 8 has represented the manufacture method of Schottky barrier diode of the present invention in detail.
Schottky barrier diode is made by following operation: the epitaxial loayer of lamination one conductivity type and stable compound semiconductor layer on non-doped compound semiconductor substrate, and the compound semiconductor layer surface under the first predetermined electrode forms the operation of the high concentration ion injection zone of a conductivity type; Make the operation that ohm knot forms first electrode on high concentration ion injection zone surface; On compound semiconductor layer, form the Schottky contacts hole, form the operation that becomes second electrode of schottky junction with epi-layer surface; Form the operation of the metal level that contacts with first and second electrode respectively.
As shown in Figure 5, first operation of the present invention is the epitaxial loayer 3 of lamination one conductivity type on non-doped compound semiconductor substrate 1 and stable compound semiconductor layer 4, and the surface of the compound semiconductor layer 4 under the first predetermined electrode 8 forms high concentration ion injection zone 7.
This operation is a feature operation of the present invention, the predetermined n type epitaxial loayer 3 that forms under Ohmic electrode 8 zones is connected to form reach n
+The high concentration ion injection zone 7 of type epitaxial loayer 2.
Promptly at the n that piles up on the non-Doped GaAs substrate 1 about 5000
+Type epitaxial loayer 2 (5 * 10
18Cm
-3), pile up the n type epitaxial loayer 3 (1.3 * 10 of 2500 thereon
17Cm
-3).And then layer is established the non-doping InGaP layer 4 of 200 thereon.Cover whole with nitride film 5 afterwards, resist layer is set, the photoetching process of windowing selectively of the resist layer on the insulating zone of being scheduled to 6.Afterwards this resist layer is injected B as masked ion
+Impurity, the insulating zone 6 that form to arrive non-Doped GaAs substrate 1 is with the GaAs that seeks cathode potential and the insulating of the 14a of anode bond pad portion.
Then the predetermined resist layer that forms on high concentration ion injection zone 7 zones is carried out photoetching process, window selectively.Afterwards this resist layer is injected high concentration n type impurity (Si+, 1 * 10 as masked ion
18Gm
-3About), the InGaP layer 4, the n type epitaxial loayer 3 that connect under the predetermined Ohmic electrode 8 form the high concentration ion injection zone 7 that arrives n+ type epitaxial loayer 2.At this moment to inject be to inject several times under different condition etc. to ion, the impurity concentration that as far as possible makes high concentration ion injection zone 7 on depth direction evenly.
Remove resist layer deposition anneal nitride film 5 once more afterwards, implement the activation annealing in high concentration ion injection zone 7 and insulating zone 6.
As shown in Figure 6, second operation of the present invention is formed in first electrode 8 of surface formation ohm knot of high concentration ion injection zone 7.
On whole, form resist layer, the predetermined part that forms Ohmic electrode 8 photoetching process of windowing selectively.Remove the nitride film 5 that exposes from resist layer, vacuum evaporation lamination in turn is as these three layers of the AuGe/Ni/Au of ground floor metal level.Remove resist layer by peeling off afterwards, the ground floor metal level is stayed predetermined Ohmic electrode 8 parts.Then form Ohmic electrode 8 on high concentration ion injection zone 7 surfaces by alloying heat treatment.
As shown in Figure 7, the 3rd operation of the present invention is to form Schottky contacts hole 19 on compound semiconductor layer 4, and the surface that is formed on epitaxial loayer 3 forms second electrode 11 of schottky junction.
This operation is a feature operation of the present invention, forms Schottky contacts hole 9, forms schottky junction by evaporation metal.
At first on whole, form resist layer PR among Fig. 7 (A), carry out photoetching process, predetermined Schottky electrode 11 parts are windowed selectively.After nitride film 5 dry ecthings of exposing with same mask etching InGaP layer 4.Here the etching selectivity of InGaP and GaAs is very big, so as long as just can only InGaP layer 4 be removed by the defined terms etching, form the Schottky contacts hole 9 of exposing n type epitaxial loayer 3.
Be shown in vacuum evaporation lamination in turn on whole as these three layers of the Ti/Pt/Au of second metal level as Fig. 7 (B) afterwards.Remove resist layer PR at n type epitaxial loayer 3 surface formation schottky junctions, as Schottky electrode 11 by peeling off afterwards.The surface of GaAs is covered by InGaP before forming schottky junction, and the GaAs surface energy forms schottky junction with good state.
Promptly can easily form the Schottky electrode 11 that becomes good schottky junction with n type epitaxial loayer 3 surfaces by InGaP layer 4.To time and temperature and then to the unusual difficulty of the precision control of the amplitude of wafer in the etching solution, vibration velocity etc., but also require in the fresh keeping time of regulation, to use etching solution in the existing manufacture method.But by manufacture method of the present invention as long as earlier forming as the only 2500 epitaxial loayer 3 of action layer, by the high etching of selectivity etching InGaP only, the thickness of easy control action layer, so can form the good schottky junction of reproducibility, the advantage of the Schottky barrier diode that can make stability of characteristics is arranged.
As shown in Figure 8, the 4th operation of the present invention is to form the metal level 14,15 that contacts with first electrode 8 and second electrode 11 respectively.
This operation also is a feature operation of the present invention, forms evaporated metal layer as anode electrode 14 and cathode electrode 15 for taking out Schottky electrode 11 and Ohmic electrode 8.
At first depositing nitride film 5 about 5000 on whole once more as interlayer dielectric.Form resist layer, carry out photoetching process, make Schottky electrode 11, Ohmic electrode 8 and anode bond pad 14a, cathode pad 15a part window etching nitride film 5 selectively as contact site.Establish new resist layer again after removing resist film, carry out photoetching process, the anode electrode 14 of hope, the figure of cathode electrode 15 are windowed selectively.Evaporation Ti/Pt/Au in turn on whole forms anode electrode 14 and cathode electrode 15 by peeling off, and back side overlap joint is made at the back side.
Here anode electrode 14 and cathode electrode 15 are the evaporation metals that form with the common method of peeling off.With the interlayer dielectric of anode electrode 14 and cathode electrode 15 are nitride films 5, welding disk also can directly be fixed on the substrate, so can omit polyimide layer.Can omit on the existing polyimide layer to the distribution of the thicker setting of bad situation that absorbs polyimides like this and form the plating Au operation of pad.
Repeatedly coating and the curing of the operation of existing formation thick polyimide layer, time-consuming and complex procedures.The formation operation of Au coating also is the essential factor that increases the worker ordinal number.But just can omit the formation operation of these polyimide layers and Au coating by manufacture method of the present invention, can realize the simplification significantly and the efficient activity of manufacturing process.
The compound semiconductor Schottky barrier diode just changes the back operation of assembling before finish during operation over to.The semiconductor chip of wafer-like is cut apart, and is separated into semiconductor chip one by one, this semiconductor chip is fixed on the framework (not shown) afterwards with closing line pad 14a, the 15a of semiconductor chip are connected with the lead-in wire (not shown) of regulation.Closing line engages with golden fine rule, with known stitch shape and connects.Transmit mould mould dress afterwards, implement resin-encapsulated.
Can be descended all effects according to structure of the present invention.
The first, by at n from the InGaP layer to GaAs
+The high concentration ion injection zone surface of type epitaxial loayer setting is provided with Ohmic electrode, realizes the Schottky barrier diode of planar structure.So can not suppress by the Ohmic electrode form variations of mesa shape deviation generation and the deterioration of characteristic, because of considering bit errors, so the spacing distance of Schottky electrode 11 and Ohmic electrode 8 can reduce significantly because of not establishing table top.Because the spacing distance of Schottky electrode 11 and Ohmic electrode 8 works to series resistance,, just can reduce more spacing distance so dwindling resistance more.
The second, the area of the GaAs of cathode potential and anode electrode 14 cross sections is 100 μ m
2About, parasitic capacitance significantly reduces.Most of zone under the anode electrode 14 is provided with insulating zone 6, the cross part area that parasitic capacitance takes place so compared with the existing only the schottky junction part just can be decreased to 1/13.And anode bond pad 14a also can directly be fixed on the GaAs, and this part does not produce parasitic capacitance, can significantly reduce total parasitic capacitance.Adopt the low polyimides of permittivity and establish thick interlayer dielectric for suppressing parasitic capacitance at present, but available thin nitride film replaces.Nitride film is than polyimides permittivity height, even but structure according to the present invention uses the nitride film about 5000 can reduce parasitic capacitance with existing comparing also.
The 3rd, because without thick polyimide, so needn't be considered as the distance of taper part of polyimides peristome of operating space and the deviation of taper portion angle.
According to above-mentioned, the only simple consideration of the spacing distance of Schottky electrode and Ohmic electrode is withstand voltage and the mask alignment precision just can.The spacing distance that is exactly schottky junction zone and Ohmic electrode specifically can be reduced to 2 μ m from 7 μ m.And with the spacing distance of high concentration ion injection zone 7 be 1 μ m, at this moment high concentration ion injection zone 7 is mobile routes of charge carrier, roughly with Ohmic electrode 8 same effect is arranged, so spacing distance can be decreased to 1/7 compared with the existing.Thereby can increase substantially high frequency characteristics by the deviation that significantly reduces resistance, significantly reduce parasitic capacitance and reduce parasitic capacitance.
The 4th, can realize the chip miniaturization, existing size 0.27 * 0.31mm in the chip size
2Be contracted to 0.25 * 0.25mm
2As size from the necessity of configuration pad and when assembling treatable chip size be limited, therefore 0.25mm is square is the limit of present situation, but can significantly be contracted to about 1/10 as operating space, so the degree of freedom in action of configuration zone becomes very big.
The 5th, can further reduce resistance by the schottky junction portion that a plurality of formation Schottky electrodes are set.The contact diameter of schottky junction portion is diminished and be provided with a plurality of, and situation that a Schottky electrode be set identical with total Schottky contacts area compared and further reduced resistance, can produce the trap of charge carrier effectively at the high concentration ion injection zone, so the advantage of further raising high frequency characteristics is arranged.
The 6th, so, realize reducing cost owing to can dwindle chip again without polyimide layer and the gold-plated fee of material that can reduce.
Manufacturing method according to the invention can get following shown in effect.
The first, owing to can form stable schottky junction, so can suppress characteristic deviation as the extremely important problem of high-frequency circuit.N type epitaxial loayer is all covered by InGaP before schottky junction forms, as long as etching InGaP evaporation Ti/Pt/Au just can make schottky junction on complete free of contamination crystal plane.N type epitaxial loayer forms only 2500 as action layer, thus the etching selectivity of InGaP and GaAs very big when condition etching in accordance with regulations etching InGaP only.Therefore do not need complicated at present GaAs etching control.Can make and improve the Schottky barrier diode that accepted product percentage, reproducibility are good, stability characteristic (quality) is arranged.
The second, the manufacturing of above-mentioned Schottky barrier diode can realize the more simplification of high efficiency, manufacturing process.N type epitaxial loayer etching work procedure, polyimide layer before can omitting mesa etch operation, schottky junction specifically exactly and forming form operation, plating Au operation etc.Polyimide layer forms for making the thick coating repeatedly of 6～7 μ m for several times.And the coating polyimide layer is both time-consuming for several times manufacturing process was complicated.If do not need polyimides then the electrode of Au coating do not need yet.The intensity that the lead rupture that causes of the stress when heat when preventing to be installed by scolder and wire-bonded and distortion at present is necessary to guarantee electrode is by thick Au coating formation anode electrode and cathode electrode.But if do not need then unnecessary its influence of consideration of words of polyimide layer.Promptly do not need gold-plated electrode, only the evaporation metal with Ti/Pt/Au just can form anode electrode and cathode electrode, and reliability has also improved.Cause that at present the low above-mentioned essential factor of qualification rate disappears, so qualification rate has also improved.
Be that advantage reduces parasitic capacitance significantly for providing, can reduce the Schottky barrier diode that resistance significantly improves high frequency characteristics more, the manufacture method of seeking manufacturing process's simplification and efficient activity can be provided again.
Claims (12)
1. a Schottky barrier diode is characterized in that, comprising: compound semiconductor substrate; Be located at the smooth conductivity type epitaxial loayer on this substrate and protect the stable compound semiconductor layer of this epitaxial loayer; Be located at a conductive high concentration ion implanted region territory on described compound semiconductor layer surface; Become first electrode of ohm knot on described high concentration ion injection zone surface; Second electrode with described epi-layer surface formation schottky junction; Take out described first and second metal layer of electrodes.
2. a Schottky barrier diode is characterized in that, comprising: compound semiconductor substrate; Be located at a smooth conductive high concentration epitaxial loayer and the conductivity type epitaxial loayer on this substrate and protect the stable compound semiconductor layer of this epitaxial loayer; Arrive a conductive high concentration ion implanted region territory of described high concentration epitaxial loayer from described compound semiconductor layer surface; Become first electrode of ohm knot on described high concentration ion injection zone surface; Surrounded periphery, form second electrode of schottky junction by described first electrode with the described epi-layer surface of described compound semiconductor layer lower floor; Take out described first and second metal layer of electrodes.
3. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described compound semiconductor layer is the InGaP of non-doping.
4. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described compound semiconductor substrate is the GaAs substrate of non-doping.
5. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described its orlop of second electrode is the evaporation metal of Pt.
6. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, the spacing distance of described second electrode and described high concentration ion injection zone is below the 5 μ m.
7. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, the schottky junction Region Segmentation that described second electrode forms is arranged to a plurality of.
8. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described high concentration ion injection zone exposes setting from described first electrode.
9. the manufacture method of a Schottky barrier diode, it is characterized in that, comprise: the epitaxial loayer of lamination one conductivity type and stable compound semiconductor layer on non-doped compound semiconductor substrate, the described compound semiconductor layer surface under the first predetermined electrode forms the operation of the high concentration ion injection zone of a conductivity type; Be formed on the operation that described high concentration ion injection zone surface becomes first electrode of ohm knot; On described compound semiconductor layer, form the Schottky contacts hole, form the operation that forms second electrode of schottky junction with described epi-layer surface; Form the operation of the metal level that contacts with described first and second electrode respectively.
10. the manufacture method of a Schottky barrier diode, it is characterized in that, comprise: lamination one conductive high concentration epitaxial loayer and a conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, formation arrive the operation in a conductive high concentration ion implanted region territory of described high concentration epitaxial loayer from the described compound semiconductor layer surface under the first predetermined electrode; Be formed on the operation that described high concentration ion injection zone surface becomes first electrode of ohm knot; On the described compound semiconductor layer of predetermined second electrode part that is surrounded periphery by described first electrode, form the Schottky contacts hole, form the operation that forms second electrode of schottky junction with the described epi-layer surface of exposing; Form the operation of the metal level that contacts with described first and second electrode respectively.
11. the manufacture method as claim 9 or 10 described Schottky barrier diodes is characterized in that, described second electrode multiple layer metal layer of evaporation Ti/Pt/Au in turn forms.
12. the manufacture method as claim 9 or 10 described Schottky barrier diodes is characterized in that the etching selectivity of described compound semiconductor layer and described epitaxial loayer is big.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP228047/2001 | 2001-07-27 | ||
| JP2001228047A JP2003046094A (en) | 2001-07-27 | 2001-07-27 | Schottky barrier diode and method of manufacturing the same |
| JP228047/01 | 2001-07-27 |
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| Publication Number | Publication Date |
|---|---|
| CN1400671A true CN1400671A (en) | 2003-03-05 |
| CN1314131C CN1314131C (en) | 2007-05-02 |
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|---|---|---|---|
| CNB02127231XA Expired - Fee Related CN1314131C (en) | 2001-07-27 | 2002-07-29 | Schottky-barrier diode and its manufacture |
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|---|---|
| JP (1) | JP2003046094A (en) |
| KR (1) | KR100612188B1 (en) |
| CN (1) | CN1314131C (en) |
| TW (1) | TW548845B (en) |
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| CN108022837A (en) * | 2017-11-14 | 2018-05-11 | 厦门市三安集成电路有限公司 | A kind of etch process for preparing HBT base stages |
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| KR100463425B1 (en) * | 2002-10-04 | 2004-12-23 | 삼성전기주식회사 | A structure of Photo Diode cells in a PDIC for a optical pickup, and its manufacturing method |
| JP4954463B2 (en) * | 2004-10-22 | 2012-06-13 | 三菱電機株式会社 | Schottky barrier diode |
| KR101058593B1 (en) | 2009-09-08 | 2011-08-22 | 삼성전기주식회사 | Semiconductor device and manufacturing method thereof |
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| FR2432550A1 (en) * | 1978-08-04 | 1980-02-29 | Sueddeutsche Kalkstickstoff | PROCESS FOR THE MANUFACTURE OF AN EASILY FLOWABLE PULVERULATED DESULFURIZATION MIXTURE |
| GB2137412B (en) * | 1983-03-15 | 1987-03-04 | Standard Telephones Cables Ltd | Semiconductor device |
| JPH07211924A (en) * | 1994-01-17 | 1995-08-11 | Nippondenso Co Ltd | Schottky diode and its manufacture |
| JPH0897234A (en) * | 1994-09-22 | 1996-04-12 | Mitsubishi Electric Corp | Electrode of semiconductor device and its manufacture |
| JP2679653B2 (en) * | 1994-12-05 | 1997-11-19 | 日本電気株式会社 | Semiconductor device |
| JP3319514B2 (en) * | 1999-09-17 | 2002-09-03 | 日本電気株式会社 | Method for manufacturing group III-V compound semiconductor crystal laminate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022837A (en) * | 2017-11-14 | 2018-05-11 | 厦门市三安集成电路有限公司 | A kind of etch process for preparing HBT base stages |
| CN108022837B (en) * | 2017-11-14 | 2020-02-11 | 厦门市三安集成电路有限公司 | Etching process for preparing HBT base electrode |
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| Publication number | Publication date |
|---|---|
| JP2003046094A (en) | 2003-02-14 |
| TW548845B (en) | 2003-08-21 |
| KR20030010553A (en) | 2003-02-05 |
| KR100612188B1 (en) | 2006-08-16 |
| CN1314131C (en) | 2007-05-02 |
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