CN108022837B - Etching process for preparing HBT base electrode - Google Patents
Etching process for preparing HBT base electrode Download PDFInfo
- Publication number
- CN108022837B CN108022837B CN201711122912.6A CN201711122912A CN108022837B CN 108022837 B CN108022837 B CN 108022837B CN 201711122912 A CN201711122912 A CN 201711122912A CN 108022837 B CN108022837 B CN 108022837B
- Authority
- CN
- China
- Prior art keywords
- etching
- layer
- etching process
- ingap
- display window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005530 etching Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000001312 dry etching Methods 0.000 claims abstract description 20
- 238000001039 wet etching Methods 0.000 claims abstract description 15
- 239000000126 substance Substances 0.000 claims abstract description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 11
- 230000003595 spectral effect Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001228 spectrum Methods 0.000 claims description 3
- 230000003313 weakening effect Effects 0.000 claims description 2
- 239000000047 product Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010953 base metal Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses an etching process for preparing an HBT base, which comprises the steps of etching InGaP by adopting a dry etching process, stopping dry etching immediately after an end point is detected by dry etching, removing residual InGaP and substances damaged by surface plasma by using a high-selectivity wet etching process, having good process controllability and stability by the dry-wet combined etching process, having no surface plasma damage of a p-doped GaAs base layer, and greatly improving the process controllability. The method is particularly suitable for preparing the HBT base with high gain and thin thickness.
Description
Technical Field
The invention relates to a semiconductor manufacturing technology, in particular to an etching process for preparing an HBT base.
Background
The InGaP/GaAs HBT power amplifier comprises an n-doped GaAs collector layer, a p-doped GaAs base layer and an InGaP emitter layer which are sequentially stacked from bottom to top, wherein the most important and strict requirement in the preparation process is the preparation of the base electrode, and the preparation is generally carried out by five steps: 1. and (3) yellow light step, namely SiN etching of the dielectric layer, InGaP etching, metal evaporation and metal stripping to form ohmic contact. The etching requirement of InGaP is very strict, and it is required to completely etch off InGaP to expose the P + GaAs base material on all sides, but it is required not to damage the base material as much as possible. Slight errors in InGaP etching can cause a series of problems such as current gain change, interface corrosion, product reliability and product yield deterioration. With the development of HBTs, the thickness of the heavily doped base material P + GaAs becomes thinner and thinner, which requires that the etching of InGaP of the emitter be better controlled and the thin base material P + GaAs cannot be damaged by the etching of InGaP.
At present, there are three HBT base preparation methods, as follows: the first is the alloying method, which is not suitable for very thin P + GaAs, because the diffusion of the base metal through InGaP during alloying may continue to over-diffuse through the thin P + GaAs layer, which can create product quality and performance problems. The second is a wet etching technique, which is difficult to apply due to the inability to guarantee the control stability of the Critical Dimension (CD) of the base, and is gradually being eliminated. The third is dry etching, which often requires a certain over-etching, which may cause plasma damage to the surface of the thin P + GaAs layer or even over-etching the P + GaAs layer, and such dry etching is difficult to achieve good process stability and stable product performance. The above methods are not suitable for the preparation of a high-concentration doped thin P + GaAs base.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an etching process for preparing an HBT base, which realizes accurate control of etching by combining dry etching and wet etching.
The technical scheme of the invention is as follows:
an etching process for preparing an HBT base electrode comprises the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a p-doped GaAs base layer and an InGaP emitter layer which are laminated; wherein the thickness of the p-doped GaAs base layer is 50-100 nm;
2) forming a photoresist layer on the InGaP emitter layer, and forming a display window in a preset base region through exposure and development;
3) dry etching is carried out on the InGaP emitter layer In the display window, an etching end point is determined by detecting the spectral intensity of In a product and according to the intensity attenuation degree of In, and the etching depth is controlled to be larger than 95% of the thickness of the InGaP emitter layer;
4) removing residual InGaP in the display window and substances damaged by ions through wet etching to expose the surface of the p-doped GaAs base layer; the etching solution is hydrochloric acid solution;
5) and depositing metal, and then stripping the light resistor, wherein the metal forms ohmic contact with the surface of the p-doped GaAs base layer in the display window.
Optionally, the etching end point is set when the variation rate of the In spectrum intensity decreasing interval reaches the minimum value.
Optionally, the doping concentration of the p-doped GaAs base layer is 3.0 × 10
19～8.0×10
19cm
-3。
Optionally, the thickness of the InGaP emitter layer is 30 to 50 nm.
Optionally, the dry etching gas is BCl
3+N
2。
Optionally, in step 4), the etching solution for wet etching is concentrated HCl: h
2O is 2-4: 1, the etching time is 5-10 s.
Optionally, in step 4), the etching solution is stirred during the wet etching process.
Optionally, a dielectric layer is further coated on the surface of the InGaP emitter layer, the photoresist layer is coated on the surface of the dielectric layer, and the thickness of the dielectric layer is 40-60 nm.
Optionally, in step 2), a step of removing the dielectric layer within the display window is further included, and in step 3), dry etching is performed on the dielectric layer within the display window, and after etching, dry etching is performed on the InGaP emitter layer.
The invention has the beneficial effects that:
in the process of etching the InGaP by a dry method, the spectral intensity of In a product is detected, the etching end point is determined by the intensity weakening degree of the In, the InGaP dry etching process is stopped In time, then the residual InGaP and substances damaged by ions are etched by a wet method, the used wet etching liquid has excellent etching selectivity, the InGaP is etched quickly, and the influence on a p-doped GaAs base layer is basically avoided, so that a very thin p-doped GaAs base material cannot be etched and damaged, the CD of the base is controlled by the dry etching with excellent control, but the surface state after the base is etched is determined by the wet etching with excellent selectivity, the controllability of the HBT base preparation process of the high-gain thin base material is greatly improved, and the stable product yield and the stable product performance are achieved.
Drawings
FIG. 1 is a process flow diagram of the present invention;
FIG. 2 is a graph of In spectrum.
Detailed Description
The present invention will be further specifically described with reference to the drawings and examples.
Referring to fig. 1, in the etching process for fabricating HBT base according to the present invention, a semiconductor substrate is provided, the semiconductor substrate includes a p-doped GaAs base layer 1, an InGaP emitter layer 2, and a dielectric layer 3 (for example, SiN), wherein the p-doped GaAs base layer 1 has a thickness of 50-100 nm and a doping concentration of 3.0 × 10
19～8.0×10
19cm
-3(3.0E 19-8.0E 19), the thickness of the InGaP emitter layer is 30-50 nm. Conventionally, an n-doped GaAs collector layer and a substrate are disposed below the p-doped GaAs base layer 1, and a base process is performed after an emitter process is completed.
Coating photoresist on the surface of the dielectric layer 3 to form a photoresist layer 4, forming a display window 41 In a preset base region through exposure and development, etching and removing the dielectric layer 3 In the display window 41 by a conventional method, then carrying out dry etching on the InGaP emitter layer In the display window 41, determining an etching end point by detecting the spectral intensity of In a product and according to the intensity attenuation degree of the In, and controlling the etching depth to be more than 95% of the thickness of the InGaP emitter layer. Specifically, the dry etching gas is BCl
3+N
2。
Specifically, BCl is utilized in the dry etching process
3And etching the InGaP emitter layer by the plasma, and judging the etching degree by detecting the spectral intensity change of In the reaction product. Referring to fig. 2, curve No. 1 is a spectral intensity diagram of In, and curve No. 2 is a differential diagram thereof. The In spectral intensity is rapidly increased and maintained at the beginning of the visible reaction, and gradually decreased as the reaction proceeds, and the curve 2 shows the rate of change, and it is seen that the rate of change has a trough (minimum) where the etching is to be performed, i.e. the bottom is reached, after which the spectral intensity rapidly decreases (i.e. the etching is considered to start to the base layer). In the actual process, due to the etching non-uniformity, it is likely that the InGaP layer segment is completely etched and the segment still has residue; or still a very thin InGaP layer is not completely etched; thus, conventional processes often perform over-etching for a certain period of time (e.g., toLine 3 as the end point) to ensure complete etch clean. In this application, the dry etching was stopped at the etching end point (line 4) when the rate of change In the decrease In the In spectral intensity reached a minimum, and the etching was not complete.
Removing the residual InGaP in the display window and substances damaged by ions through wet etching to enable the surface of the p-doped GaAs base layer to be completely exposed, wherein etching liquid of the wet etching is hydrochloric acid solution; the ratio of the hydrochloric acid solution is H
2Concentrated HCl volume ratio of 1: 2-4, the etching time is 5-10 s, and the etching solution is stirred in the wet etching process to ensure uniform reaction. The wet etching only etches InGaP, but does not etch p-doped GaAs, so that InGaP can be completely etched without damaging the base layer 1, and the base layer 1 has an ideal surface state.
And finally, depositing metal 5, stripping the light resistance 4, and forming ohmic contact between the metal and the surface of the p-doped GaAs base layer 1 in the display window to complete the base electrode manufacturing process.
The HBT prepared by the process has normal direct current performance and passes the WAT test verification.
The above embodiments are merely provided to further illustrate the etching process for preparing the HBT base of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.
Claims (7)
1. An etching process for preparing an HBT base is characterized by comprising the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a p-doped GaAs base layer and an InGaP emitter layer which are laminated; wherein the thickness of the p-doped GaAs base layer is 50-100 nm;
2) forming a photoresist layer on the InGaP emitter layer, and forming a display window in a preset base region through exposure and development;
3) dry etching is carried out on the InGaP emitter layer In the display window, an etching end point is determined by detecting the spectral intensity of In a product and according to the intensity attenuation degree of In, and the etching depth is controlled to be larger than 95% of the thickness of the InGaP emitter layer; wherein, the etching end point is the time when the variation rate of the In spectrum intensity weakening interval reaches the minimum value;
4) removing residual InGaP in the display window and substances damaged by ions through wet etching to expose the surface of the p-doped GaAs base layer; the etching solution is hydrochloric acid solution; the etching solution for wet etching is prepared from concentrated HCl: h
2O =2 to 4: 1, etching time is 5-10 s;
and depositing metal, and then stripping the light resistor, wherein the metal forms ohmic contact with the surface of the p-doped GaAs base layer in the display window.
2. The etching process of claim 1, wherein: the doping concentration of the p-doped GaAs base layer is 3.0 × 10
19~8.0×10
19cm
-3。
3. The etching process of claim 1, wherein: the thickness of the InGaP emitter layer is 30-50 nm.
4. The etching process of claim 1, wherein: the dry etching gas is BCl
3+N
2。
5. The etching process of claim 1, wherein: in the step 4), the etching solution is stirred in the wet etching process.
6. The etching process of claim 1, wherein: the surface of the InGaP emitter layer is also covered with a dielectric layer, the photoresist layer is coated on the surface of the dielectric layer, and the thickness of the dielectric layer is 40-60 nm.
7. The etching process of claim 6, wherein: in step 2), the step of removing the dielectric layer inside the display window is further included, and in step 3), the step of performing dry etching on the dielectric layer inside the display window is further included, and the dry etching is performed on the InGaP emitter layer after etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711122912.6A CN108022837B (en) | 2017-11-14 | 2017-11-14 | Etching process for preparing HBT base electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711122912.6A CN108022837B (en) | 2017-11-14 | 2017-11-14 | Etching process for preparing HBT base electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108022837A CN108022837A (en) | 2018-05-11 |
| CN108022837B true CN108022837B (en) | 2020-02-11 |
Family
ID=62079872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711122912.6A Active CN108022837B (en) | 2017-11-14 | 2017-11-14 | Etching process for preparing HBT base electrode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108022837B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759497A (en) * | 2023-08-11 | 2023-09-15 | 晶能光电股份有限公司 | MicroLED pixelation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400671A (en) * | 2001-07-27 | 2003-03-05 | 三洋电机株式会社 | Schottky-barrier diode and its manufacture |
| CN101562132A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for corroding submicron emitter in InGaAs/InP HBT by wet process |
| CN101562121A (en) * | 2008-04-17 | 2009-10-21 | 上海华虹Nec电子有限公司 | Method for monitoring end point of small opening density structure by dry etching |
| CN104392923A (en) * | 2014-10-20 | 2015-03-04 | 中国电子科技集团公司第十三研究所 | Manufacturing method of heterojunction bipolar transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100732191B1 (en) * | 2006-04-21 | 2007-06-27 | 한국과학기술원 | High efficiency led with multi-layer reflector structure and method for fabricating the same |
-
2017
- 2017-11-14 CN CN201711122912.6A patent/CN108022837B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400671A (en) * | 2001-07-27 | 2003-03-05 | 三洋电机株式会社 | Schottky-barrier diode and its manufacture |
| CN101562132A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for corroding submicron emitter in InGaAs/InP HBT by wet process |
| CN101562121A (en) * | 2008-04-17 | 2009-10-21 | 上海华虹Nec电子有限公司 | Method for monitoring end point of small opening density structure by dry etching |
| CN104392923A (en) * | 2014-10-20 | 2015-03-04 | 中国电子科技集团公司第十三研究所 | Manufacturing method of heterojunction bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108022837A (en) | 2018-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6499654B2 (en) | Method for selectively etching a mask deposited on a silicon substrate | |
| JP4999400B2 (en) | Oxide semiconductor film dry etching method | |
| US20180144929A1 (en) | Method for forming high aspect ratio patterning structure | |
| JP2008052255A (en) | Method of producing active matrix substrate | |
| WO2017143678A1 (en) | Oxide thin film transistor and preparation method therefor | |
| US11961852B2 (en) | Manufacture method of array substrate, array substrate, and display panel | |
| CN108022837B (en) | Etching process for preparing HBT base electrode | |
| US20120138139A1 (en) | Dry etching method of surface texture formation on silicon wafer | |
| JP3416113B2 (en) | Precision wide band gap semiconductor etching | |
| US5632855A (en) | Thermal oxide etch technique | |
| CN112420871B (en) | Mesa type indium gallium arsenic detector chip and preparation method thereof | |
| KR20140016404A (en) | Method of fabrication of porous film structure by dry processes and porous film structures fabricated by the same | |
| CN116741874B (en) | Method for preparing contact hole on tellurium-cadmium-mercury infrared detector chip | |
| US6093653A (en) | Gas mixture for etching a polysilicon electrode layer and etching method using the same | |
| KR20010030328A (en) | A method of manufacturing semiconductor device | |
| US6358760B1 (en) | Method for amorphous silicon local interconnect etch | |
| CN102082090B (en) | Self-aligning silicide membrane etching method | |
| CN101562132A (en) | Method for corroding submicron emitter in InGaAs/InP HBT by wet process | |
| TWI229379B (en) | Method and solution for selectively etching III-V semiconductor | |
| JPH07106583A (en) | Manufacture of thin film transistor | |
| CN103871858A (en) | Manufacturing method for submicron electrode of indium phosphide-based heterojunction transistor | |
| CN108807424A (en) | A kind of production method of array substrate, array substrate and display panel | |
| KR100496867B1 (en) | Method of handling process wafer before selective epitaxial growth | |
| US9873949B2 (en) | Method and device for producing nanotips | |
| US6184149B1 (en) | Method for monitoring self-aligned contact etching |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |