CN1272836C - Manufacture of Schottky-barrier diode - Google Patents
Manufacture of Schottky-barrier diode Download PDFInfo
- Publication number
- CN1272836C CN1272836C CNB021272328A CN02127232A CN1272836C CN 1272836 C CN1272836 C CN 1272836C CN B021272328 A CNB021272328 A CN B021272328A CN 02127232 A CN02127232 A CN 02127232A CN 1272836 C CN1272836 C CN 1272836C
- Authority
- CN
- China
- Prior art keywords
- schottky
- compound semiconductor
- electrode
- semiconductor layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 62
- 239000002184 metal Substances 0.000 claims description 51
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 45
- 150000001875 compounds Chemical class 0.000 claims description 43
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 238000001704 evaporation Methods 0.000 claims description 15
- 230000008020 evaporation Effects 0.000 claims description 15
- 238000003475 lamination Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 abstract description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 20
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 122
- 239000004642 Polyimide Substances 0.000 description 24
- 229920001721 polyimide Polymers 0.000 description 24
- 239000010931 gold Substances 0.000 description 21
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000007738 vacuum evaporation Methods 0.000 description 4
- 238000005275 alloying Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000013138 pruning Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
A manufacturing method of Schottky barrier diode solves the conventional problem of a very precise etching control being required, when forming a Schottky junction section, resulting in a, poor reproducibility and unstable high frequency characteristics. The present inventive manufacturing method of Schottky barrier diode can provide a Schottky barrier diode with no complicated etching control, and with good reproducibility and stability. On the surface of a substrate, an InGaP layer is deposited, and then Pt/Ti/Pt/Au are vapor deposited thereon. Thereafter, heat treatment is conducted to embed Pt in the InGaP layer, to form a Schottky junction with a GaAs interface.
Description
Technical field
The present invention relates to the manufacture method of the Schottky barrier diode of the compound semiconductor that high-frequency circuit adopts, relate in particular to the manufacture method of the Schottky barrier diode of the compound semiconductor that can form the good schottky junction of reproducibility.
Background technology
Because the expansion of world's Mobile Phone Market, the needs of digital satellite transmitter-receiver are surging, and high-frequency apparatus needs rapid growth thereupon., continually develop thereupon and make integrated monolithic integrated microwave circuit of described switching circuit self (MMIC) and local oscillation FET for handling the field-effect transistor that high frequency has often used GaAs (GaAs) as its element.
The GaAs Schottky barrier diode has also improved consumption because of being used for base station etc.
Fig. 6 represents the profile of the operating space part of existing Schottky barrier diode.
At the n+ type epitaxial loayer 22 (5 * 10 about lamination 6 μ m on the n+ type GaAs substrate 21
18Cm
-3), pile up for example n type epitaxial loayer 23 (1.3 * 10 of the formation action layer of 3500 again
17Cm
-3).
The ground floor metal level that constitutes Ohmic electrode 28 is the AuGe/Ni/Au that forms ohm knot with n+ type epitaxial loayer 22.The second layer metal layer is Ti/Pt/Au.The figure of this second layer metal layer has two kinds of anode-side and cathode sides.Anode-side and n type epitaxial loayer 23 form schottky junction.The anode-side second layer metal layer that below will have this schottky junction zone 31a becomes Schottky electrode 31.Schottky electrode 31 also constitutes the underlayer electrode of the 3rd layer of plating Au layer that forms the anodic bonding contact, makes both sides' figure overlapping fully.The second layer metal layer of cathode side contacts with Ohmic electrode, and further becomes the underlayer electrode of the 3rd layer of plating Au layer that forms negative electrode joint contact, and anode-side makes both sides' figure overlapping fully equally.Schottky electrode 31 since the end position of its figure need be configured in polyimide layer above, so, carry out graphic making at the cathode side 16 μ m that overlap at the regional 31a periphery of schottky junction.Substrate beyond the schottky junction portion is a cathode potential, in the part of anode electrode 34 with the GaAs intersection that forms cathode potential, for insulation is provided with polyimide layer 30.The area of this cross section forms 1300 μ m
2About, owing to have big parasitic capacitance, need make its spacing distance is thickness about 6～7 μ m, relaxes parasitic capacitance.Polyimides is used as interlayer insulating film according to the character of its low dielectric constant and very heavy back formation.
Withstand voltage and the good Schottky characteristic of schottky junction zone 31a about in order to ensure 10V is arranged on 3 * 10
17Cm
-3About n type epitaxial loayer 23 on.In addition, Ohmic electrode 28 to take out resistance and is located at by mesa etching and makes on the surface of its n+ type epitaxial loayer 22 that exposes in order to reduce.The lower floor of n+ type epitaxial loayer 22 is the GaAs substrate 21 of high concentration, is provided with AuGe/Ni/Au as Ohmic electrode 28 as backplate, also can the corresponding machine that takes out from substrate back.
Fig. 7 to Figure 11 represents the manufacture method of existing Schottky barrier diode.
Among Fig. 7, utilize mesa etching that n+ type epitaxial loayer 22 is exposed, adhere to the ground floor metal level and form Ohmic electrode 28.
That is to say, at the n+ type epitaxial loayer 22 (5 * 10 about lamination 6 μ m on the n+ type GaAs substrate 21
18Cm
-3), pile up for example n type epitaxial loayer 23 (1.3 * 10 of 3500 more thereon
17Cm
-3).Then, cover whole, carry out photoetching process, optionally window at the resist layer of predetermined Ohmic electrode 28 with oxide-film 25.Then, be the oxide-film 25 of predetermined Ohmic electrode 28 parts of mask etching with this resist layer, and carry out the mesa transistor etching of n type epitaxial loayer 23, n+ type epitaxial loayer 22 is exposed.
Then, vacuum evaporation and lamination ground floor metal level are these three layers of AuGe/Ni/Au successively.Afterwards, remove resist layer, stay metal level in predetermined Ohmic electrode 28 parts.Then, on n+ type epitaxial loayer 22, form Ohmic electrode 28 by Alloying Treatment.
Among Fig. 8, form Schottky contacts hole 29.On whole, form new resist layer, carry out photoetching process, optionally window in predetermined schottky junction zone 31a part.Then, the oxide-film 25 that etching is exposed is removed resist afterwards, the Schottky contacts hole 29 that the n type epitaxial loayer 23 of the schottky junction zone 31a portion that formation is predetermined exposes.
Among Fig. 9, the polyimide layer 30 that is formed for insulating.The several coating polyimide is provided with thick polyimide layer 30 on whole.On whole, form new resist layer, carry out photoetching process, optionally window, thereby stay predetermined polyimide layer 30 parts.Then, Wet-type etching and remove the polyimides that exposes.Then, remove resist layer, polyimide layer 30 is solidified, form the thickness of 6～7 μ m.
Among Figure 10, the n type epitaxial loayer 23 that exposes in the etching Schottky contacts hole 29 forms Schottky electrode 31.
With the oxide-film 25 around the Schottky contacts hole 29 is mask etching n type epitaxial loayer 23.As previously mentioned, after Schottky contacts hole 29 forms, form polyimide layer 30 under the state that exposes on n type epitaxial loayer 23 surfaces.Schottky junction must be formed on the peace and quiet GaAs surface, therefore, be before Schottky electrode forms etching n type epitaxial loayer 23 surfaces.And 2500 in order to ensure as action layer optimum thickness will critically control temperature and time, carry out Wet-type etching and make thickness become 2500 from 3500 .
Then, vacuum evaporation Ti/Pt/Au successively, the Schottky electrode 31 and the cathode electrode 35 that form the underlayer electrode of double as anode electrode are used underlayer electrode.
Among Figure 11, become the Au coating of anode electrode 34 and cathode electrode 35.
Expose at the underlayer electrode that makes predetermined anode electrode 34 and cathode electrode 35 parts, cover other parts with resist layer after, carry out electrolytic gold plating.At this moment, resist layer becomes mask, advances the part of exposing at underlayer electrode and adheres to gold-platedly, forms anode electrode 34, cathode electrode 35.Underlayer electrode is located on whole, after removing resist, carries out ion(ic) etching with the Ar plasma, and the underlayer electrode of not gold-plated part of pruning carries out the shape that graphic making forms anode and cathode electrode 34,35.At this moment, though how many gold-plated parts is also pruned, has the thickness about 6 μ m, so no problem.
Then,, carry out Alloying Treatment, form the Ohmic electrode 28 at the back side back side evaporation AuGe/Ni/Au successively.
After the current operation of compound semiconductor Schottky barrier diode is finished, enter the back operation of assembling.The semiconductor chip of wafer-like is cut, be separated into independent semiconductor chip, this semiconductor chip is fixedly mounted on the framework (not shown), then, connects the anode of semiconductor chip and the lead-in wire (not shown) that negative electrode engages contact and regulation with bonding wire.Bonding wire uses metal wire, connects with known stitch bonding.Then, transmit mould mould dress, carry out resin-encapsulated.
Summary of the invention
The board structure of existing Schottky barrier diode forms the structure that can corresponding multimachine kind also can take out negative electrode from the back side, be formed on the n+ type GaAs substrate n+ type epitaxial loayer be set, and for the characteristic guaranteeing to stipulate thereon layer be provided with 1.3 * 10
17Cm
-3About the structure of n type epitaxial loayer.
Schottky electrode must be guaranteed the characteristic stipulated, thus the peace and quiet surface of n type epitaxial loayer is exposed, and evaporation metal, form schottky junction.Ohmic electrode will form ohm knot at the n+ of its lower floor type epitaxial loayer in order to reduce taking-up resistance.
There is following problems in existing manufacture method.
The first, schottky junction zone 31a schottky junctions is combined on the n type epitaxial loayer 23 of the superiors, is i.e. 2500 of optimum thickness that guarantee to consider to move behind the withstand voltage and resistance of layer, and the n type epitaxial loayer 23 from about 3500 is etched to 2500 and forms.The etching of this moment is a Wet-type etching, and the control of the amplitude of the interior wafer of time and temperature and etching solution, vibration velocity etc. is very difficult, and, must in the fresh keeping time of regulation, use etching solution.Therefore, use this method, can produce deviation, the reproducibility of the characteristic of very difficult realization operating space and the raising of high frequency characteristics because of wafer is different.
The second, owing to adopt mesa structure, need to increase the mesa etching of operation amount, meeting produces bad because of the deviation of the connecting airtight property of resist film and oxide-film.In addition, need simultaneously to form operation and the gold-plated formation operation etc. of the taking-up of electrode is set on polyimide layer, have that manufacturing process is complicated, problems such as efficient is low on the time as the polyimide layer of interlayer dielectric.
Compound semiconductor is because this height of price of its substrate so in order to rationalize, simplification and the efficient activity of seeking manufacturing process are important topics, simultaneously, expects to obtain the characteristic of the good and stable Schottky barrier diode of reproducibility.
The present invention develops with regard to being based on above-mentioned problem, it provides a kind of manufacture method of Schottky barrier diode, this method comprises: lamination one conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, the operation in formation one conductive high concentration ion implanted region territory on the compound semiconductor layer surface under the first predetermined electrode; Form the operation that is first electrode of ohm knot with the high concentration ion injection zone; Behind evaporation schottky metal on the compound semiconductor layer surface, heat-treat, make the part diffusion of schottky metal be embedded to compound semiconductor layer, form the operation that forms second electrode of schottky junction with the epitaxial layer interface of compound semiconductor layer lower floor; Form the operation of the metal level that contacts with first and second electrode respectively.This method can realize the simplification and the efficient activity of manufacturing process, and reproducibility is good, stability of characteristics and can improve high frequency characteristics.
Description of drawings
Fig. 1 is the profile of explanation semiconductor device of the present invention;
Fig. 2 is the profile of the manufacture method of explanation semiconductor device of the present invention;
Fig. 3 is the profile of the manufacture method of explanation semiconductor device of the present invention;
Fig. 4 is the profile of the manufacture method of explanation semiconductor device of the present invention;
Fig. 5 is the profile of the manufacture method of explanation semiconductor device of the present invention;
Fig. 6 is the profile of the existing semiconductor device of explanation;
Fig. 7 is the profile of the manufacture method of the existing semiconductor device of explanation;
Fig. 8 is the profile of the manufacture method of the existing semiconductor device of explanation;
Fig. 9 is the profile of the manufacture method of the existing semiconductor device of explanation;
Figure 10 is the profile of the manufacture method of the existing semiconductor device of explanation;
Figure 11 is the profile of the manufacture method of the existing semiconductor device of explanation.
Embodiment
Describe embodiments of the invention in detail referring to figs. 1 through Fig. 5.
Schottky barrier diode of the present invention comprises: compound semiconductor substrate 1; High concentration epitaxial loayer 2, epitaxial loayer 3 and stable compound semiconductor layer 4; High concentration ion injection zone 7; First electrode 8; Second electrode 11; With metal level 14,15.
Fig. 1 is the profile of operating space part.
InGaP layer 4 surface that high concentration ion injection zone 7 is set under Ohmic electrode 8 arrive n+ type epitaxial loayer 2.Along circular Schottky electrode 11 periphery settings, with the roughly overlapping setting of Ohmic electrode 8, the spacing distance of Schottky electrode 11 and high concentration ion injection zone 7 is 1 μ m.That is to say, replace the existing situation that adopts mesa structure, be formed on the structure that high concentration ion injection zone 7 is set under the situation that keeps planar structure from the teeth outwards, table top is not set realizes ohm knot.
Schottky electrode 11 as second electrode is second layer metal layers of evaporation Pt/Ti/Pt/Au successively.Drawing forms the circle of diameter 10 μ m, with the n type epitaxial loayer 3 formation schottky junctions of InGaP layer 4 lower floor.
In order to obtain the withstand voltage characteristic that waits regulation, its thickness is preferably 2500 as the n type epitaxial loayer 3 of operating space.By InGaP layer 4 is set, n type epitaxial loayer 3 by 4 protection of InGaP layer, can form high-quality, high-precision schottky junction with the n type epitaxial loayer 3 of 2500 before will forming Schottky electrode 11.In addition, because InGaP layer 4 is non-doping, so can suppress the generation of electric capacity of the schottky junction side surface part of second layer metal layer formation.
Metal level is to be the evaporated metal layer that Ti/Pt/Au constitutes by forming anode electrode 14 and cathode electrode 15 the 3rd layer.Anode electrode 14 contacts with Schottky electrode 11, extends to the anodic bonding zone, forms anodic bonding contact 14a.And by the GaAs insulation of nitride film 5 with Ohmic electrode 8 or cathode potential.
Under the anodic bonding contact 14a of portion, inject the zone 6 that boron etc. is provided with insulation (following it is called insulating regions).The insulating regions 6 that utilize to arrive non-Doped GaAs substrate can be with the GaAs and anode electrode 14 insulation of cathode potential, directly wire bonds portion are fixedly mounted on the substrate so can not establish polyimides and nitride film.
Fig. 2 to Fig. 5 describes the manufacture method of Schottky barrier diode of the present invention in detail.
The manufacture method of Schottky barrier diode comprises: lamination one conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, the operation in formation one conductive high concentration ion implanted region territory on the compound semiconductor layer surface under the first predetermined electrode; Form the operation that is first electrode of ohm knot with the high concentration ion injection zone; Behind evaporation schottky metal on the compound semiconductor layer surface, heat-treat, make the part diffusion of schottky metal be embedded to compound semiconductor layer, form the operation that forms second electrode of schottky junction with the epitaxial layer interface of compound semiconductor layer lower floor; Form the operation of the metal level that contacts with first and second electrode respectively.
As shown in Figure 2, in first operation of the present invention, lamination one conductivity type epitaxial loayer 3 and stable compound semiconductor layer 4 on non-doped compound semiconductor substrate 1 form a conductive high concentration ion implanted region territory 7 on compound semiconductor layer 4 surfaces under the first predetermined electrode 8.
This operation is the operation that constitutes feature of the present invention, and the n type epitaxial loayer 3 that connects the zone of predetermined formation Ohmic electrode 8 forms high concentration ion injection zone 7 up to n+ type epitaxial loayer 2.
That is to say, on non-Doped GaAs substrate 1, pile up the n+ type epitaxial loayer 2 (5 * 10 of 5000
18Cm
-3), pile up the n type epitaxial loayer 3 (1.3 * 10 of 2500 thereon
17Cm
-3).Layer is provided with the non-doping InGaP layer 4 of 200 thereon again.Here InGaP layer 4 is stable compound semiconductor layers, forms the passivating film that protection GaAs is not subjected to external contamination.
, with nitride film 5 cover whole, resist layer is set, carry out photoetching process, the resist layer on the predetermined insulating regions 6 is optionally windowed thereafter.Then, be mask with this resist layer, ion injects B+ impurity, forms the insulating regions 6 until non-Doped GaAs substrate 1, realizes the GaAs of cathode potential and the insulation of anodic bonding contact 14a.
Then, carry out photoetching process, the resist layer on the zone of predetermined formation high concentration ion injection zone 7 is optionally windowed.Then, be mask with this resist layer, ion injects the n type impurity (Si+, 1 * 10 of high concentration
18Cm
-3About), InGaP layer 4, the n type epitaxial loayer 3 of Ohmic electrode 8 parts that perforation is predetermined form the high concentration ion injection zone 7 up to n+ type epitaxial loayer 2.At this moment, ion injects by under different conditions, injects several times to wait and carries out, and makes the impurity concentration of high concentration ion injection zone 7 even as far as possible at depth direction.
Then, remove resist layer, the cvd nitride film 5 once more, carry out the activation annealing of high concentration ion injection zone 7 and insulating regions 6.
As shown in Figure 3, in the present invention's second operation, form first electrode 8 that is ohm knot with high concentration ion injection zone 7 surfaces.
On whole, form resist layer, carry out photoetching process, the part of predetermined formation Ohmic electrode 8 is optionally windowed.Remove the nitride film 5 that exposes from resist layer, the ground floor of vacuum evaporation lamination successively metal level is these three layers of AuGe/Ni/Au.Then, remove resist layer, stay the ground floor metal level in predetermined Ohmic electrode 8 parts by peeling off.Then utilize Alloying Treatment, form Ohmic electrode 8 on high concentration ion injection zone 7 surfaces.
As shown in Figure 4, in the 3rd operation of the present invention, behind evaporation schottky metal 10 on compound semiconductor layer 4 surfaces, heat-treat, make the part diffusion of schottky metal 10 be embedded to compound semiconductor layer 4, form second electrode 11 that forms schottky junction with epitaxial loayer 3 interfaces of compound semiconductor layer 4 lower floors.
This operation is the operation that constitutes feature of the present invention, after the evaporation schottky metal 10, heat-treats on InGaP layer 4 surface, and that utilizes schottky metal 10 imbeds the formation schottky junction.
In Fig. 4 (A), on whole, form new resist layer, carry out photoetching process, predetermined Schottky electrode 11 parts are optionally windowed.Behind the nitride film 5 that dry-etching exposes, the Schottky contacts hole 9 that the InGaP layer 4 that the Schottky electrode that formation is scheduled to is 11 ones exposes.Then on whole order vacuum evaporation and lamination as these four layers of the second layer metal layer Pt/Ti/Pt/Au of schottky metal 10.Then, remove resist layer, stay schottky metal layer 10 in Schottky contacts hole 9 by peeling off.
In Fig. 4 (B), then heat-treat up and down at 400 ℃.Make schottky metal 10 undermost Pt be diffused into InGaP layer 4 by heat treatment, thereby, schottky metal 10 is embedded in, arrive the interface of n type epitaxial loayer 3.Like this, do not carry out the etching control of existing complexity and form the Schottky electrode 11 that forms schottky junction with n type epitaxial loayer 3.That is to say that before will forming schottky junction, the GaAs interface is all covered by InGaP, can very form schottky junction under the good state at the GaAs interface.And the heat treatment of imbedding stops to imbed at InGaP layer 4, and the n type epitaxial loayer 3 that forms operating space can be kept 2500 that can obtain predetermined characteristic.Here, schottky metal 10 just is not limited to above-mentioned situation so long as orlop is the evaporated metal layer of Pt.
That is to say, utilize the InGaP layer 4 as passivating film can easily form Schottky electrode 11, this Schottky electrode 11 forms good schottky junction with n type epitaxial loayer 3 surfaces.In existing manufacture method, control such as the precision of the amplitude of the wafer in time and temperature and the etching solution, vibration velocity etc. is difficulty very, and, require in the fresh keeping time of regulation, to use etching solution.But manufacturing method according to the invention by being pre-formed the epitaxial loayer 3 as 2500 best of action layer, is utilized heat treatment, is that the InGaP layer is imbedded in the schottky metal layer diffusion of Pt with orlop, and like this, the action Thickness Control is easy.And, do not carry out complicated at present etching control, before forming schottky junction,,, can make the Schottky barrier diode of stability of characteristics so can form the good schottky junction of reproducibility by the surface of InGaP layer protection n type epitaxial loayer.
As shown in Figure 5, the 4th operation of the present invention is to form the metal level 14,15 that contacts with first electrode 8 and second electrode 11 respectively.
This operation also is the operation that constitutes feature of the present invention, in order to take out Schottky electrode 11 and Ohmic electrode 8, form the evaporated metal layer that constitutes anode electrode 14 and cathode electrode 15.
At first, at the nitride film 5 of deposit about once more on whole as 5000 of interlayer dielectric.Form resist layer, carry out photoetching process Schottky electrode 11, Ohmic electrode 8 and anodic bonding contact 14a, negative electrode joint contact 15a part selectivity as contact site are windowed, nitride film 5 is carried out etching.After removing resist, new resist layer is set again, carry out photoetching process the figure selecting of required anode electrode 14, cathode electrode 15 is windowed.Evaporation Ti/Pt/Au successively on whole forms anode electrode 14 and cathode electrode 15 by peeling off, overlap joint (バ Star Network ラ Star プ) back side.
Here, anode electrode 14 and cathode electrode 15 are the evaporation metals that form with the common method of peeling off.And, with the interlayer dielectric of anode electrode 14 and cathode electrode 15 are nitride films 5, engage contact portion and also can directly be fixedly mounted on the substrate, so can omit polyimide layer.Like this, can omit at present on polyimide layer the distribution that is provided with for the defective of eliminating polyimides very heavy back and form the gold-plated process that engages contact.
The formation operation of present thick polyimide layer is owing to need coating for several times and solidify very time-consuming and complex procedures.And the formation operation of Gold plated Layer also is the main cause that increases the worker ordinal number.But manufacturing method according to the invention can be omitted these polyimide layers and Gold plated Layer and form operation, can realize the simplification significantly and the efficient activity of manufacturing process.
The compound semiconductor Schottky barrier diode after the operation, enters the back operation of assembling before finishing.The semiconductor chip of wafer-like is cut, and is separated into single semiconductor chip, and this semiconductor chip is fixedly mounted on after framework (not shown) goes up, and with bonding wire joint contact 14a, the 15a of semiconductor chip and the lead (not shown) of regulation is connected.The golden fine rule of bonding wire adopts known stitch type bonding method to connect.Then, transmit mould mould dress, carry out resin-encapsulated.
Manufacturing method according to the invention can obtain effect as follows.
The first, utilizing passivating film is that the InGaP layer can easily form with the N-shaped epi-layer surface and forms well The Schottky electrode of schottky junction. By being pre-formed the extension as 2500 best of action layer Layer 3 utilizes heat treatment, is that the InGaP layer is imbedded in the schottky metal layer diffusion of Pt with orlop, like this, The control of action layer thickness is easy. And, do not carry out the etching control of present complexity, forming Xiao Te Protect the surface of N-shaped epitaxial loayer by the InGaP layer before the base knot, thus the good schottky junction of repeatability can be formed, But the Schottky-barrier diode that manufacturing characteristics is stable.
In existing manufacture method, the amplitude of the wafer in time and temperature and the etching solution, vibration velocity etc. Precision control very difficult, and, require in the fresh keeping time of regulation, to use etching solution. But root According to manufacture method of the present invention, can improve yield rate, and form stable schottky junction, can suppress height The deviation of the very important characteristic of frequency circuit.
The second, manufacturing process can be raised the efficiency and simplify to the manufacturing of above-mentioned Schottky-barrier diode. Specifically Ground says, be mesa transistor etching work procedure, schottky junction form front N-shaped epitaxial loayer etching work procedure, Polyimide layer forms operation, gold-plated process etc. Because it is thick that polyimide layer will form 6～7 μ m, so Repeat to apply for several times and form. Coating polyimide layer is wanted spended time for several times, and manufacturing process is also complicated . And if do not need polyimides, then the electrode of Gold plated Layer also no longer needs. At present in order to prevent weldering Cracking and the distortion of the electrode that the stress the when heat when material is installed and wire-bonded causes must be guaranteed electricity The intensity of the utmost point forms anode electrode and cathode electrode by thick Gold plated Layer. But, if owing to do not need Polyimide layer just need not considered its impact. That is to say, no longer need gold-plated electrode, only the evaporation metal by Ti/Pt/Au can form anode electrode and cathode electrode, and reliability has also improved. And, owing to disappear Except the above-mentioned reason that causes that at present yield rate is low, so yield rate has also improved.
Three, form operation and gold-plated formation operation owing to can omit polyimide layer, so can disappear significantly Subtract cost.
That is to say, Schottky-barrier diode that repeatability has well stable high frequency characteristics can be provided Realize manufacturing process's simplification and high efficiency manufacture method.
Claims (5)
1, a kind of manufacture method of Schottky barrier diode is characterized in that, comprising: the operation of the compound semiconductor layer that lamination is stable on a conductivity type epitaxial loayer; Behind evaporation schottky metal on the described compound semiconductor layer surface, heat-treat, make the part diffusion of described schottky metal be embedded to described compound semiconductor layer, and form the operation of schottky junction with described epitaxial layer interface.
2, the manufacture method of Schottky barrier diode as claimed in claim 1, it is characterized in that, comprise: lamination one conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, the operation in formation one conductive high concentration ion implanted region territory on the described compound semiconductor layer surface under the first predetermined electrode; Form the operation that becomes first electrode of ohm knot with described high concentration ion injection zone; Behind evaporation schottky metal on the described compound semiconductor layer surface, heat-treat, make the part diffusion of described schottky metal be embedded to described compound semiconductor layer, form the operation that forms second electrode of schottky junction with the described epitaxial layer interface of described compound semiconductor layer lower floor; Form the operation of the metal level that contacts with described first and second electrode respectively.
3, the manufacture method of Schottky barrier diode as claimed in claim 1, it is characterized in that, comprise: lamination one conductive high concentration epitaxial loayer, a conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, the surface of the compound semiconductor layer under Yu Ding first electrode forms the operation in a conductive high concentration ion implanted region territory to described high concentration epitaxial loayer certainly; Form the operation that becomes first electrode of ohm knot with described high concentration ion injection zone; Behind evaporation schottky metal on the described compound semiconductor layer surface of the described first electrodes surrounding periphery, heat-treat, make the orlop diffusion of described schottky metal be embedded to described compound semiconductor layer, form the operation that forms second electrode of schottky junction with the described epitaxial layer interface of described compound semiconductor layer lower floor; Form the operation of the metal level that contacts with described first and second electrode respectively.
4, as the manufacture method of each described Schottky barrier diode of claim 1～3, it is characterized in that, described schottky metal with orlop be Pt the multiple layer metal layer successively evaporation form.
5, as the manufacture method of each described Schottky barrier diode of claim 1～3, it is characterized in that, before forming schottky junction, protect the surface of described epitaxial loayer by described compound semiconductor layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP228048/2001 | 2001-07-27 | ||
| JP228048/01 | 2001-07-27 | ||
| JP2001228048A JP2003046092A (en) | 2001-07-27 | 2001-07-27 | Method of manufacturing schottky barrier diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1400641A CN1400641A (en) | 2003-03-05 |
| CN1272836C true CN1272836C (en) | 2006-08-30 |
Family
ID=19060612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021272328A Expired - Fee Related CN1272836C (en) | 2001-07-27 | 2002-07-29 | Manufacture of Schottky-barrier diode |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2003046092A (en) |
| KR (1) | KR100612187B1 (en) |
| CN (1) | CN1272836C (en) |
| TW (1) | TW552708B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7282386B2 (en) * | 2005-04-29 | 2007-10-16 | Freescale Semiconductor, Inc. | Schottky device and method of forming |
| KR101284475B1 (en) * | 2005-11-22 | 2013-07-15 | 가부시끼가이샤 하이테크 시스템즈 | Method of manufacturing semiconductor device |
-
2001
- 2001-07-27 JP JP2001228048A patent/JP2003046092A/en active Pending
-
2002
- 2002-07-17 TW TW091115902A patent/TW552708B/en not_active IP Right Cessation
- 2002-07-26 KR KR1020020044132A patent/KR100612187B1/en not_active IP Right Cessation
- 2002-07-29 CN CNB021272328A patent/CN1272836C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003046092A (en) | 2003-02-14 |
| TW552708B (en) | 2003-09-11 |
| CN1400641A (en) | 2003-03-05 |
| KR20030010552A (en) | 2003-02-05 |
| KR100612187B1 (en) | 2006-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106549009B (en) | Stacked semiconductor device structure and manufacturing method thereof | |
| US6399996B1 (en) | Schottky diode having increased active surface area and method of fabrication | |
| US4028140A (en) | Semiconductor device manufacture | |
| TW561622B (en) | Schottky barrier diode and method of making same | |
| US7271068B2 (en) | Method of manufacture of semiconductor device | |
| US11139375B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
| JP7355496B2 (en) | Local semiconductor wafer thinning | |
| CN1272836C (en) | Manufacture of Schottky-barrier diode | |
| EP2779244A2 (en) | Method of forming a HEMT semiconductor device and structure therefor | |
| CN1279626C (en) | Shottky barrier diode and its manufacture | |
| CN1417867A (en) | Integrated schottky barrier diode and its manufacture | |
| CN1314131C (en) | Schottky-barrier diode and its manufacture | |
| CN115548110A (en) | Semiconductor device and method for manufacturing the same | |
| CN1279625C (en) | Shottky barrier diode and its manufacture | |
| CN1314132C (en) | Schottky-barrier diode and its manufacture | |
| CN107808825A (en) | Metal layer for semiconductor devices and forming method thereof | |
| CN114868231A (en) | Semiconductor element and method for manufacturing the same, and semiconductor device and method for manufacturing the same | |
| US6060757A (en) | High frequency RF diode with low parasitic capacitance | |
| CN209804659U (en) | Product structure of IGBT chip | |
| CN100470845C (en) | Shottky barrier diode and its manufacture | |
| US6682968B2 (en) | Manufacturing method of Schottky barrier diode | |
| CN108701694B (en) | High-voltage silicon carbide Schottky diode flip chip array | |
| US20240128215A1 (en) | Semiconductor device with stacked conductive layers and related methods | |
| US20230077430A1 (en) | Manufacturing method for semiconductor device | |
| US8710665B2 (en) | Electronic component, a semiconductor wafer and a method for producing an electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060830 |