CN115332185A - Power semiconductor wafer and preparation method - Google Patents
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Abstract
The invention relates to a power semiconductor wafer and a preparation method thereof, wherein the power semiconductor wafer comprises: the power semiconductor chip module comprises a plurality of power semiconductor chip areas, a plurality of scribing channel areas and an edge area, wherein the scribing channel areas and the edge area form a mechanical support area, the power semiconductor chip areas are located between the mechanical support areas, and the edge area is located at the periphery of the power semiconductor chip areas and the scribing channel areas; the thickness of the semiconductor material of the edge area is equal to that of the semiconductor material of the scribing channel area, and the thickness of the semiconductor material of the power semiconductor chip area is smaller than that of the mechanical support area, so that the mechanical support area forms a grid structure. The power semiconductor wafer can effectively reduce the fragment rate, is firmer than a circular ring structure in a mechanical structure, has no relation with the specific semiconductor material used, has strong universality and adaptability, and can be a power semiconductor chip with low on-resistance and low thermal resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductor wafers, and particularly relates to a power semiconductor wafer and a preparation method thereof.
Background
The substrate of a power semiconductor chip typically additionally increases the electrical and thermal resistance of the chip, degrading its performance. Taking a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as an example, in a latest generation 20V low voltage power MOSFET, the substrate resistance accounts for about 50% of the total resistance of the device. The substrate itself does not have any useful electrical properties, and serves only as a mechanical support during the wafer fabrication process to prevent wafer breakage.
Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a cross-sectional view of a wafer with an excess substrate of a power semiconductor chip removed according to the prior art, fig. 2 is a top view of the wafer with the excess substrate of the power semiconductor wafer removed according to the prior art, and fig. 3 is a cross-sectional view of a power semiconductor chip with a thin substrate and a peripheral scribe lane thereof according to the prior art. In fig. 1 and 2, the conventional ultra-thin wafer manufacturing technology still maintains a relatively thick semiconductor material region at the Edge (Edge) position, which serves as a mechanical support to provide sufficient mechanical strength to the wafer to prevent the wafer from being broken during the processing. In the regions within the edge regions (Die & Scribe Line), the wafer has thinner regions of semiconductor material relative to the edge positions, and the power semiconductor chips 100 and the dicing streets are located in these thinner regions. However, this technique is limited in that the grinding equipment for achieving selective thinning is expensive; the back of the wafer after local thinning is uneven, so that the wafer cannot be compatible with most of general equipment such as a photoetching machine, a sputtering machine and the like, and the wafer is easy to crack in the process; the wafer is divided by removing the semiconductor material region with thicker edge first, which increases the complexity of the process.
In fig. 3, the heavily doped n + substrate can be reduced from about 200 microns to about 50 microns, which effectively reduces the on-resistance and thermal resistance of the chip. However, the prior art is limited in that the risk of wafer breakage during grinding will rise sharply if the substrate is further thinned. Taking optimosm 5 from the british flying example, in a 30V MOSFET, even though the substrate thickness has been thinned to 60 μm, its parasitic resistance still accounts for 14% of the on-resistance, and its parasitic resistance still accounts for more than 50% of the thermal resistance.
In summary, the conventional power semiconductor wafer and the manufacturing method thereof have the problems that the wafer is easy to crack, the manufacturing process is complex, the cost is high, and the electrical performance of the chip and the thickness of the substrate cannot be achieved.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a power semiconductor wafer and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
an embodiment of the present invention provides a power semiconductor wafer, including: a plurality of power semiconductor chip regions, a plurality of scribe line regions and a margin region, wherein,
the scribing channel areas and the edge areas form mechanical supporting areas, the power semiconductor chip areas are located between the mechanical supporting areas, and the edge areas are located on the peripheries of the power semiconductor chip areas and the scribing channel areas;
the thickness of the semiconductor material of the edge area is equal to that of the semiconductor material of the scribing channel area, and the thickness of the semiconductor material of the power semiconductor chip area is smaller than that of the semiconductor material of the mechanical support area, so that the mechanical support area forms a grid structure.
In an embodiment of the present invention, the back surface of the wafer is provided with a plurality of grooves corresponding to the plurality of power semiconductor chip regions one to one.
In one embodiment of the present invention, the back surface structure of the power semiconductor chip in the power semiconductor chip area is located in the groove, and the sum of the thickness of the semiconductor material of the power semiconductor chip area and the thickness of the back surface structure is equal to the thickness of the mechanical support area.
In one embodiment of the invention, the backside structure comprises a backside metal layer.
In one embodiment of the present invention, the back side structure comprises a field stop region, an implanted region and a back side metal layer, wherein the field stop region is located on the implanted region and the implanted region is located on the back side metal layer.
In one embodiment of the invention, the power semiconductor chip in the power semiconductor chip area comprises one or more of a diode, a schottky diode, a power field effect transistor, and an insulated gate bipolar transistor.
In one embodiment of the invention, the semiconductor material comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride.
Another embodiment of the present invention provides a method for manufacturing a power semiconductor wafer, including the steps of:
forming a front structure of the power semiconductor chip, and exposing the semiconductor substrate on the back of the wafer;
removing a part of the semiconductor substrate corresponding to the front surface structure to form a groove;
preparing a back structure of the power semiconductor chip in the groove and carrying out planarization treatment;
and patterning the top layer metal in the front structure to form a latticed power semiconductor wafer.
In an embodiment of the present invention, removing a portion of the semiconductor substrate corresponding to the front structure to form a recess includes:
and self-aligning and removing a part of the semiconductor substrate corresponding to the front structure by an electrochemical etching method to form the groove.
In an embodiment of the present invention, preparing the back structure of the power semiconductor chip in the groove and performing a planarization process includes:
preparing a back metal layer of the power semiconductor chip in the groove, and carrying out planarization treatment; or preparing the field stop region, the injection region and the back metal layer of the power semiconductor chip in the groove in sequence, and carrying out planarization treatment.
Compared with the prior art, the invention has the beneficial effects that:
1. in the power semiconductor wafer, the mechanical support region simultaneously comprises an edge region and a scribing channel region, so that the mechanical support region has enough thickness; meanwhile, the thickness of the semiconductor material in the edge area is consistent with that of the semiconductor material in the scribing channel area, and the thickness of the semiconductor material in the power semiconductor chip area is smaller than that of the semiconductor material in the mechanical support area, so that the mechanical support area forms a grid structure; compared with the circular ring structure in the prior art, the reticular supporting structure is firmer, is favorable for keeping the whole firmness of the wafer, can effectively reduce the fragment rate, is irrelevant to the specific semiconductor material used, has strong universality and adaptability, and can have the advantages of low on-resistance and low thermal resistance.
2. The manufacturing method of the power semiconductor wafer can realize the latticed power semiconductor wafer, and has the advantages of good process compatibility, universal processing equipment, high production yield and lower preparation cost.
Drawings
FIG. 1 is a cross-sectional view of a wafer with excess substrate removed from a power semiconductor chip according to the prior art;
FIG. 2 is a top view of a wafer with excess substrate of a power semiconductor chip removed according to the prior art;
FIG. 3 is a cross-sectional view of a power semiconductor chip with a thin substrate and its peripheral scribe lines provided in the prior art;
FIG. 4 is a cross-sectional view of a power semiconductor wafer according to an embodiment of the present invention;
FIG. 5 is a top view of a power semiconductor wafer according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a power semiconductor chip and scribe lanes with a thinned substrate according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating an initial state of a power semiconductor chip, a top metal layer and an edge scribe lane according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a power semiconductor chip, a top metal layer, and an edge scribe line after electrochemical etching according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a power semiconductor chip, a top metal layer, and an edge scribe line after backside metal deposition according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a power semiconductor chip, a top metal layer, and an edge scribe line after backside CMP according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a power semiconductor chip, a top metal layer, and an edge scribe line patterned by front metal according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 4, fig. 5 and fig. 6, fig. 4 is a cross-sectional view of a power semiconductor wafer according to an embodiment of the present invention, fig. 5 is a top view of a power semiconductor wafer according to an embodiment of the present invention, and fig. 6 is a cross-sectional view of a power semiconductor chip and a scribe lane having a thinned substrate according to an embodiment of the present invention, where the power semiconductor wafer of fig. 4 and fig. 5 is a wafer after removing an excess substrate of the power semiconductor chip, filling metal, and performing chemical mechanical polishing.
The power semiconductor wafer includes: a plurality of power semiconductor chip regions, a plurality of scribe line regions and a margin region. The scribing channel areas and the edge areas form mechanical supporting areas, the power semiconductor chip areas are located between the mechanical supporting areas, and the edge areas are located on the peripheries of the power semiconductor chip areas and the scribing channel areas; the thickness of the semiconductor material of the edge area is equal to that of the semiconductor material of the scribing channel area, and the thickness of the semiconductor material of the power semiconductor chip area is smaller than that of the semiconductor material of the mechanical support area, so that the mechanical support area forms a grid structure.
As shown in fig. 4 and 5, a plurality of power semiconductor chip regions (Die) 200 are distributed at intervals, a plurality of Scribe Line regions are distributed around the plurality of power semiconductor chip regions in a criss-cross manner, and an Edge region (Edge) surrounds the plurality of Scribe Line regions and the plurality of Scribe Line regions, wherein the plurality of Scribe Line regions and the Edge region form a mechanical support region to form a support structure of the power semiconductor wafer.
As shown in fig. 4 and 6, the thickness of the semiconductor material in the edge region is equal to that of the scribe lane region, and the thickness of the semiconductor material in the power semiconductor chip region is smaller than that of the scribe lane region. Furthermore, since the semiconductor material thickness of the power semiconductor chip region (Die) is smaller than that of the mechanical support region, and the Scribe lane (Scribe Line) regions are distributed in a staggered manner, the mechanical support region forms a grid structure, and the power semiconductor chip region is located in a grid in the grid structure.
Specifically, the fact that the thickness of the semiconductor material in the power semiconductor chip area is smaller than that of the semiconductor material in the mechanical support area means that the semiconductor material on the front side of the power semiconductor chip area is flat and flat with the semiconductor material on the front side of the mechanical support area, the semiconductor material on the back side is thinned and recessed, so that the thickness of the semiconductor material in the power semiconductor chip area is smaller than that of the semiconductor material in the mechanical support area, and at the moment, the back side of the power semiconductor wafer is of a grid-shaped structure.
In the embodiment, the semiconductor material region with sufficient thickness and serving as the mechanical support is not only at the edge of the wafer, but also at the scribing channel, so that the mechanical support region has a net-shaped structure, rather than a ring structure in the prior art, the net-shaped support structure is more favorable for keeping the whole wafer firm, and the fragment rate can be effectively reduced. At the same time, the semiconductor material (substrate) thickness of the chip can be lower than the chip substrate in the existing ring structure under the more robust support network condition, thereby achieving lower electrical and thermal resistance.
In one embodiment, the back surface of the wafer is provided with a plurality of grooves corresponding to a plurality of power semiconductor chip areas one by one.
Specifically, the back semiconductor material of the power semiconductor chip area is thinned and recessed to form a plurality of grooves, and the grooves correspond to the power semiconductor chip areas one to one.
In a specific embodiment, the back structure of the power semiconductor chip in the power semiconductor chip area is located in the groove, and the sum of the thickness of the semiconductor material of the power semiconductor chip area and the thickness of the back structure is equal to the thickness of the mechanical support area.
Specifically, the power semiconductor chip area is used for preparing a power semiconductor chip, and the back surface structure of the prepared power semiconductor chip is embedded in a groove on the back surface of the power semiconductor chip area; and the sum of the thickness of the back surface structure of the power semiconductor chip and the thickness of the semiconductor material is equal to the thickness of the mechanical support area, so that the back surface of the power semiconductor wafer is kept flat.
In this embodiment, the power semiconductor chip has a relatively thin semiconductor material layer and a thicker backside structure in the mechanically supported mesh structure. Due to the filling effect of the back structure, the whole thickness of the chip is equivalent to that of the mechanical support network, and the back of the wafer can still be kept flat. The flat wafer backside enables the wafer to be compatible with most common processing equipment such as photolithography, sputtering, glue applicators, and the like.
In a particular embodiment, the backside structure includes a backside metal layer.
Specifically, if the substrate is an n + type substrate, an n-type semiconductor material, a p-type semiconductor material and an Anode (Anode) are sequentially arranged on the substrate, and a metal cathode is prepared in a groove on the back surface of the wafer, at this time, the power semiconductor chip is in a p-i-n diode structure.
In this embodiment, the heavily doped n-type region is labeled as n + And the heavily doped region usually has a thickness of between 1 × 10 19 cm -3 And 1X 10 21 cm -3 Doping concentration in between; the lightly doped n-type region is marked as n - And the lightly doped region usually has a thickness of between 1 × 10 13 cm -3 And 1X 10 17 cm -3 Doping concentration in between; the p-type region is labeled p.
In a specific embodiment, the back structure includes a field stop region, an implant region and a back metal layer, wherein the field stop region is located on the implant region and the implant region is located on the back metal layer.
In particular, if the substrate is n - A p-type substrate, a p-type well semiconductor material (emitter), silicon dioxide and a polysilicon gate sequentially arranged on the substrate, and n-type well semiconductor material (emitter) sequentially prepared in a groove on the back of the wafer + Field stop region, p + An implant region and a metal collector, in which case the power semiconductor chip is an Insulated Gate Bipolar Transistor (IGBT).
In a specific embodiment, the power semiconductor chip of the present embodiment includes one or more of a diode, a schottky diode, a power field effect transistor, and an insulated gate bipolar transistor.
In particular, almost all types of power devices may benefit from a relatively thinner substrate, and thus power semiconductor devices suitable for use with the present embodiments include p-i-n diodes, schottky diodes, power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), insulated Gate Bipolar Transistors (IGBTs), and the like. Further, the present embodiment is also applicable to hybrid devices based on these device structures, such as reverse conducting IGBTs, schottky integrated power (MOSFETs), and the like.
In a particular embodiment, the semiconductor material comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride.
Compared with the prior art, the wafer in the embodiment is firmer in mechanical structure, has nothing to do with the specific semiconductor material used, can be selected by technicians according to actual conditions, and is wide in application range and high in universality.
In the power semiconductor wafer of the embodiment, the mechanical support region includes both the edge region and the scribe lane region, so that the mechanical support region has a sufficient thickness; meanwhile, the thickness of the semiconductor material in the edge area is consistent with that of the semiconductor material in the scribing channel area, and the thickness of the semiconductor material in the power semiconductor chip area is smaller than that of the semiconductor material in the mechanical support area, so that the mechanical support area forms a grid structure; compared with a circular ring structure in the prior art, the reticular supporting structure is firmer in mechanical structure, is favorable for keeping the whole firm of the wafer, can effectively reduce the fragment rate, is irrelevant to the specific semiconductor material used, has strong universality and adaptability, and can have the advantages of low on-resistance and low thermal resistance.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a power semiconductor wafer, including:
s1, forming a front structure of the power semiconductor chip and exposing the semiconductor substrate on the back of the wafer.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating an initial state of a power semiconductor chip, a top metal layer and an edge scribe lane according to an embodiment of the present invention.
Specifically, a front structure of the power semiconductor chip is formed, top metal is reserved and is not patterned, and the semiconductor substrate on the back of the wafer is exposed through mechanical grinding or etching, so that the next step of electrochemical corrosion is facilitated. As shown in fig. 7, the front structure of the power semiconductor chip is completed, and only the top metal of the front is not patterned, and the top metal is used as an electrode for the subsequent electrochemical etching.
And S2, removing a part of the semiconductor substrate corresponding to the front surface structure to form a groove.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a state of a power semiconductor chip, a top metal layer and an edge scribe lane after electrochemical etching according to an embodiment of the present invention.
Specifically, the redundant semiconductor substrate aligned with the front-side diode structure is removed in a self-alignment manner by an electrochemical etching method, and the semiconductor material of the scribing channel and the edge region is reserved for mechanical support, so that a groove is formed on the back side of the wafer.
Specifically, the self-aligned removal of the redundant semiconductor substrate is based on directional etching of a controllable position by matching anode current with an etching solution. As shown in fig. 8, the electrochemical corrosion process is: power semiconductor chip 200 is connected to an external power source, exposing the bottom of the entire wafer to the etching solution. Taking a silicon wafer as an example, the electrochemical etching (etching) process of silicon can be divided into two stages, namely, oxidation and dissolution, taking a silicon material electrochemically etched in a Hydrogen Fluoride (HF) solution as an example, the oxidation stage is as follows: si + (n-m) h + →Si surface n+ +m e - The dissolving stage is as follows: si surface n+ →Si solution 4+ +(4-n)e - During both the oxidation and dissolution stages, electrons (e-) will be generated, which are extracted from the anode (top metal) through the p-i-n diode inside the chip 200. In this process, the scribe streets and the peripheral regions of the wafer cannot form conductive paths because they have no diode structure, and the corresponding substrate material at these locations will be retained to provide mechanical support for the entire wafer. In other words, the entire etching process is performed "self-aligned" based on the anode current without additional lithography. Furthermore, it should be noted that other semiconductor materials can be treated by "self-aligned" electrochemical etching if a suitable etching solution is selected, and the etching position can be controlled by controlling the etching current as long as a diode (or parasitic diode) conducting unidirectionally exists inside the power semiconductor chip.
And S3, preparing a back structure of the power semiconductor chip in the groove and carrying out planarization treatment.
In a specific embodiment, a back metal layer of the power semiconductor chip is prepared in the groove and is subjected to planarization treatment. Specifically, a back metal layer of the wafer is formed in the groove, and the back of the wafer is planarized by Chemical Mechanical Polishing (CMP). Furthermore, the back metal layer of the wafer is formed by electroplating. At this time, the prepared power semiconductor chip is a p-i-n diode.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating a power semiconductor chip, a top metal layer and an edge scribe lane after a back metal deposition according to an embodiment of the present invention. Specifically, the back metal of the power semiconductor chip is usually titanium, nickel, silver in sequence, wherein the silver is finally soldered with the package as a solderable material. For this embodiment, in order to planarize the backside of the wafer, a relatively thicker backside metal is required to fill the etched-away substrate portion. Electroplating can be used to prepare thicker backside metal layers. On the other hand, since the back metal layer in this embodiment is thick enough, cheaper metals such as copper, molybdenum, etc. can be used instead of silver without affecting the electrical and thermal properties. In addition, the back side metal may also be deposited physically, including but not limited to using sputtering and evaporation techniques.
It should be noted that, the p-i-n diode is used as a preferred embodiment to describe the manufacturing method, but schottky diodes, power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and Insulated Gate Bipolar Transistors (IGBTs) all have similar conductivity from the front side to the back side of the chip, and the method of this embodiment is also applicable to these devices.
In a specific embodiment, the field stop region, the injection region and the back metal layer of the power semiconductor chip are sequentially prepared in the groove, and are subjected to planarization treatment.
Specifically, a field stop region having the same conductivity type as the substrate and an implant region having a conductivity type opposite to the substrate and a back metal layer are sequentially formed in a groove of the back surface of the wafer, and the back surface of the wafer is planarized by Chemical Mechanical Polishing (CMP). At this time, the prepared power semiconductor chip is an insulated gate bipolar transistor.
Further, chemical Mechanical Polishing (CMP) is a commonly used planarization technique. Referring to fig. 10, fig. 10 is a schematic diagram illustrating a power semiconductor chip, a top metal layer and an edge scribe lane after a backside chemical mechanical polishing process according to an embodiment of the present invention. In this embodiment, since the back metal layer is not flat, the flatness of the back surface of the wafer is affected if the back metal layer is not planarized. After CMP, the excess metal on the scribe streets and edge locations is removed, while the backside metal of the chip 200 itself, i.e. the cathode of the power semiconductor chip 200, is hardly affected by the protection of the surrounding mechanical support structure.
And S4, patterning the top layer metal in the front structure to form a latticed power semiconductor wafer.
Specifically, the top metal in the front structure is patterned, and the preparation of the power semiconductor wafer is completed to obtain the latticed power semiconductor wafer. Referring to fig. 11, fig. 11 is a schematic diagram illustrating a power semiconductor chip, a top metal layer and an edge scribe lane after front metal patterning according to an embodiment of the present invention, and in fig. 11, after CMP, the back surface of the wafer is planarized, so that the front metal may be patterned by conventional photolithography, etching and photoresist removal to form an anode 200. After this step the wafer may be diced and packaged.
This embodiment differs from conventional thin wafer processes in that: the wafers in the whole process flow always keep enough mechanical strength, so that production equipment does not need to be newly added (upgraded) for processing thin wafers in a production line, and operators do not need to worry about the breakage of the wafers in a certain step due to insufficient mechanical strength.
The manufacturing method of the power semiconductor wafer can realize the latticed power semiconductor wafer, and has the advantages of good process compatibility, universal processing equipment, high production yield and lower preparation cost.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (10)
1. A power semiconductor wafer, comprising: a plurality of power semiconductor chip regions, a plurality of scribe line regions and a periphery region, wherein,
the scribing channel areas and the edge areas form mechanical supporting areas, the power semiconductor chip areas are located between the mechanical supporting areas, and the edge areas are located on the peripheries of the power semiconductor chip areas and the scribing channel areas;
the thickness of the semiconductor material of the edge area is equal to that of the semiconductor material of the scribing channel area, and the thickness of the semiconductor material of the power semiconductor chip area is smaller than that of the semiconductor material of the mechanical support area, so that the mechanical support area forms a grid structure.
2. The power semiconductor wafer according to claim 1, wherein a plurality of grooves corresponding to the plurality of power semiconductor chip areas one to one are disposed on the back surface of the wafer.
3. The power semiconductor wafer of claim 2, wherein the back surface structures of the power semiconductor chips in the power semiconductor chip areas are located in the recesses, and a sum of the thickness of the semiconductor material of the power semiconductor chip areas and the thickness of the back surface structures is equal to the thickness of the mechanical support area.
4. The power semiconductor wafer of claim 3, in which the back side structure comprises a back side metal layer.
5. The power semiconductor wafer of claim 3, wherein the back side structure comprises a field stop region, an implant region and a back side metal layer, wherein the field stop region is located on the implant region and the implant region is located on the back side metal layer.
6. The power semiconductor wafer of claim 1, wherein the power semiconductor chips in the power semiconductor chip area comprise one or more of diodes, schottky diodes, power field effect transistors, insulated gate bipolar transistors.
7. The power semiconductor wafer of claim 1, wherein the semiconductor material comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride.
8. A method for preparing a power semiconductor wafer is characterized by comprising the following steps:
forming a front structure of the power semiconductor chip, and exposing the semiconductor substrate on the back of the wafer;
removing a part of the semiconductor substrate corresponding to the front surface structure to form a groove;
preparing a back structure of the power semiconductor chip in the groove and carrying out planarization treatment;
and patterning the top layer metal in the front surface structure to form a grid-shaped power semiconductor wafer.
9. The method as claimed in claim 8, wherein removing a portion of the semiconductor substrate corresponding to the front side structure to form a recess comprises:
and self-aligning and removing a part of the semiconductor substrate corresponding to the front structure by an electrochemical etching method to form the groove.
10. The method for preparing a power semiconductor wafer according to claim 8, wherein preparing the back surface structure of the power semiconductor chip in the groove and performing planarization treatment comprises:
preparing a back metal layer of the power semiconductor chip in the groove, and carrying out planarization treatment; or preparing a field stop region, an injection region and a back metal layer of the power semiconductor chip in sequence in the groove, and carrying out planarization treatment.
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