CN1387258A - 键合区 - Google Patents

键合区 Download PDF

Info

Publication number
CN1387258A
CN1387258A CN02120137A CN02120137A CN1387258A CN 1387258 A CN1387258 A CN 1387258A CN 02120137 A CN02120137 A CN 02120137A CN 02120137 A CN02120137 A CN 02120137A CN 1387258 A CN1387258 A CN 1387258A
Authority
CN
China
Prior art keywords
district
bonding region
bonding
chip
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN02120137A
Other languages
English (en)
Inventor
F·B·哈伦
陈兰珠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1387258A publication Critical patent/CN1387258A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体集成电路装置的引线键合区,包括:可被探测器触点所触及的第一测试部分,和引线与其键合的第二引线键合部分,用于将键合区电连接到载体或引线框架。所提供的分离的测试部分防止引线键合部分在测试中被探测器触点所损坏。

Description

键合区
技术领域
本发明涉及集成电路，更具体地说涉及一种能使引线键合更可靠的键合区(bonding pad)。
背景技术
集成电路(IC)芯片是制作在半导体晶片(如硅晶片)上的小装置。通常，这种电路芯片从晶片上切割下来，然后，将该芯片上的键合区经引线键合电连接到载体引线或引线框架。芯片和引线键合用保护材料封装以制成组件。引线框架的引线从组件伸出，并终止于管脚，使芯片能与其它电路，如印刷电路板上的电路电连接。
然而，随着集成电路复杂性的不断增加，这种电路的尺寸正在减小。进而，在更小的区域里要求有更多的键合区，使得键合区的尺寸及键合区之间的间隔减小。图1A和1B示出了键合区尺寸和间隔的减小。从一个键合区中心到相邻键合区中心的度量单位称之为节矩(pitch)。图1A是芯片10的放大图，它有键合区12，节矩为90um，和图1B是芯片14的放大图，它有键合区14，节矩为50um。
在从其上形成有芯片的晶片上切割芯片之前，通过将探测器与键合区接触来检测芯片。探测器能在键合区上做出标记。虽然键合区的尺寸已被减小，但探测器技术还落后于引线键合技术。就是说，在键合区尺寸已减小时，用于测试的探测器触点的尺寸却还基本保持不变，使得键合区更容易被探测器损坏。正如本领域普通技术人员所知道的那样，极细小节矩的键合质量和可靠性受探测标记的面积、深度和用于探测键合区的频率的影响。
图2A是一对相邻芯片键合区20的顶视放大图，其上有探测器触点标出的探测标记22，图2B是已被探测器触点损坏的键合区24、26的顶视放大图。更具体地说，键合区24镀的金属已被刺破，并且键合区26已破裂。尺寸过大的探测器还可能在探测标记区域形成可能阻止金属化合增加的球形焊接。
参照图3，图3示出了传统键合区30。该键合区30用金属构成，如铜、铝和金。该键合区30包括围绕在该键合区30周边的边框32。该边框32通常由涂有聚酰亚胺(polymide)的金属层制成。该合区30宽度为X，长度为Y。对于节矩为63um的装置，X约为60um，Y约为90um，边框32宽约2um，和相邻键合区之间的间隔约3um。
键合区30的内区用于用引线键合技术将连接引线(未示出)连接于键合区30。引线键合通常使用以下三种工业标准技术中的一种来实现：使用压力和高温结合的热压(T/C)键合；使用压力、高温和超声波振动爆发结合的热声(T/S)键合；和使用压力和超声波振动爆发结合的超声波(U/S)键合。
标号34所示的圆形阴影区表示焊接球的有效直径，是球实际接触键合区30的尺寸。对于63um的节矩，要求焊接球的直径(BBD)约为45um。标号36所示的内部椭圆形区域表示探测器标记。如上所述，探测器标记可能损坏键合区，导致引线键合质量低和不可靠。
本发明的目的是提供一种使引线键合更可靠的键合区。
发明内容
为提供更可靠的引线键合，本发明提供一种集成电路装置的键合区，它有用于接纳探测器触点的第一区域，和连接引线可与其键合的第二区域。第一区和第二区最好用金属构成的隔离物分隔开。
本发明还提供一种集成电路装置的键合区，它具有用于接纳一个探测器触点和连接引线的第一区，和与第一区连续的第二区，第二区用于接纳另一个探测器触点和连接引线。
本发明进一步提供一种改进的集成电路键合区，它有金属隔离线，从键合区第一侧伸展到键合区相对的第二侧，隔离线形成键合区第一区和一个分开的键合区第二区，其中，键合区的第一区用于接纳探测器触点，和键合区的第二区用接纳将键合区连接到引线框架的键合引线的一端。
在另一实施方案中，本发明提供一种集成电路芯片的测试方法，该芯片具有多个键合区，包括如下步骤：将探测器触点放在至少一个芯片键合区的第一区上，用通过探测器触点连接于芯片的测试装置测试芯片，测试步骤完成后，将探测器触点从至少一个芯片键合区移开，并将一引线连接于至少一个芯片键合区的第二区。第二区与第一区分开。分隔还提供很好的对照，并且因此增强引线键合器的模式识别系统(PRS)，从而有更好的键合布局。键合布局对于极细小节距的情况是关键性的，标准要求是焊接球直径100％必须落在键合区尺寸之内。
附图说明
以上概述及以下对本发明优选实施方案的详细说明，结合附图可以更好地理解。为说明本发明之目的，附图示出优选实施方案。然而，可以理解，本发明并没有被限制于所示的具体结构及方法。在附图中：
图1A是具有其节矩为90um的键合区的传统芯片的顶视放大图；
图1B是具有其节矩为50um的键合区的传统芯片的顶视放大图；
图2A是具有探测标记的传统引线键合区的顶视放大图；
图2B是传统的引线键合区被探测器损坏的顶视放大图；
图3是传统芯片键合区的顶视放大图，示出球形焊区和探测器标记；
图4是芯片键合区的顶视放大图，示出本发明第一实施方案的球形焊区和探测标记；
图5是芯片键合区的顶视放大图，示出本发明第二实施方案的球形焊区和探测标记；和
图6是图4芯片键合区的剖面放大图。
具体实施方式
以下结合附图的详细说明是为了说明本发明当前的优选实施方案，且并不表示是本发明实践的唯一形式。可以理解的是，在不偏离本发明精神和范围下，相同或同等的功能可由不同实施方案来完成。相同编号用来表示相同元件。
如上所述，键合区尺寸的减少会使键合区更容易遭受到由探测器引起的损坏。该问题对节距极细小的键合区尤其明显。由于探测器标记面积、深度和探测频率对极细小节距的焊接质量和可靠性有很大影响，因此确定，为保证良好的焊接性，探测器标记的尺寸应小于约30％的BBD或16％的键合区开口。然而，遗憾地是使用现有探测技术，探测器标记的尺寸经常比所希望的键合区开口的16％要大。
解决方案之一是延长键合区的尺寸，使键合区尺寸有效地加倍，使得键合能够远离探测器标记进行。然而，该方案额外需要许多一般不容易得到的空间。
参照图4，图4示出的本发明第一实施方案的集成电路装置的键合区40。在键合区40中，为探测和键合提供独立的空间。该键合区40包括第一区42和与第一区42相邻的第二区44。分隔物46将第一区42与第二区44分隔开，并且，边框48围绕第一区42和第二区44的外周边伸展。分隔物46连接于边框48的第一侧和第二相对侧。
键合区的尺寸和形状应当使第一区42能接受一个探测器触点和连接引线或其它连接器，例如球性焊接，并且第二区44能接受另一探测器触点和连接引线。图中，第一区42示出探测器触点标记36，第二区44示出焊接球34的直径。
键合区40的宽度如A所示，和键合区40的长度如C所示。宽度A优选为给定节距的最小键合区宽度。长度C优选大于或约等于2A，以适合探测器的性能。分隔物46放置在使第一区42和第二区44的面积基本相等的位置。因此，在优选实施方案中，当键合区40整个为长方形时，第一区42和第二区44分别基本为正方形，以致宽度A等于第二区44高度B。然而，正如本领域普通技术人员所知道的，第一区42和第二区44不必是正方形。例如，图5示出键合区50的另一种形状，其中，宽度A和长度C基本相同，使得第一区52和第二区45是长方形形状。第二区54的长度B约为长度C的一半。形状类似键合区50的键合区最好用于芯片的角上。分隔提供良好的对照，并且因此增强引线键合器的模式识别系统(PRS)，以获得更好的键合布局。键合布局对于极细小节距的情况是关键性的，它要求焊接球直径100％必须落在键合区尺寸之内。
现参照图6，图6示出键合区40剖面的放大图。第一区42和第二区44可以制造成数层，包括氧化物层60，钛氮化物层62或本领域普通技术人员所知道的任何其它金属阻挡装置，和顶层64，优选至少用铝，铜和硅之一制成，正如本领域普通技术人员所知道的。制造中，第一区42和第二区44是一个连续的区域，并且，分隔物46和边框48被制造在该连续区域上。分隔物46和边框48优选用涂有聚酰亚胺(polymide)68的金属66制成。正如本领域普通技术人员所知道的，金属66和polymide68涂在顶层64上，并切然后刻蚀，以暴露出第一区42和第二区44。
再参照图4，边框48的宽度约为2um至30um。分隔物46的宽度优选更接近2um。分隔物46在第一区42和第二区44之间起隔离器的作用，以便使用做键合的区域明显地是一个单一的实体或单一的键合区区域，从而有利于键合对准工序。就是说，使第一区42和第二区44呈现为独立的空间，有利于引线键合模式识别系统(PRS)的操作。因此，有赖于制造能力和PRS探测及区分第一区42和第二区44的能力，分隔物可以小于2um宽。
如上所述，键合区40是很有用的，因为，它通过在一个键合区上为探测和引线键合提供分开的区域，以防止引线键合区域被探测器触点损坏。通过为引线键合提供分开的空间，引线键合空间使得热声键合(球焊)有良好的焊接性。没有附加的引线被键合在该键合区域的其他部分。
本发明还提供一种测试集成电路芯片的方法，该芯片包括多键合区，每个或某些键合区有第一和第二区。就是说，并不要求芯片的所有键合区都有分隔物46。例如，某些键合区可被指定用于探测或测试，而其他键合区并不要求与探测器触点为测试而接触。
在测试具有如上所述键合区的芯片时，探测器触点放置在至少一个芯片键合区40的第一区42上。随后，用通过探测器触点与芯片连接的现有测试装置测试芯片。当特定测试或全部测试完成时，探测器触点从该至少一个芯片键合区40移开。接下来，通过将引线连接于至少一个芯片键合区40的第二区44来完成引线键合。如上所述，本发明不限于任何特定的引线键合技术。
显然，本发明提供了一种新的键合区结构，使得探测器触点接触的区域和用于引线键合的区域相分开，从而导键合区域不会被探测器触点所损坏，并且，引线键合因此产生更可靠的键合。
对本发明优选实施方案进行的描述仅为解释及说明之目的，并不打将本发明包含在或限制在所公开的形式内。本领域普通技术人员在不偏离本发明实质精神的范围内，可对上述实施方案进行修改。例如，本发明并没有限制为任何一种单一的引线键合技术。而且，尽管本发明结合引线键合连接技术加以说明，但本发明可以应用其它连接技术，如直接芯片连接。因此，可以理解，本发明并没有被限制在所公开的具体实施方案，聚本发明通过其权利要求来涵盖在本发明的精神和范围内的改进。

Claims (14)

1.一种集成电路装置的键合区，包括：
接纳一探测器触点和一连接引线的第一区；
相邻于所述第一区的第二区，所述第二区是用于接纳另一探测器触点和连接引线；和
将所述第一区和所述第二区分隔开的分隔物，其中，所述分隔物用金属构成。
2.如权利要求1的键合区，其中，所述第一区和所述第二区的面积基本相等。
3.如权利要求2的键合区，其中，所述第一区和所述第二区基本为正方形。
4.如权利要求1的键合区，进一步包括一个围绕所述第一和第二区的外周边伸展的边框。
5.如权利要求4的键合区，其中，所述分隔物连接所述边框的第一侧和所述边框的第二相对侧。
6.如权利要求5的键合区，其中，所述分隔物用金属构成。
7.如权利要求6的键合区，其中，所述分隔物和所述边框的金属涂有聚酰亚胺。
8.如权利要求7键合区，其中，所述第一区和所述第二区至少用铝、铜和硅其中之一构成。
9.如权利要求1的键合区，其中，所述键合区的长度大于或等于所述键合区宽度的约两倍。
10.一种改进的半导体集成电路键合区，包括：
从所述键合区第一侧伸展到所述键合区第二相对侧的金属分隔线，所述分隔线形成键合区第一区和分开的键合区第二区，其中，所述键合区第一区是用于接纳一个探测器触点，所述键合区第二区是用于接纳将所述键合区连接到引线框架的键合引线的一端。
11.如权利要求10的键合区，其中，所述键合区的长度大于或等于所述键合区宽度的约两倍。
12.一种集成电路装置的键合区，包括：
用于接纳一个探测器触点和一连接引线的第一区；
与所述第一区连续的第二区，所述第二区是用于接纳另一个探测器触点和连接引线；
围绕所述键合区外周边形成的金属边框；和
连接所述边框第一侧和所述边框第二相对侧的金属分隔物，所述边框和所述分隔物限定出所述第一和第二区的面积。
13.如权利要求12的键合区，其中，所述键合区的长度大于或等于所述键合区宽度的约两倍。
14.一种测试集成电路芯片的方法，该芯片有多个键合区，所述方法包括如下步骤：
将探测器触点放置在至少一个芯片的第一区上；
用经该探测器触点连接于该芯片的测试装置测试该芯片；
测试步骤完成后，从该至少一个芯片键合区移去该探测器触点；和
将引线连接于该至少所述一个芯片键合区的第二区，其中，该第二区与该第一区连续，并且该第一和第二区被由金属构成的分隔物分隔开。
CN02120137A 2001-05-23 2002-05-21 键合区 Pending CN1387258A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/864,098 2001-05-23
US09/864,098 US6563226B2 (en) 2001-05-23 2001-05-23 Bonding pad

Publications (1)

Publication Number Publication Date
CN1387258A true CN1387258A (zh) 2002-12-25

Family

ID=25342528

Family Applications (1)

Application Number Title Priority Date Filing Date
CN02120137A Pending CN1387258A (zh) 2001-05-23 2002-05-21 键合区

Country Status (3)

Country Link
US (1) US6563226B2 (zh)
CN (1) CN1387258A (zh)
TW (1) TW543117B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784556B2 (en) * 2002-04-19 2004-08-31 Kulicke & Soffa Investments, Inc. Design of interconnection pads with separated probing and wire bonding regions
US6765228B2 (en) * 2002-10-11 2004-07-20 Taiwan Semiconductor Maunfacturing Co., Ltd. Bonding pad with separate bonding and probing areas
JP2005116724A (ja) * 2003-10-07 2005-04-28 Renesas Technology Corp 半導体装置及びその製造方法
JP4585327B2 (ja) * 2005-02-08 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100630756B1 (ko) * 2005-07-25 2006-10-02 삼성전자주식회사 개선된 패드 구조를 갖는 반도체 장치
JP5148825B2 (ja) * 2005-10-14 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US7947978B2 (en) * 2005-12-05 2011-05-24 Megica Corporation Semiconductor chip with bond area
US7955973B2 (en) * 2006-08-01 2011-06-07 Freescale Semiconductor, Inc. Method and apparatus for improvements in chip manufacture and design
US8198738B1 (en) * 2007-10-16 2012-06-12 Amkor Technology, Inc. Structure of bond pad for semiconductor die and method therefor
US8604625B1 (en) * 2010-02-18 2013-12-10 Amkor Technology, Inc. Semiconductor device having conductive pads to prevent solder reflow
US8242613B2 (en) 2010-09-01 2012-08-14 Freescale Semiconductor, Inc. Bond pad for semiconductor die

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404047A (en) 1992-07-17 1995-04-04 Lsi Logic Corporation Semiconductor die having a high density array of composite bond pads
US5342999A (en) 1992-12-21 1994-08-30 Motorola, Inc. Apparatus for adapting semiconductor die pads and method therefor
US5786701A (en) 1993-07-02 1998-07-28 Mitel Semiconductor Limited Bare die testing
US5594273A (en) 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
US5544804A (en) 1994-06-08 1996-08-13 Texas Instruments Incorporated Capillary designs and process for fine pitch ball bonding
US5891745A (en) 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design
US5693565A (en) 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
JP3549714B2 (ja) * 1997-09-11 2004-08-04 沖電気工業株式会社 半導体装置
US6143668A (en) 1997-09-30 2000-11-07 Intel Corporation KLXX technology with integrated passivation process, probe geometry and probing process
US6166556A (en) 1998-05-28 2000-12-26 Motorola, Inc. Method for testing a semiconductor device and semiconductor device tested thereby
US6180964B1 (en) 1998-12-03 2001-01-30 Taiwan Semiconductor Manufacturing Co., Ltd Low leakage wire bond pad structure for integrated circuits
US6348742B1 (en) * 1999-01-25 2002-02-19 Clear Logic, Inc. Sacrificial bond pads for laser configured integrated circuits
US6181016B1 (en) 1999-06-08 2001-01-30 Winbond Electronics Corp Bond-pad with a single anchoring structure
US6359342B1 (en) * 2000-12-05 2002-03-19 Siliconware Precision Industries Co., Ltd. Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same

Also Published As

Publication number Publication date
US6563226B2 (en) 2003-05-13
US20020175411A1 (en) 2002-11-28
TW543117B (en) 2003-07-21

Similar Documents

Publication Publication Date Title
US6713881B2 (en) Semiconductor device and method of manufacturing same
US20060231959A1 (en) Bonding pad for a packaged integrated circuit
US6765228B2 (en) Bonding pad with separate bonding and probing areas
US5834338A (en) Chip carrier semiconductor device assembly and a method for forming the same
US5328079A (en) Method of and arrangement for bond wire connecting together certain integrated circuit components
US7391114B2 (en) Electrode pad section for external connection
US6590274B2 (en) Semiconductor wafer and method for manufacturing semiconductor devices
EP0577333B1 (en) Temporary connections for fast electrical access to electronic devices
US6921979B2 (en) Semiconductor device having a bond pad and method therefor
JP2825085B2 (ja) 半導体装置の実装構造、実装用基板および実装状態の検査方法
US6242813B1 (en) Deep-submicron integrated circuit package for improving bondability
US8637975B1 (en) Semiconductor device having lead wires connecting bonding pads formed on opposite sides of a core region forming a shield area
US6674156B1 (en) Multiple row fine pitch leadless leadframe package with use of half-etch process
CN1387258A (zh) 键合区
JP2005322921A (ja) バンプテストのためのフリップチップ半導体パッケージ及びその製造方法
US6756305B1 (en) Stacked dice bonded with aluminum posts
US6359342B1 (en) Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same
CN1921098A (zh) 一种封装结构的半导体晶粒
US5463255A (en) Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion
US5408127A (en) Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components
US7432588B2 (en) Semiconductor device and method of fabricating the same
TWI363392B (en) Method of bumping die pads for wafer testing
US20020070450A1 (en) Bond pad structure for integrated circuits
JPS62261139A (ja) 半導体装置
US6212077B1 (en) Built-in inspection template for a printed circuit

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: FREESCALE SEMICONDUCTOR INC.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20040903

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20040903

Address after: texas

Applicant after: Fisical Semiconductor Inc.

Address before: Illinois

Applicant before: Motorola Inc.

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication