CN1378251A - Intra-metal dielectric layer structure and its forming method - Google Patents
Intra-metal dielectric layer structure and its forming method Download PDFInfo
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- CN1378251A CN1378251A CN 01112321 CN01112321A CN1378251A CN 1378251 A CN1378251 A CN 1378251A CN 01112321 CN01112321 CN 01112321 CN 01112321 A CN01112321 A CN 01112321A CN 1378251 A CN1378251 A CN 1378251A
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Abstract
The present invention relates to a kind of intrametal dielectric layer structure and its forming process and relates to integrated circuit with two metal layers. The forming process includes: forming the first silicon oxide layer on the first metal layer; forming one painted glass layer on the first silicon oxide layer; forming etching stopping layer on the painted glass layer; forming the second silicon oxide layer on the etching stopping layer as the intrametal dielectric layer between the first metal layer and the second metal layer. During the subsequent wet etching of forming the conducting holes, the etching stopping layer has lower etching performance relative to the silicon oxide layer on the painted glass layer, and this results in well conducting hole contour.
Description
The present invention relates to a kind of intra-metal dielectric layer structure and forming method thereof, refer to be applied to intra-metal dielectric layer structure in the integrated circuit of tool multi-metal layer structure and forming method thereof especially.
Amassing into after degree and the complexity increase gradually of semiconductor subassembly, originally individual layer just is enough to bear the metal level of the connection of inter-modules such as transistor on it, resistance, electric capacity, can't satisfy the demands now, and the lead that must utilize the structure of multi-metal layer just can finish whole integrated circuit connects.
And in the manufacturing process of multi-metal layer, being positioned at two metal interlevels is tool one inner metal dielectric layers (Inter-Metal-Dielectrics Layer) in order to insulation, and this inner metal dielectric layer often uses the structure of a kind of sandwich style (Sandwich Type) to finish and reach simultaneously the effect of local planarization, in order to the carrying out of the upper metal layers of made next, and will be comparatively accurate also through the wire pattern that lithography shifted.
See also shown in Figure 1, below the first metal layer 11 and above 15 of second metal levels be to grow up in regular turn first silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) 12 is arranged, spin-on glasses (Spin On Glass, SOG) layer 13, and second silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) equally 14 is formed the inner metal dielectric layer of sandwiched type structure, wherein finish spin-on glasses layer (Spin On Glass, SOG) layer 13 flattening method has not etching method (NEB) and etching method (PEB) etc. partly, this not with give unnecessary details.
See also Fig. 2 again, it is depicted as in multi-metal layer structure the metal plug via that (plug) passes through (via through hole) schematic diagram is provided, wherein open-work structure 21 is to penetrate this second silica (PE-Oxide) layer 14, spin-on glasses (Spin On Glass, SOG) layer 13 and first silica (PE-Oxide) layer 12 and arrive ground floor metal level 11, it is in order to the formation of metal plug (plug) to be provided, and the method that etches this open-work structure 21 is generally the mode that wet etching adds dry ecthing, so that can form sloped sidewall outline component 211 and vertical sidewall part 212 individually, and then can provide this metal plug growth required preferred profile (profile), especially relatively poor because of ladder covering (step coverage) ability of aluminium connector, so need to finish sloped sidewall outline component 211, connect the reliability of finishing to guarantee connector with wet etch step.
But owing to form the wet etching processing procedure of sloped sidewall outline component 211, generally be that the length of adjusting etching period is carried out the control of its etched thickness, and the inner metal dielectric layer of above-mentioned sandwiched type structure will be starched the wet etching ratio of enhanced chemical vapor deposition silica that method is finished (PE-Oxide) and spin-on glasses (SOG) greater than 1: 10 with electricity because of having (a), and (b) may have the problems such as defective of hole (pin hole) with electricity slurry enhanced chemical vapor deposition silica that method is finished (PE-Oxide) layer, so that second silicon oxide layer, 14 quilts very easily take place along the hole eating thrown, and make that lower floor's spin-on glasses (SOG) is emptied, and then cause second silicon oxide layer, 14 peeling off phenomenon.
In addition, when people shown in Figure 3 after chip edge provides that the street district of cutting is textural and utilizes photoresistance 38 to define etched pattern, and desire to add that with wet etching the mode of dry ecthing is at first silica (PE-Oxide) layer 35, spin-on glasses (Spin On Glass, when SOG) carrying out etching on layer 36 and second silica (PE-Oxide) layer 37, wherein because the field oxide 31 of the about 4k* of thickness that is grown up on the chip 30, behind the ground floor metal level 33 of the core dielectric material of the about 6k* of thickness (Inter Layer Dielectric) layer 32 and the about 7k* of thickness, with respect to street district 34 existing sizable ground potential differences, and because (c) may be less than 60% (a among Fig. 3 be than last b) with ladder covering (step coverage) rate of electricity slurry enhanced chemical vapor deposition silica that method is finished (PE-Oxide), so that is therebetween grown up starches first silica (PE-Oxide) layer 35 that enhanced chemical vapor deposition method (PECVD) is finished with electricity, spin-on glasses (Spin On Glass, SOG) layer 36, and the shape of second silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) equally 37 will be as shown in the figure not satisfactory, and because (d) stress concentration effect at metal pattern edge (metal pattern edge stress concentration) will be strengthened wet etching may take place for the etching speed of metal level edge problems such as (arrow shown in Figure 3 are expressed the tissue fragility of this metal level because of this edge that inwardly contraction causes that descends through temperature with slight crack system), so in actual processing procedure, must shorten etching period, to stay silicon oxide layer that thickness is at least about 3k* as shown in Figure 2 safety zone (safety margin) 22, and then can avoid because of above-mentioned (a) (b) (c) (d) when situation takes place, institute causes second silicon oxide layer 14 that lower floor's spin-on glasses (SOG) is emptied and makes 14 generations of second silicon oxide layer peel off phenomenon, but so the practice will cause following two problems of conflicting mutually and being difficult to accept or reject: (1) need reserve safety zone (asfety margin) because of teacher of the carrying out's etching, so will cause the shape of sloped sidewall outline component 211 comparatively not good, influence the growth of follow-up metal plug.(2) if when second silica (PE-Oxide) of growing up thicker layer 14 makes the shape of sloped sidewall outline component 211 comparatively good, with the shortcoming that causes integral thickness to increase simultaneously and physical features is increased.
And how to solve the shortcoming of above-mentioned prior art means, and provide actual techniques means to reach, for developing main purpose of the present invention.
The present invention is a kind of intra-metal dielectric layer structure, it is applied in the integrated circuit of tool multi-metal layer structure, this integrated circuit has the first metal layer and second metal level, and this intra-metal dielectric layer structure comprises: first silicon oxide layer is positioned on this first metal layer; The spin-on glasses layer is positioned on this first silicon oxide layer; Etch stop layer is positioned on this spin-on glasses layer; And second silicon oxide layer, be positioned on this etch stop layer with this second metal level under, the wet etching that in follow-up via (via through hole) manufacturing process, carried out of this etch stop layer wherein, have the characteristic of low etching ratio with respect to these silicon oxide layers and this spin-on glasses layer, and can get a preferable via profile.
According to above-mentioned conception, this first silicon oxide layer and this second silicon oxide layer are finished by electricity slurry enhanced chemical vapor deposition method in the intra-metal dielectric layer structure.
According to above-mentioned conception, this etch stop layer is finished by the material that is selected from boron nitride, carborundum, the amorphous silicon in the intra-metal dielectric layer structure.
According to above-mentioned conception, this wet etching that is carried out for this via of formation (via through hole) in the intra-metal dielectric layer structure is utilization one buffer oxide etch liquid (Buffer Oxide Etcher, BOE) chemical wet of being carried out (Chemical Wet Etch).
According to above-mentioned conception, this etch stop layer is finished by the silicon nitride that is about 200 dust to 1000 dusts with electricity slurry enhanced chemical vapor deposition method institute deposit thickness in the intra-metal dielectric layer structure.
According to above-mentioned conception, the etch stop layer that should finish by silicon nitride in the intra-metal dielectric layer structure and this second silicon oxide layer be with same reative cell in starch the enhanced chemical vapor deposition method with electricity and formed.
Another aspect of the invention is a kind of inner metal dielectric layer formation method, it is applied to have in the integrated circuit of multi-metal layer structure, this integrated circuit has the first metal layer and second metal level, and this method comprises the following step: form first silicon oxide layer on this first metal layer; On this first silicon oxide layer, form the spin-on glasses layer; On this spin-on glasses layer, form etch stop layer; And on this etch stop layer, form second silicon oxide layer, and then finish this inner metal dielectric layer between this first metal layer and this second metal level, wherein this etch stop layer in follow-up via (via through hole) in these silicon oxide layers and this spin-on glasses layer have a low etched characteristic, and the preferable via profile that can get.
According to above-mentioned conception, this first silicon oxide layer and this second silicon oxide layer are finished by an electricity slurry enhanced chemical vapor deposition method in the inner metal dielectric layer formation method.
According to above-mentioned conception, this etch stop layer is finished by one of being selected from boron nitride, carborundum, the amorphous silicon material in the intra-metal dielectric layer structure.
According to above-mentioned conception, this wet etching that is carried out for this via of formation (via through hole) in the intra-metal dielectric layer structure is utilization one buffer oxide etch liquid (Buffer Oxide Etcher, BOE) chemical wet of being carried out (Chemical Wet Etch).
According to above-mentioned conception, this etch stop layer is finished by the silicon nitride that is about 200 dust to 1000 dusts with electricity slurry enhanced chemical vapor deposition method institute deposit thickness in the intra-metal dielectric layer structure.
According to above-mentioned conception, should in same reative cell, be formed by etch stop layer and this second silicon oxide layer that silicon nitride is finished in the intra-metal dielectric layer structure with electricity slurry enhanced chemical vapor deposition method.
The present invention will get a more deep understanding by following accompanying drawing and detailed description:
Fig. 1 is the inner metal dielectric layer schematic diagram of traditional sandwich style (Sandwich Type) structure.
Fig. 2 is guide hole (the via through hole) generalized section in order to metal plug (plug) deposition growing to be provided in the inner metal dielectric layer of traditional sandwich style (Sandwich Type) structure.
Fig. 3 is in finishing the schematic diagram of inner metal dielectric layer of traditional sandwich style (Sandwich) structure that the street district place of cutting is provided at chip edge.
Fig. 4 is the intra-metal dielectric layer structure schematic diagram that preferred embodiment of the present invention disclosed.
Fig. 5 is via (the via through hole) generalized section in order to metal plug (plug) deposition growing to be provided in the inner metal dielectric layer that discloses in preferred embodiment of the present invention.
Fig. 6 is for finishing the schematic diagram of the inner metal dielectric layer that preferred embodiment of the present invention disclosed that the street district place of cutting is provided at chip edge.
See also Fig. 4, it is for the organigram of preferred embodiment of the present invention, wherein the first metal layer 41 and above 46 of second metal levels grow up in regular turn first silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) 42 arranged, spin-on glasses (Spin On Glass, SOG) layer 43, etch stop layer 44 and second silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) equally 45 are formed disclosed new intra-metal dielectric layer structure, wherein this etch stop layer 44 is by silicon nitride, boron nitride, carborundum, materials such as amorphous silicon are finished, main because above-mentioned material is difficult for being formed the wet etching that this via (via through hole) carried out and corrodes, and is emptied and causes second silicon oxide layer, 45 peeling off phenomenon so can avoid ought second silicon oxide layer 45 being produced along the hole eating thrown spin-on glasses layer 43.
For example, when etch stop layer is by the silicon nitride (SiNx that is about 200 dust to 1000 dusts with electricity slurry enhanced chemical vapor deposition method institute deposit thickness, 0.8 when＜x＜1.2) finishing, because at utilization buffer oxide etch liquid (Buffer Oxide Etcher, BOE) under the chemical wet of being carried out (Chemical Wet Etch), silicon nitride, the rate of etch of silica and spin-on glasses layer is about 1: 10: 100 (still deciding on film deposition conditions), thereby can successfully avoid the spin-on glasses layer 43 may be by the phenomenon of emptying and causing second silicon oxide layer 45 to be peeled off, and etch stop layer 44 and this second silicon oxide layer 45 that silicon nitride is finished can be in same reative cells, be lower than the following electricity slurry enhanced chemical vapor deposition method of 500 degree Celsius with depositing temperature and formed, do not increase its process complexity.
See also Fig. 5 again, it is depicted as in the multi-metal layer structure that discloses in preferred embodiment of the present invention has via (the via through hole) schematic diagram that metal plug (plug) passes through, wherein open-work structure 51 is to penetrate this second silica (PE-Oxide) layer 45, etch stop layer 44, spin-on glasses (Spin OnGlass, SOG) layer 43 and first silica (PE-Oxide) layer 42 and arrive ground floor metal level 41, and because the possibility that the function of etch stop layer 44 can effectively avoid spin-on glasses layer 43 to be emptied, so in actual processing procedure, just need not shorten etching period, and stay the excessive safety zone of thickness (safety margin) 52, therefore under the situation of second silica (PE-Oxide) layer 45 that needn't grow up thicker, just can obtain the good sloped sidewall outline component 511 of shape.
In addition, when people shown in Figure 6 after chip edge provides that the street district of cutting is textural and utilizes photoresistance 69 to define etched pattern, and desire to add that with wet etching the mode of dry ecthing is in first silica (PE-Oxide) layer 65, spin-on glasses (Spin On Glass, SOG) layer 66, when carrying out etching on etch stop layer 67 and second silica (PE-Oxide) layer 68, even the field oxide 61 of the about 4k dust of thickness of being grown up on the chip 60, behind the ground floor metal level 63 of the core dielectric material of the about 6k dust of thickness (Inter Layer Dielectric) layer 62 and the about 7k dust of thickness, with respect to street district 64 existing sizable ground potential differences.
And because may be less than 60% (a among Fig. 6 be than last b) with ladder covering (step coverage) rate of electricity slurry enhanced chemical vapor deposition silica that method is finished (PE-Oxide), first silica (PE-Oxide) layer of being finished with electricity slurry enhanced chemical vapor deposition method (PECVD) 65 that results in therebetween to be grown up, spin-on glasses (Spin On Glass, SOG) layer 66, the shape of etch stop layer 67 and second silica (PE-Oxide) layer 68 is not satisfactory, even because (d) stress concentration effect at metal pattern edge (metalpattern edge stress concentration) will strengthen wet etching for the etching speed of the first metal layer 63 edges (arrow shown in the figure and slight crack system express this first metal layer 63 inwardly shrink because of descending through temperature cause the tissue fragility of this edge) etc. problem may cause spin-on glasses layer 43 quilt to be emptied situation, all can effectively avoid, reach development main purpose of the present invention really because of the effect of etch stop layer 44.
The present invention can carry out many variations by those skilled in the art person, but these variations are included in the appended claim scope.
Claims (12)
1. metal and dielectric structure in a kind, it is applied to have in the integrated circuit of multi-metal layer structure, and this integrated circuit has the first metal layer and second metal level, and this intra-metal dielectric layer structure comprises:
First silicon oxide layer is positioned on this first metal layer;
The spin-on glasses layer is positioned on this first silicon oxide layer;
Etch stop layer is positioned on this spin-on glasses layer; And
Second silicon oxide layer, be positioned on this etch stop layer with this second metal level under, the wet etching that in follow-up via manufacturing process, carried out of this etch stop layer wherein, have the characteristic of low etching ratio with respect to these silicon oxide layers and this spin-on glasses layer, and can get preferable via profile.
2. intra-metal dielectric layer structure as claimed in claim 1 is characterized in that, this first silicon oxide layer and this second silicon oxide layer are finished by electricity slurry enhanced chemical vapor deposition method.
3. intra-metal dielectric layer structure as claimed in claim 1 is characterized in that, this etch stop layer is finished by the material in boron nitride, carborundum, the amorphous silicon.
4. intra-metal dielectric layer structure as claimed in claim 1 is characterized in that, for forming the chemical wet of this wet etching for using buffer oxide etch liquid to be carried out that this via carries out.
5. intra-metal dielectric layer structure as claimed in claim 1 is characterized in that, this etch stop layer is finished by the silicon nitride that is about 200 dust to 1000 dusts with electricity slurry enhanced chemical vapor deposition method institute deposit thickness.
6. intra-metal dielectric layer structure as claimed in claim 1 is characterized in that, should be formed with electricity slurry enhanced chemical vapor deposition method in same reative cell by etch stop layer and this second silicon oxide layer that silicon nitride is finished.
7. inner metal dielectric layer formation method, it is applied in the integrated circuit of tool multi-metal layer structure, and this integrated circuit has the first metal layer and second metal level, and described method comprises the following step:
On this first metal layer, form first silicon oxide layer;
On this first silicon oxide layer, form the spin-on glasses layer;
On this spin-on glasses layer, form etch stop layer; And
On this etch stop layer, form second silicon oxide layer, and then finish this inner metal dielectric layer between this first metal layer and this second metal level, wherein, the wet etching that this etch stop layer is carried out in follow-up via manufacturing process, have the characteristic of low etching ratio with respect to these silicon oxide layers and this spin-on glasses layer, and can get preferable via profile.
8. inner metal dielectric layer formation method as claimed in claim 7 is characterized in that, this first silicon oxide layer and this second silicon oxide layer are finished by electricity slurry enhanced chemical vapor deposition method.
9. inner metal dielectric layer formation method as claimed in claim 7 is characterized in that, this etch stop layer is finished by the material that is selected from boron nitride, carborundum, the amorphous silicon.
10. inner metal dielectric layer formation method as claimed in claim 7 is characterized in that, is chemical wet for using a buffer oxide etch liquid to be carried out for forming this wet etching that this via carries out.
11. inner metal dielectric layer formation method as claimed in claim 7 is characterized in that, this etch stop layer is finished by the silicon nitride that is about 200 dust to 1000 dusts with electricity slurry enhanced chemical vapor deposition method institute deposit thickness.
12. inner metal dielectric layer formation method as claimed in claim 11 is characterized in that, should be formed with electricity slurry enhanced chemical vapor deposition method in same reative cell by etch stop layer and this second silicon oxide layer that silicon nitride is finished.
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| CN 01112321 CN1201377C (en) | 2001-03-29 | 2001-03-29 | Intra-metal dielectric layer structure and its forming method |
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| CN 01112321 CN1201377C (en) | 2001-03-29 | 2001-03-29 | Intra-metal dielectric layer structure and its forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324678C (en) * | 2003-11-12 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Internal dielectric layer of semiconductor, semiconductor assembly and mfg.method thereof |
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| CN110085737A (en) * | 2018-01-26 | 2019-08-02 | 联华电子股份有限公司 | Magnetic random access memory and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024748B (en) * | 2009-09-15 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing critical dimension of contact hole |
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2001
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| CN1324678C (en) * | 2003-11-12 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Internal dielectric layer of semiconductor, semiconductor assembly and mfg.method thereof |
| CN110085737A (en) * | 2018-01-26 | 2019-08-02 | 联华电子股份有限公司 | Magnetic random access memory and preparation method thereof |
| US11944016B2 (en) | 2018-01-26 | 2024-03-26 | United Microelectronics Corp. | Magnetoresistive random access memory and method of manufacturing the same |
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| CN1201377C (en) | 2005-05-11 |
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Granted publication date: 20050511 |