CN1359149A - Packaged IC substrate and making method - Google Patents
Packaged IC substrate and making method Download PDFInfo
- Publication number
- CN1359149A CN1359149A CN00134541A CN00134541A CN1359149A CN 1359149 A CN1359149 A CN 1359149A CN 00134541 A CN00134541 A CN 00134541A CN 00134541 A CN00134541 A CN 00134541A CN 1359149 A CN1359149 A CN 1359149A
- Authority
- CN
- China
- Prior art keywords
- substrate
- packaged
- sheet metal
- sheet
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a packaged integrated circuit base board and its production method for raising integrated circuit signal transer quality. It is characterized by that said base board is formed from sheetmetals which are mutually and smoothly arranged and packaging colloidal matter for covering most of sheetmetals. Every sheetmetal possesses first surface which is exposed from the packaging colloidal matter and electrically connected with input end of integrated circuit and second surface which is exposed from the packaging colloidal matter and electrically connected with output end of circuit board. Its production method includes the following steps: placing the sheetmetal with first surface and second surface into mould, injection pakcaging colloidal matter into the mould to form base board and taking out said base board.
Description
The invention belongs to encapsulated integrated circuit parts and manufacture method thereof, particularly a kind of packaged IC substrate and manufacture method thereof.
The substrate system of general encapsulated integrated circuit makes integrated circuit form in the routing mode with this substrate and is electrically connected in order to the integrated circuit setting thereon, then substrate is fixed on the circuit board again, and the signal of integrated circuit is passed on the circuit board.
Must have signal input end and signal output end on this substrate, with form when substrate and integrated circuit be electrically connected after, make the signal of integrated circuit be passed to the signal input end of substrate, the signal output end by substrate is sent on the circuit board again.So, the signal input end of substrate is short more to the distance of signal output end, and then the effect of signal transmission is then good more; Otherwise if the substrate signal input end is long more to the distance of output, then the effect of signal transmission is then poor more.
Be provided with on the known packaged IC substrate and be the metallic plate of horizontal Jiong (Contraband) shape as the input of substrate signal, output, integrated circuit then is electrically connected with the end of metallic plate as signal input end, and metallic plate then is electrically connected with circuit board as an end of signal output end.The distance that this structure substrate signal transmits is quite long, so that influences the quality that the integrated circuit signal transmits.
Moreover, when this horizontal Jiong (Contraband) shape metallic plate is made, be difficult to obtain smooth signal output end, it is electrically connected with circuit board when doing the signal transmission, the effect that signal transmits is unsatisfactory, so that has influence on the qualification rate and the reliability thereof of integrated circuit encapsulation.
The purpose of this invention is to provide a kind of easy to make, product qualified rate is high, improve packaged IC substrate and manufacture method thereof that the integrated circuit signal transmits quality.
Substrate of the present invention is made of most smooth sheet metals of arranging mutually and the adhesive body that coats most sheet metals; Sheet metal has the formation of exposing plastic body and is electrically connected the first surface of input and formation is electrically connected output with circuit board second surface with integrated circuit.
Manufacture of substrates of the present invention comprises the steps:
Step 1
Row are established sheet metal
Having first and second surperficial sheet metal with most arranges mutually and is located at mould;
Step 2
With the die forming substrate
Adhesive body is poured in the mould, coats the adhesive body of most sheet metals with formation, and make each sheet metal first surface and second surface expose adhesive body, form substrate signal input end and output;
Step 3
Take out substrate
Substrate is taken out in mould.
Wherein:
Sheet metal is smooth sheet metal.
The first surface of sheet metal is electrically connected with integrated circuit in the routing mode on the substrate.
Substrate metal sheet second surface is provided with the Metal Ball that becomes to be electrically connected with circuit board.
Metal Ball is the Metal Ball in the ball grid array mode.
Adhesive body is by plastic cement material.
Also most sheet metals can be arranged glutinous being located on the adhesive tape mutually, and the hollow out mould is arranged on the adhesive tape (tape), and make most sheet metals be positioned at the hollow out mould.
Earlier adhesive tape is removed from mold bottom before taking out substrate.
Adhesive body is by plastic cement material.
The sheet metal second surface is provided with Metal Ball.
The Metal Ball that is arranged at the sheet metal second surface is made in the ball grid array mode.
Because substrate of the present invention is made of most smooth sheet metals of arranging mutually and the adhesive body that coats most sheet metals; Sheet metal has the formation of exposing plastic body and is electrically connected the first surface of input and formation is electrically connected output with circuit board second surface with integrated circuit; Its manufacture method is included in the interior row of mould and establishes first and second surperficial sheet metal of tool, adhesive body is poured into mould internal shaping substrate and takes out substrate.During use, the signal that makes substrate by foil transmits media, when the signal with integrated circuit is passed to circuit board, can obtain short transmission distance, having preferable signal transmission effect, and make the second surface of sheet metal form preferable electro-contact effect with circuit board.Not only easy to make, product qualified rate is high, and improve the integrated circuit signal and transmit quality, thereby reach purpose of the present invention.
Fig. 1, for board structure schematic isometric of the present invention.
Fig. 2, be encapsulated integrated circuit structural representation cutaway view with substrate package of the present invention.
Fig. 3, for manufacture of substrates step 1 schematic sectional view of the present invention.
Fig. 4, for manufacture of substrates step 2 schematic sectional view of the present invention.
Below in conjunction with accompanying drawing the present invention is further elaborated.
As shown in Figure 1, substrate 10 of the present invention is by most the smooth sheet metals of arranging mutually 12 and coat constituting for the adhesive body 26 of plastic cement material of most sheet metals 12.Each sheet metal 12 has first surface 14 that exposes plastic body 26 formation signal input ends and the second surface 16 that forms signal output end.
As shown in Figure 2, substrate 10 of the present invention is used to encapsulate comprises stacked in regular turn circuit board 24, integrated circuit 18 and during in order to adhesive layer 40 that integrated circuit 18 is sealed up, form with the weld pad 20 of integrated circuit 18 with the lead 22 of routing mode with the first surface 14 of sheet metal 12 on the substrate 10 of the present invention and to be electrically connected, the second surface 16 of sheet metal 12 forms with circuit board 24 and is electrically connected on the substrate 10, so the signal of integrated circuit 18 is passed on the circuit board 24 by most sheet metals 12 on the substrate 10, to finish the electric connection of integrated circuit 18 and circuit board 24.
Manufacture of substrates of the present invention comprises the steps:
Step 1
Row are established sheet metal
As shown in Figure 3, at first most sheet metal 12 mutual arrangements the with first surface 14, second surface 16 are attached on the adhesive tape (tape) 28, and mould 30 is arranged on the adhesive tape (tape) 28, and make most sheet metals 12 be positioned at hollow out mould 30.
Step 2
With the die forming substrate
As shown in Figure 4, plastic cement material is poured in the mould 30, coats the adhesive body 26 of most sheet metals 12 with formation, and make each sheet metal 12 first surface 14 expose adhesive body 26, form substrate 10 and form the signal input end that is electrically connected with integrated circuit 18 weld pads 20.
Step 3
Take out substrate
As mentioned above, substrate of the present invention and manufacture method thereof have following advantage:
1, makes the signal transmission media of substrate 10 by foil 12, when the signal with integrated circuit 18 is passed to circuit board 24, can obtains short transmission distance, thereby have preferable signal transmission effect.
2, sheet metal 12 has smooth second surface 16, can form preferable electro-contact effect with circuit board 24.
Claims (12)
1, a kind of packaged IC substrate is characterized in that it is made of most smooth sheet metals of arranging mutually and the adhesive body that coats most sheet metals; Sheet metal has the formation of exposing plastic body and is electrically connected the first surface of input and formation is electrically connected output with circuit board second surface with integrated circuit.
2, encapsulated integrated circuit according to claim 1 is characterized in that described sheet metal is smooth sheet metal.
3, packaged IC substrate according to claim 1 is characterized in that the first surface of sheet metal on the described substrate is electrically connected with integrated circuit in the routing mode.
4, packaged IC substrate according to claim 1 is characterized in that described substrate metal sheet second surface is provided with the Metal Ball that becomes to be electrically connected with circuit board.
5, packaged IC substrate according to claim 4 is characterized in that described Metal Ball is the Metal Ball in the ball grid array mode.
6, packaged IC substrate according to claim 1 is characterized in that described adhesive body is by plastic cement material.
7, a kind of packaged IC substrate manufacture method is characterized in that it comprises the steps:
Step 1
Row are established sheet metal
Having first and second surperficial sheet metal with most arranges mutually and is located at mould;
Step 2
With the die forming substrate
Adhesive body is poured in the mould, coats the adhesive body of most sheet metals with formation, and make each sheet metal first surface and second surface expose adhesive body, form substrate signal input end and output;
Step 3
Take out substrate
Substrate is taken out in mould.
8, packaged IC substrate manufacture method according to claim 7, it is characterized in that described step 1 also can arrange glutinous being located on the adhesive tape mutually with most sheet metals, and the hollow out mould is arranged on the adhesive tape (tape), and make most sheet metals be positioned at the hollow out mould.
9,, it is characterized in that described step 3 removes adhesive tape earlier before taking out substrate from mold bottom according to claim 7 or 8 described packaged IC substrate manufacture methods.
10 packaged IC substrate manufacture methods according to claim 7 is characterized in that described adhesive body is by plastic cement material.
11, packaged IC substrate manufacture method according to claim 7 is characterized in that described sheet metal second surface is provided with Metal Ball.
12, packaged IC substrate manufacture method according to claim 11 is characterized in that the described Metal Ball that is arranged at the sheet metal second surface makes in the ball grid array mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001345419A CN1152427C (en) | 2000-12-11 | 2000-12-11 | Packaged IC substrate and making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001345419A CN1152427C (en) | 2000-12-11 | 2000-12-11 | Packaged IC substrate and making method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1359149A true CN1359149A (en) | 2002-07-17 |
| CN1152427C CN1152427C (en) | 2004-06-02 |
Family
ID=4596264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001345419A Expired - Fee Related CN1152427C (en) | 2000-12-11 | 2000-12-11 | Packaged IC substrate and making method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1152427C (en) |
-
2000
- 2000-12-11 CN CNB001345419A patent/CN1152427C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1152427C (en) | 2004-06-02 |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |