CN1355561A - Technology for manufacturing flat display with film transistors - Google Patents
Technology for manufacturing flat display with film transistors Download PDFInfo
- Publication number
- CN1355561A CN1355561A CN 00128493 CN00128493A CN1355561A CN 1355561 A CN1355561 A CN 1355561A CN 00128493 CN00128493 CN 00128493 CN 00128493 A CN00128493 A CN 00128493A CN 1355561 A CN1355561 A CN 1355561A
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- layer
- metal level
- connection gasket
- transistor
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
- C03C17/06—Surface treatment of glass, not in the form of fibres or filaments, by coating with metals
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C2218/00—Methods for coating glass
- C03C2218/30—Aspects of methods for coating glass not covered above
- C03C2218/32—After-treatment
- C03C2218/328—Partly or completely removing a coating
- C03C2218/33—Partly or completely removing a coating by etching
Abstract
A technology for preparing flat display with thin-film transistors includes such steps as generating the first metal layer on glass substrate, yellow light etching to generate grid and pad electrodes, sequentially generating insulating layer, semiconductor layer and doped conducting silicon layer, second yellow light etching to limit active areas and connection windows, generating transparent conducting layer and the second metal layer, third yellow light etching to form sources and drains, generating protection layer, fourth yellow light etching and oxidizing reaction.
Description
The present invention relates to a kind of manufacture method of film transistor plane indicator, particularly relate to four yellow-light etching process of a kind of use (photo-etching-process, the manufacture method of Thin Film Transistor-LCD PEP).
Thin Film Transistor-LCD ((Thin Film Transistor Liquid Crystal Display, hereinafter to be referred as TFT-LCD) mainly be the thin-film transistor that utilizes into rectangular arrangement, cooperate electronic components such as suitable electric capacity, connection gasket to drive liquid crystal pixel, enrich beautiful figure with generation.The electronic component of TFT-LCD has consisted essentially of a transparency carrier (transparent substrate), has scan line (scan line) and holding wire (signal line), a filter (color filter) and the liquid crystal material between transparency carrier and filter of thin-film transistor that an array formula arranges, pixel electrode (pixel electrode), orthogonal staggered (orthogonal) on it.
Please refer to Fig. 1 to Fig. 5, Fig. 1 to Fig. 5 is the existing method schematic diagram of making a TFT-LCD electronic component.As shown in Figure 1, existing TFT-LCD is produced on the transparency carrier 10, and transparency carrier 10 is one by high purifying silicon dioxide (high-purified SiO
2) transparent glass substrate that constituted, be provided with a transistor (transistor) district A and a connection gasket (pad) district B on its surface at least, to be used for forming transistor 20 and connection gasket 30 respectively.
Existing method forms a first metal layer 11 prior to transparency carrier 10 surfaces, and carry out one first yellow-light etching process (PEP), form a gate electrode 12 with transparency carrier 10 surfaces, and form a pad electrode 14 on transparency carrier 10 surfaces of connection gasket district B respectively at transistor area A.
As shown in Figure 2, then carry out a chemical vapour deposition (CVD) manufacture craft (chemical vapordeposition process, CVD), the insulating barrier (isolation layer) 16 that forms by silicon nitride (siliconnitride) at transparency carrier 10 surperficial uniform depositions one, thickness is about 4000 dusts (angstrom), and form one in regular turn by amorphous silicon (amorphous silicon, a-Si) semiconductor layer 18 of Gou Chenging and doped silicon (doped silicon) conductive layer 22 on insulating barrier 16 surfaces.
As shown in Figure 3, carry out one second yellow-light etching process, in transistor area A, form the pattern of doped silicon conductive layer 22 and semiconductor layer 18, to limit an active area 23.In connection gasket district B, carry out one the 3rd yellow-light etching process then, remove pad electrode 14 tops doped silicon conductive layer 22, semiconductor layer 18, with insulating barrier 16, to form the opening 24 of connection gasket district B, pad electrode 14 is exposed in the opening 24.
As shown in Figure 4, carry out another CVD manufacture craft to deposit a transparency conducting layer 25 and one second metal level 26 in transparency carrier 10 surfaces in regular turn comprehensively.(indiumtin oxide ITO) forms, as pixel electrode (pixel electrode) transparency conducting layer 25 by tin indium oxide.Then carry out one the 4th yellow-light etching process, to form the passage 27 on sensible semiconductor layer 18 surfaces to gate electrode 12 tops in transistor area A.Passage 27 is separated into two districts with second metal level 26, transparency conducting layer 25 with doped silicon conductive layer 22, to form an one source pole 26a and a drain electrode 26b respectively.
As shown in Figure 5, in transistor 20 and connection gasket 30 surperficial uniform deposition one protective layers (passivation layer) 28, protective layer 28 can be inserted in the passage 27 at last.Then, carry out one the 5th yellow-light etching process, remove the substrate 10 top protective layers 28 and second metal level 26, transistor area A transparency conducting layer 25 is in addition come out, and finish the making of electronic component in the Thin Film Transistor-LCD.
Existing method uses five road yellow-light etching process to limit grid and the pattern that fills up electrode, active area, connection gasket district opening, source electrode and drain electrode and pixel electrode in regular turn respectively, the manufacturing process of whole Thin Film Transistor-LCD is still quite tediously long and complicated, and the image quality of display is not very good yet, remains further to be improved.
The object of the present invention is to provide a kind of Thin Film Transistor-LCD manufacture craft of simplifying, and can improve the manufacture method of display image quality.
The object of the present invention is achieved like this, a kind of manufacture method of film transistor plane indicator promptly is provided, this display is produced on the substrate (substrate), this substrate includes at least one transistor (transistor) district and at least one connection gasket (pad) district, be used for forming a transistor and a connection gasket respectively, this manufacture method includes the following step: (1) forms a first metal layer on this substrate surface; (2) (photo-etching-process PEP) limits the pattern (pattern) of this first metal layer, to form a gate electrode and a pad electrode respectively in this transistor area and this connection gasket district to carry out one first yellow-light etching process; (3) on this substrate, form an insulating barrier, semi-conductor layer and a doped silicon (doped silicon) conductive layer in regular turn; (4) carry out the pattern that one second yellow-light etching process limits this doped silicon conductive layer, this semiconductor layer and this insulating barrier, in this connection gasket district, limit an open area, remove outside (a) this transistor area simultaneously and (b) this connection gasket district outer with this open area in this insulating barrier, this semiconductor layer, and this doped silicon conductive layer, come out with this connection gasket district exposure of substrates in addition beyond so making this transistor area, and form an opening in this connection gasket district, make this pad electrodes exposed in this opening; (5) on this substrate, form a transparency conducting layer and one second metal level in regular turn, and this transparency conducting layer and this second metal level are inserted in this opening; (6) carry out the pattern that one the 3rd yellow-light etching process limits this second metal level, in this transistor area, limit a channel region earlier, remove this second metal level in this channel region, be shade with this second metal level afterwards, remove this transparency conducting layer and this doped silicon conductive layer of this channel region, this semiconductor layer is exposed in this passage; (7) on this substrate, form a protective layer (passivation layer), and make it cover this passage fully; And (8) carry out one the 4th yellow-light etching process; limit the pattern of this protective layer and this second metal level; remove (a) this transistor area outer with (b) this connection gasket district outside reach this protective layer and this second metal level in this opening, so make this transparency conducting layer be exposed in this opening, this transistor area is outer, and this connection gasket district outside the zone.
Carry out a heat treatment (thermal process) step at last, make the protective layer soft heat and cover transistor area and the connection gasket district in the sidewall of second metal level.Utilize a heat treatment to protect second metal level at last, make it be unlikely the pollution liquid crystal, therefore can reach and reduce manufacturing process steps number of times and the purpose of improving image quality.
Below in conjunction with accompanying drawing, describe embodiments of the invention in detail, wherein:
Fig. 1 to Fig. 5 is the manufacture method schematic diagram of the electronic component of existing film transistor plane indicator;
Fig. 6 to Figure 12 is the manufacture method schematic diagram of the electronic component of film transistor plane indicator of the present invention.
Please refer to Fig. 6 to Figure 12, Fig. 6 to Figure 12 is the manufacture method schematic diagram of film transistor plane indicator of the present invention.As shown in Figure 6, film transistor plane indicator is produced on the transparency carrier 40, transparency carrier 40 is a transparent glass substrate that is made of high purifying silicon dioxide, and its surface is provided with a transistor area C and a connection gasket district D at least, to be used for forming transistor 50 and connection gasket 60 respectively.
The present invention forms a first metal layer 41 on transparency carrier 40 surfaces earlier, is generally chromium or titanium.Then carry out one first yellow-light etching process, utilize a photoresist to limit and an etching process, transparency carrier 40 surfaces respectively at transistor area C form a gate electrode 42, and form a pad electrode 44 on transparency carrier 40 surfaces of connection gasket district D.
As shown in Figure 7, then carrying out a film forming manufacture craft, for example is the chemical vapor deposition (CVD) manufacture craft, at whole transparency carrier 40 surperficial uniform deposition one insulating barriers 46, thickness is about 4000 dusts, and forms semi-conductor layer 48 and doped silicon conductive layer 52 in regular turn on insulating barrier 46 surfaces.Semiconductor layer 48 can be made up of amorphous silicon (a-Si) or polysilicon.
As shown in Figure 8, carry out a photoresist and limit second yellow-light etching process that makes up with an etching process, form the pattern of doped silicon conductive layer 52, semiconductor layer 48 and insulating barrier 46, to form an active area 53 and in connection gasket district D, to form an opening 54 at transistor area C simultaneously.In this step, on connection gasket district D, limit an open area earlier, remove outside (a) transistor area C simultaneously and (b) connection gasket district D outer with the open area in insulating barrier 46, semiconductor layer 48, and doped silicon conductive layer 52, come out with this connection gasket district D exposure of substrates in addition beyond so making transistor area C, and, pad electrode 44 is exposed in the opening 54 in connection gasket district D formation opening 54.
As shown in Figure 9, carry out a film forming manufacture craft and deposit a transparency conducting layer 56 and one second metal level 58 in transparency carrier 40 surfaces in regular turn.Transparency conducting layer 56 is made up of tin indium oxide (ITO) usually, as pixel electrode.Then carry out one the 3rd yellow-light etching process, utilize a photoresist to limit and an etching process,, remove second metal level 58 in the channel region prior to limiting a channel region in the transistor area C in transistor area C.Afterwards, be shade with second metal level 58 again, remove the transparency conducting layer 56 and doped silicon conductive layer 52 of channel region, semiconductor layer 48 is exposed in the passage 62.Passage 62 is separated into two districts with metal level 58, transparency conducting layer 56 and doped silicon conductive layer 52, to form an one source pole 58a and a drain electrode 58b respectively.
As shown in figure 10,, and carry out one the 4th yellow-light etching process, utilize a photoresist to limit the pattern that limits the protective layer 64 and second metal level 58 with an etching process at transistor 50 and connection gasket 60 surperficial uniform deposition one protective layers 64.In this step; remove outside (a) transistor area C outer (b) and the connection gasket district D and the protective layer 64 and second metal level 58 in the opening 54; transparency conducting layer 56 is exposed in the opening 54; and the transparency conducting layer 56 that transistor area C is outer and connection gasket district D is outer also comes out, and the protective layer 64 of opening 54 both sides and metal level 58 width of being separated by is about 35mm.
Usually, protective layer 64 is made of silicide, can be silicon nitride or silica.At this moment, after the 4th yellow-light etching process, can carry out a high-temperature oxydation manufacture craft (thermal oxidationprocess).Shown in Fig. 11, carry out an oxidation reaction on the surface of second metal level 58, make second metal level, 58 sidewall surfaces form an oxide layer 65, be used for protecting second metal level 58, make unlikely contact the in metal surface and influence its electrical performance with liquid crystal.
Because the deposit thickness of protective layer 64 only is about 2mm, and the width of opening 54 reaches 35mm, even with protective layer 64 heating and melting, also is unlikely opening 54 is filled up, does not therefore have the problem that increases pad electrode 44 resistance values and produce.
Compare with the manufacture method of existing Thin Film Transistor-LCD, the inventive method can provide one to simplify manufacture craft, the access times of yellow-light etching process is reduced to four times by five times, to reduce production costs.Simultaneously, the present invention utilizes heat treatment or oxidation reaction protection to live metal level, avoids it to pollute liquid crystal, therefore can promote the image quality of display, is very helpful to improving competitiveness of product.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (9)
1. the manufacture method of a film transistor plane indicator, this display is produced on the substrate (substrate), this substrate includes at least one transistor (transistor) district and at least one connection gasket (pad) district, be used for forming a transistor and a connection gasket respectively, this manufacture method includes the following step:
(1) on this substrate surface, forms a first metal layer;
(2) (photo-etching-process PEP) limits the pattern (pattern) of this first metal layer, to form a gate electrode and a pad electrode respectively in this transistor area and this connection gasket district to carry out one first yellow-light etching process;
(3) on this substrate, form an insulating barrier, semi-conductor layer and a doped silicon (dopedsilicon) conductive layer in regular turn;
(4) carry out the pattern that one second yellow-light etching process limits this doped silicon conductive layer, this semiconductor layer and this insulating barrier, in this connection gasket district, limit an open area, remove outside (a) this transistor area simultaneously and (b) this connection gasket district outer with this open area in this insulating barrier, this semiconductor layer, and this doped silicon conductive layer, come out with this connection gasket district exposure of substrates in addition beyond so making this transistor area, and form an opening in this connection gasket district, make this pad electrodes exposed in this opening;
(5) on this substrate, form a transparency conducting layer and one second metal level in regular turn, and this transparency conducting layer and this second metal level are inserted in this opening;
(6) carry out the pattern that one the 3rd yellow-light etching process limits this second metal level, in this transistor area, limit a channel region earlier, remove this second metal level in this channel region, be shade with this second metal level afterwards, remove this transparency conducting layer and this doped silicon conductive layer of this channel region, this semiconductor layer is exposed in this passage;
(7) on this substrate, form a protective layer (passivation layer), and make it cover this passage fully; And
(8) carry out one the 4th yellow-light etching process; limit the pattern of this protective layer and this second metal level; remove (a) this transistor area outer with (b) this connection gasket district outside reach this protective layer and this second metal level in this opening, so make this transparency conducting layer be exposed in this opening, this transistor area is outer, and this connection gasket district outside the zone.
2. the method for claim 1; the sidewall of this second metal level is exposed in this transistor area and this connection gasket district; and this method also comprises a heat treatment step afterwards in this step (8), makes this protective layer soft heat (reflow) also cover the sidewall of second metal level in this transistor area and this connection gasket district fully.
3. method as claimed in claim 2, wherein this protective layer is formed by an organic material.
4. the method for claim 1, wherein after finishing the 4th yellow-light etching process, this method also comprises an oxidation reaction, so that this second metal level sidewall forms an oxide layer, is used for protecting this second metal level.
5. method as claimed in claim 4, wherein this protective layer is formed by an inorganic material.
6. the method for claim 1, wherein this second yellow-light etching process trims the edge of this doped silicon conductive layer, this semiconductor layer and this insulating barrier approximately so that the transparency conducting layer of subsequent deposition some can directly be deposited on this glass substrate.
7. the method for claim 1, when wherein this step (6) limits the pattern of this transparency conducting layer and this doped silicon conductive layer, in this transistor area, form an one source pole electrode and a drain electrode, and this source electrode and this drain electrode by this channel region the interval.
8. the method for claim 1, wherein this substrate also comprises a capacitive region, to be used to form an electric capacity.
9. the method for claim 1, wherein this semiconductor layer is an amorphous silicon layer or polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001284932A CN1174480C (en) | 2000-11-24 | 2000-11-24 | Technology for manufacturing flat display with film transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001284932A CN1174480C (en) | 2000-11-24 | 2000-11-24 | Technology for manufacturing flat display with film transistors |
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| Publication Number | Publication Date |
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| CN1355561A true CN1355561A (en) | 2002-06-26 |
| CN1174480C CN1174480C (en) | 2004-11-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB001284932A Expired - Lifetime CN1174480C (en) | 2000-11-24 | 2000-11-24 | Technology for manufacturing flat display with film transistors |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423284C (en) * | 2003-11-27 | 2008-10-01 | 三星Sdi株式会社 | Flat panel display |
| CN101072470B (en) * | 2006-05-11 | 2010-10-27 | 启萌科技有限公司 | Glass circuit board and its manufacturing method |
| US7863616B2 (en) | 2006-01-12 | 2011-01-04 | Industrial Technology Research Institute | Structure of thin film transistor array |
| CN101072471B (en) * | 2006-05-11 | 2011-01-12 | 启萌科技有限公司 | Glass circuit board and its manufacturing method |
| CN101976650A (en) * | 2010-10-09 | 2011-02-16 | 友达光电股份有限公司 | Thin film transistor and manufacture method thereof |
| CN101572215B (en) * | 2008-04-28 | 2011-04-27 | 财团法人工业技术研究院 | Method for manufacturing patterned metal layer and film transistor |
| CN101335303B (en) * | 2003-07-14 | 2011-05-18 | 株式会社半导体能源研究所 | Light-emitting device |
| US8022405B2 (en) | 2007-07-20 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| CN1871711B (en) * | 2003-10-28 | 2011-12-07 | 株式会社半导体能源研究所 | Display device, method for manufacturing same, and television receiver |
| CN103376607A (en) * | 2012-04-12 | 2013-10-30 | 株式会社日本显示器中部 | Liquid crystal display device and method of manufacturing the same |
| WO2015161523A1 (en) * | 2014-04-23 | 2015-10-29 | 深圳市华星光电技术有限公司 | Preparation methods for thin-film transistor and organic light-emitting diode display |
| WO2018045612A1 (en) * | 2016-09-08 | 2018-03-15 | 武汉华星光电技术有限公司 | Method for manufacturing oxide thin film transistor |
-
2000
- 2000-11-24 CN CNB001284932A patent/CN1174480C/en not_active Expired - Lifetime
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8319219B2 (en) | 2003-07-14 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| US8735896B2 (en) | 2003-07-14 | 2014-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| CN101335303B (en) * | 2003-07-14 | 2011-05-18 | 株式会社半导体能源研究所 | Light-emitting device |
| US8373166B2 (en) | 2003-07-14 | 2013-02-12 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| CN1871711B (en) * | 2003-10-28 | 2011-12-07 | 株式会社半导体能源研究所 | Display device, method for manufacturing same, and television receiver |
| US7656087B2 (en) | 2003-11-27 | 2010-02-02 | Samsung Mobile Display Co., Ltd. | Flat panel display |
| CN100423284C (en) * | 2003-11-27 | 2008-10-01 | 三星Sdi株式会社 | Flat panel display |
| US7936125B2 (en) | 2003-11-27 | 2011-05-03 | Samsung Mobile Display Co., Ltd. | Flat panel display |
| US7863616B2 (en) | 2006-01-12 | 2011-01-04 | Industrial Technology Research Institute | Structure of thin film transistor array |
| CN101072470B (en) * | 2006-05-11 | 2010-10-27 | 启萌科技有限公司 | Glass circuit board and its manufacturing method |
| CN101072471B (en) * | 2006-05-11 | 2011-01-12 | 启萌科技有限公司 | Glass circuit board and its manufacturing method |
| US8680528B2 (en) | 2007-07-20 | 2014-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| US8022405B2 (en) | 2007-07-20 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| CN101572215B (en) * | 2008-04-28 | 2011-04-27 | 财团法人工业技术研究院 | Method for manufacturing patterned metal layer and film transistor |
| CN101976650B (en) * | 2010-10-09 | 2012-06-27 | 友达光电股份有限公司 | Thin film transistor and manufacture method thereof |
| CN101976650A (en) * | 2010-10-09 | 2011-02-16 | 友达光电股份有限公司 | Thin film transistor and manufacture method thereof |
| CN103376607A (en) * | 2012-04-12 | 2013-10-30 | 株式会社日本显示器中部 | Liquid crystal display device and method of manufacturing the same |
| US9329446B2 (en) | 2012-04-12 | 2016-05-03 | Japan Display Inc. | Liquid crystal display device and method of manufacturing the same |
| CN103376607B (en) * | 2012-04-12 | 2016-08-03 | 株式会社日本显示器 | Liquid crystal display and manufacture method thereof |
| WO2015161523A1 (en) * | 2014-04-23 | 2015-10-29 | 深圳市华星光电技术有限公司 | Preparation methods for thin-film transistor and organic light-emitting diode display |
| US9401418B2 (en) | 2014-04-23 | 2016-07-26 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Method of manufacturing thin film transistor and organic light emitting diode display |
| WO2018045612A1 (en) * | 2016-09-08 | 2018-03-15 | 武汉华星光电技术有限公司 | Method for manufacturing oxide thin film transistor |
| US10170631B2 (en) | 2016-09-08 | 2019-01-01 | Wuhan China Star Optoelectronics Technology Co., Ltd | Manufacturing methods of oxide thin film transistors |
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| Publication number | Publication date |
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| CN1174480C (en) | 2004-11-03 |
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