CN101330106B - Thin-film transistor substrate and thin-film transistor for display panel as well as preparation method thereof - Google Patents
Thin-film transistor substrate and thin-film transistor for display panel as well as preparation method thereof Download PDFInfo
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- CN101330106B CN101330106B CN2008101320980A CN200810132098A CN101330106B CN 101330106 B CN101330106 B CN 101330106B CN 2008101320980 A CN2008101320980 A CN 2008101320980A CN 200810132098 A CN200810132098 A CN 200810132098A CN 101330106 B CN101330106 B CN 101330106B
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Abstract
The invention discloses a thin film transistor, which is formed on a transparent base plate. The thin film transistor comprises a patterned semiconductor layer, a grid insulating layer positioned on the patterned semiconductor layer, a grid positioned on the grid insulating layer, and a patterned light absorption layer. The patterned semiconductor layer comprises a channel area, and a source electrode area and a drain electrode which are respectively positioned in the patterned semiconductor layer on both sides of the channel area. The patterned light absorption layer is positioned between the transparent base plate and patterned semiconductor layer.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate of display floater and thin-film transistor and preparation method thereof, particularly relate to a kind of thin-film transistor that suppresses light leakage current and preparation method thereof.
Background technology
Please refer to Fig. 1.Fig. 1 is the schematic diagram of the thin-film transistor of available liquid crystal display floater.As shown in Figure 1, existing thin-film transistor 10 is formed at the top of the thin film transistor base plate 1 of display panels.Thin-film transistor 10 comprises that semi-conductor layer, a gate insulator 18 are positioned on the semiconductor layer, and a grid 20, is positioned on the gate insulator 18.Semiconductor layer comprises that a channel region 12 and one source pole district 14 and a drain region 16 lay respectively at channel region 12 both sides.
Because display panels is non-self-luminous display device, therefore must be dependent on backlight that backlight module provides as light source.Thin-film transistor is the pixel switch assembly of display panels, and wherein grid is connected with scan line and is subjected to its control and opens, and source area is connected with data wire with acknowledge(ment) signal, and the drain region then is connected with pixel electrode.By above-mentioned connected mode, when grid receives grid voltage, thin-film transistor can be opened and make the signal that data wire sent to arrive pixel electrode via source area, channel region and drain region, and form a liquid crystal capacitance between pixel electrode and the common electrode this moment, can change penetrance backlight by this and reach the purpose of control GTG brightness.Yet as shown in Figure 1, expose to the open air fully under the irradiation of backlight, or under the irradiation of external light source, therefore can cause light leakage current to increase, influence the normal operation of thin-film transistor 10 owing to have the channel region 12 of thin-film transistor 10 now.
Summary of the invention
Thin-film transistor that provides a kind of display floater and preparation method thereof is provided one of purpose of the present invention, to reduce the light leakage current of thin-film transistor.
For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor, be formed on the transparency carrier.Thin-film transistor comprises that a patterned semiconductor layer, a gate insulator are positioned on the patterned semiconductor layer, a grid is positioned on the gate insulator, and a patterning light absorbing zone.Patterned semiconductor layer comprises a channel region, and one source pole district and a drain region lay respectively in the patterned semiconductor layer of channel region both sides.The patterning light absorbing zone is between transparency carrier and patterned semiconductor layer.
Described thin-film transistor, wherein, this patterning light absorbing zone comprises a silicic dielectric layer.
Described thin-film transistor, wherein, this silicic dielectric layer comprises a silicon rich silicon oxide layer, a silicon-rich silicon nitride layer or a Silicon-rich nitrogen oxide layer.
Described thin-film transistor, wherein, the refractive index of this silicic dielectric layer is between 1.7 to 3.7.
Described thin-film transistor, wherein, this patterning light absorbing zone has a thickness between between the 100nm to 300nm.
Described thin-film transistor, wherein, this silicic dielectric layer comprises a silicon nanocrystal grain dielectric layer.
Described thin-film transistor, wherein, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is substantially between 5 to 500 dusts.
Described thin-film transistor, wherein, this patterning light absorbing zone covers this patterned semiconductor layer substantially.
Described thin-film transistor, wherein, other comprises a resilient coating, between this patterned semiconductor layer and this transparency carrier.
Described thin-film transistor, wherein, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
For reaching above-mentioned purpose, the present invention provides a thin film transistor base plate in addition, is applicable to a display floater, comprises a transparency carrier, and a plurality of thin-film transistor is positioned on the transparency carrier.Each thin-film transistor comprises a patterned semiconductor layer, a gate insulator, is positioned on the patterned semiconductor layer, a grid is positioned on the gate insulator, and a patterning light absorbing zone.Patterned semiconductor layer comprises a channel region, and one source pole district and a drain region lay respectively in the patterned semiconductor layer of channel region both sides.The patterning light absorbing zone is between transparency carrier and patterned semiconductor layer.
Described thin film transistor base plate, wherein, this patterning light absorbing zone comprises a silicic dielectric layer.
Described thin film transistor base plate, wherein, this silicic dielectric layer comprises a silicon rich silicon oxide layer, a silicon-rich silicon nitride layer or a Silicon-rich nitrogen oxide layer.
Described thin film transistor base plate, wherein, the refractive index of this silicic dielectric layer is between 1.7 to 3.7.
Described thin film transistor base plate, wherein, this patterning light absorbing zone has a thickness between between the 100nm to 300nm.
Described thin film transistor base plate, wherein, this silicic dielectric layer comprises a silicon nanocrystal grain dielectric layer.
Described thin film transistor base plate, wherein, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is substantially between 5 to 500 dusts.
Described thin film transistor base plate, wherein, this patterning light absorbing zone covers this patterned semiconductor layer substantially.
Described thin film transistor base plate, wherein, other comprises a resilient coating, between this patterned semiconductor layer and this transparency carrier.
Described thin film transistor base plate, wherein, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
For reaching above-mentioned purpose, the present invention provides a kind of method of making thin-film transistor in addition, comprises the following steps.One transparency carrier is provided.Then form a patterning light absorbing zone and a patterned semiconductor layer in regular turn on transparency carrier, wherein this patterning light absorbing zone covers this patterned semiconductor layer substantially.Form a thin-film transistor in this patterned semiconductor layer subsequently.
Described method wherein, forms this thin-film transistor in this patterned semiconductor layer and comprises the following steps:
On this patterned semiconductor layer, form a gate insulator, and on this gate insulator, form a grid; And
In this patterned semiconductor layer, form a channel region, and in this patterned semiconductor layer of the both sides of this channel region, form an one source pole district and a drain region respectively.
Described method, wherein, other is included in and forms before this patterned semiconductor layer, prior to forming a resilient coating on this transparency carrier.
Described method, wherein, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
Described method, wherein, this patterning light absorbing zone comprises a silicic dielectric layer.
Described method, wherein, this silicic dielectric layer comprises a silicon nanocrystal grain dielectric layer.
Described method, wherein, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is substantially between 5 to 500 dusts.
The thin-film transistor of display floater of the present invention utilizes light absorbing zone to cover backlight that backlight module sends, and makes to reduce the semiconductor layer that shines directly into backlight, therefore can reduce the light leakage current problem of thin-film transistor.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the schematic diagram of the thin-film transistor of available liquid crystal display floater;
Fig. 2 to Fig. 5 makes the method schematic diagram of a preferred embodiment of the thin-film transistor of display floater for the present invention;
Fig. 6 and Fig. 7 have illustrated the thin-film transistor of the present invention schematic diagram of two embodiment in addition;
Fig. 8 has illustrated the drain current and the grid voltage graph of a relation of thin-film transistor.
Wherein, Reference numeral:
1 thin film transistor base plate, 10 thin-film transistors
12 channel regions, 14 source areas
16 drain regions, 18 gate insulators
20 grids, 30 transparency carriers
32 patterning light absorbing zones, 34 resilient coatings
36 patterned semiconductor layer 36C channel regions
38 gate insulators, 40 grids
50 thin-film transistors
Embodiment
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is made further more detailed description.
Please refer to Fig. 2 to Fig. 5.Fig. 2 to Fig. 5 makes the method schematic diagram of a preferred embodiment of the thin-film transistor of display floater for the present invention, wherein the display floater of present embodiment is a display panels, but not as limit.Shown in Fig. 2 figure, a transparency carrier 30 at first is provided, wherein transparency carrier 30 is as the thin film transistor base plate of display panels, and it can be the substrate that glass substrate, quartz base plate or plastic base etc. are made of transparent material.Then on transparency carrier 30, form a patterning light absorbing zone 32.Patterning light absorbing zone 32 can comprise a Silicon-rich (silicon-rich) dielectric layer, for example is silicon rich silicon oxide (silicon-richsilicon oxide; Si-rich SiOx) layer, silicon-rich silicon nitride (silicon-rich silicon nitride; Si-richSiNy) layer or Silicon-rich silicon oxynitride (silicon-rich silicon oxynitride; Si-rich SiOxNy) layer, wherein at least one or its stack layer etc. or other Silicon-rich compound.When the material of silicic dielectric layer was silicon rich silicon oxide, the branch subexpression of its silicon rich silicon oxide was SiOx, and wherein x is greater than 0 and less than 2.When the material of silicic dielectric layer for example was silicon-rich silicon nitride, the molecular formula of its silicon-rich silicon nitride was SiNy, and wherein y is greater than 0 and less than 4/3 (about 1.67).When the Silicon-rich dielectric material for example was the Silicon-rich silicon oxynitride, the molecular formula of its Silicon-rich silicon oxynitride was SiOxNy, and wherein (x+y) is greater than 0 and less than 2.
In present embodiment, the formation of silicic dielectric layer can be via plasma enhanced chemical vapor deposition manufacturing process (plasma enhanced chemical vapor deposition, PECVD), and plasma enhanced chemical vapor deposition manufacturing process by feeding silane (SiH
4), nitrous oxide (N
2O) or ammonia (NH
3) wait mist and adjust proper proportion and deposit silicic dielectric layer, silicon rich silicon oxide, silicon-rich silicon nitride or Silicon-rich silicon oxynitride are amassed out in Shen by this.For instance, if the mist that feeds is that silane and nitrous oxide then can amass out silicon rich silicon oxide (Si-rich SiOx) in Shen, if the mist that feeds is silane and ammonia (NH
3But) then Shen amass out silicon-rich silicon nitride (Si-rich SiNy), but if silane, nitrous oxide and ammonia that the mist that feeds is then amass out Silicon-rich silicon oxynitride (Si-rich SiOxNy) in Shen.In addition, silicone content is healed high index of refraction more greatly in the silicic dielectric layer, and its refractive index is between 1.7 to 3.7, and its thickness of tool is reducible between between the 100nm to 300nm.
Patterning light absorbing zone 32 is preferably silicon nanocrystal grain (nanocrystalline silicon) dielectric layer, wherein the diameter of the silicon nanocrystal grain of silicon nanocrystal grain dielectric layer is substantially between 5 to 500 dusts, can utilize low temperature annealing laser manufacturing process to form, but not as limit.The effect of patterning light absorbing zone 32 be to absorb by transparency carrier 30 belows inject backlight, because backlight illumination produces light leakage current, and better effect is arranged to avoid thin-film transistor.
As shown in Figure 3, then optionally on transparency carrier 30 or patterning light absorbing zone 32, form a resilient coating 34.The effect of resilient coating 34 is to avoid the impurity in the transparency carrier 30 to diffuse in the semiconductor layer in follow-up manufacturing process, and influences the normal operation of thin-film transistor.In the present embodiment, resilient coating 34 is not limited to be formed on the top of patterning light absorbing zone 32, also can before forming patterning light absorbing zone 32, be formed at earlier on the transparency carrier 30, in addition resilient coating 32 can be the single layer structure layer for example for buffer oxide layer or the buffering nitration case, or the multilayer structure layer for example comprise simultaneously buffer oxide layer with the buffering nitration case.
As shown in Figure 4, then on resilient coating 34, form patterned semiconductor layer 36, for example a polysilicon layer.In the present embodiment, patterning light absorbing zone 32, resilient coating 34 and patterned semiconductor layer 36 can utilize same light shield to define by once little shadow and etching manufacturing process, but method of the present invention is not as limit.In addition, the size of patterning light absorbing zone 32 and the pattern of patterned semiconductor layer 36 equate substantially and shape corresponding, patterning light absorbing zone 32 can cover patterned semiconductor layer 36 and avoids patterned semiconductor layer 36 to be subjected to backlight illumination and produce leakage current by this, but can not influence the aperture opening ratio of display floater.
As shown in Figure 5, then on patterned semiconductor layer 36, form a gate insulator 38, and on gate insulator 38, form a grid 40.Utilize the position of implanting ions manufacturing process corresponding grid 40 in patterned semiconductor layer 36 to form a channel region 36C subsequently, and in the patterned semiconductor layer 36 of the both sides of channel region 36C, form an one source pole district 36S and a drain region 36D respectively, promptly produce thin-film transistor 50.
From the above, thin-film transistor 50 of the present invention is provided with light absorbing zone 32 in semiconductor layer 36 belows, and it is backlight to avoid thin-film transistor 50 to produce light leakage currents to use absorption.Light absorbing zone 32 should be chosen in the material that wave-length coverage backlight (most of for visible wavelength range) has high-absorbility, use effectively cover backlight.In the above-described embodiments, select the silicic dielectric layer that includes the silicon nanocrystal grain material for use as light absorbing zone 32, however the present invention can not select for use other to be fit to as limit light absorbing material.
Please refer to Fig. 6 and Fig. 7.Fig. 6 and Fig. 7 have illustrated the thin-film transistor of the present invention schematic diagram of two embodiment in addition, and wherein for ease of comparing the similarities and differences of each embodiment, the same components of thin-film transistor is used the same-sign mark in each embodiment.As shown in Figure 6, in the present embodiment, form patterning light absorbing zone 32 earlier and form resilient coating 34 again, so patterning light absorbing zone 32 is positioned at the below of resilient coating 34.In the present embodiment, resilient coating 34 can be the single layer structure layer and for example is buffer oxide layer or buffering nitration case, or the multilayer structure layer for example comprises buffer oxide layer and buffering nitration case simultaneously.As shown in Figure 7, because patterning light absorbing zone 32 itself also has the effect of the diffusion of impurities of preventing, therefore thin-film transistor 50 is provided with patterning light absorbing zone 32 but is not provided with resilient coating in the present embodiment.
Please refer to Fig. 8.Fig. 8 has illustrated the drain current (Drain Current) and grid voltage (Gate Voltage) graph of a relation of thin-film transistor.Fig. 8 includes four curves, and its experiment condition is as described below:
Curve A: be not provided with light absorbing zone and backlight closing;
Curve B: be not provided with light absorbing zone and backlight open (backlight illumination is 5000nits);
Curve C: be provided with light absorbing zone (using silicic dielectric layer, thickness) and backlight open approximately between 2000 to 3000 dusts; And
Curve D: be provided with light absorbing zone and backlight closing.
As shown in Figure 8, do not reach at grid voltage and to open the beginning during (threshold) voltage, be provided with the thin-film transistor of light absorbing zone, its drain current has clearly less than the drain current of the thin-film transistor that is not provided with light absorbing zone under the situation of backlight open (curve B) under the situation of backlight open (curve C).
From the above, the thin-film transistor utilization of display floater of the present invention is provided with the mode of light absorbing zone, can effectively reduce the leakage problem of thin-film transistor really, and promotes reliability by this.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (19)
1. a thin-film transistor is formed on the transparency carrier, it is characterized in that, this thin-film transistor comprises:
One patterned semiconductor layer is positioned on this transparency carrier, comprising:
One channel region; And
An one source pole district and a drain region lay respectively in this patterned semiconductor layer of these channel region both sides;
One gate insulator is positioned on this patterned semiconductor layer;
One grid is positioned on this gate insulator; And
One patterned silicon nanocrystal dielectric layer between this transparency carrier and this patterned semiconductor layer, is used to absorb a light.
2. thin-film transistor according to claim 1 is characterized in that, the refractive index of this patterned silicon nanocrystal dielectric layer is between 1.7 to 3.7.
3. thin-film transistor according to claim 1 is characterized in that, this patterned silicon nanocrystal dielectric layer has a thickness between between the 100nm to 300nm.
4. thin-film transistor according to claim 1 is characterized in that, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is between 5 to 500 dusts.
5. thin-film transistor according to claim 1 is characterized in that, this patterned silicon nanocrystal dielectric layer covers this patterned semiconductor layer.
6. thin-film transistor according to claim 1 is characterized in that other comprises a resilient coating, between this patterned semiconductor layer and this patterned silicon nanocrystal dielectric layer.
7. thin-film transistor according to claim 6 is characterized in that, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
8. a thin film transistor base plate is applicable to a display floater, it is characterized in that, comprising:
One transparency carrier; And
A plurality of thin-film transistors are positioned on this transparency carrier, and respectively this thin-film transistor comprises:
One patterned semiconductor layer comprises:
One channel region; And
An one source pole district and a drain region lay respectively in this patterned semiconductor layer of these channel region both sides;
One gate insulator is positioned on this patterned semiconductor layer;
One grid is positioned on this gate insulator; And
One patterned silicon nanocrystal dielectric layer between this transparency carrier and this patterned semiconductor layer, is used to absorb a light.
9. thin film transistor base plate according to claim 8 is characterized in that, the refractive index of this patterned silicon nanocrystal dielectric layer is between 1.7 to 3.7.
10. thin film transistor base plate according to claim 8 is characterized in that, this patterned silicon nanocrystal dielectric layer has a thickness between between the 100nm to 300nm.
11. thin film transistor base plate according to claim 8 is characterized in that, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is between 5 to 500 dusts.
12. thin film transistor base plate according to claim 8 is characterized in that, this patterned silicon nanocrystal dielectric layer covers this patterned semiconductor layer.
13. thin film transistor base plate according to claim 8 is characterized in that, other comprises a resilient coating, between this patterned semiconductor layer and this patterned silicon nanocrystal dielectric layer.
14. thin film transistor base plate according to claim 13 is characterized in that, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
15. a method of making thin-film transistor is characterized in that, comprising:
One transparency carrier is provided;
Form a patterned silicon nanocrystal dielectric layer and a patterned semiconductor layer on this transparency carrier in regular turn, this patterned silicon nanocrystal dielectric layer covers this patterned semiconductor layer, and wherein this patterned silicon nanocrystal dielectric layer is used to absorb a light; And
Form a thin-film transistor in this patterned semiconductor layer.
16. method according to claim 15 is characterized in that, forms this thin-film transistor in this patterned semiconductor layer and comprises the following steps:
On this patterned semiconductor layer, form a gate insulator, and on this gate insulator, form a grid; And
In this patterned semiconductor layer, form a channel region, and in this patterned semiconductor layer of the both sides of this channel region, form an one source pole district and a drain region respectively.
17. method according to claim 15 is characterized in that, other is included in and forms before this patterned semiconductor layer, prior to forming a resilient coating on this patterned silicon nanocrystal dielectric layer.
18. method according to claim 17 is characterized in that, this resilient coating comprises a buffer oxide layer or a buffering nitration case.
19. method according to claim 15 is characterized in that, the diameter of the silicon nanocrystal grain of this silicon nanocrystal grain dielectric layer is between 5 to 500 dusts.
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| CN2008101320980A CN101330106B (en) | 2008-07-28 | 2008-07-28 | Thin-film transistor substrate and thin-film transistor for display panel as well as preparation method thereof |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103681869A (en) * | 2012-08-31 | 2014-03-26 | 群康科技(深圳)有限公司 | Thin film transistor substrate, manufacturing method for thin film transistor substrate, and display |
| CN104900711B (en) | 2015-06-08 | 2019-11-05 | 京东方科技集团股份有限公司 | Thin film transistor and its manufacturing method and array substrate, display device |
| CN105470268A (en) | 2016-01-11 | 2016-04-06 | 京东方科技集团股份有限公司 | Array substrate, fabrication method thereof and display device |
| TWI608624B (en) * | 2016-09-07 | 2017-12-11 | 友達光電股份有限公司 | Thin film transistor of display panel and method for manufacturing the same |
| CN108573981B (en) * | 2017-03-10 | 2021-12-03 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN107046042B (en) * | 2017-04-20 | 2019-08-23 | 京东方科技集团股份有限公司 | A kind of low temperature polycrystalline silicon backboard and its manufacturing method, display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064091A (en) * | 1997-12-10 | 2000-05-16 | U.S. Philips Corporation | Thin film transistors having an active region composed of intrinsic and amorphous semiconducting layers |
| US6734052B2 (en) * | 1999-12-10 | 2004-05-11 | Koninklijke Philips Electronics N.V. | Method of manufacturing thin film transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064091A (en) * | 1997-12-10 | 2000-05-16 | U.S. Philips Corporation | Thin film transistors having an active region composed of intrinsic and amorphous semiconducting layers |
| US6734052B2 (en) * | 1999-12-10 | 2004-05-11 | Koninklijke Philips Electronics N.V. | Method of manufacturing thin film transistor |
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