CN102054874B - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN102054874B CN102054874B CN201010533970XA CN201010533970A CN102054874B CN 102054874 B CN102054874 B CN 102054874B CN 201010533970X A CN201010533970X A CN 201010533970XA CN 201010533970 A CN201010533970 A CN 201010533970A CN 102054874 B CN102054874 B CN 102054874B
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- layer
- film transistor
- thickness
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a thin film transistor and a manufacturing method thereof. The thin film transistor comprises a substrate, a semiconductor layer, a patterning doped semiconductor layer, a source electrode, a drain electrode, a grid isolating layer and a grid electrode, wherein the semiconductor layer is arranged on the substrate; the patterning doped semiconductor layer is arranged above two opposite sides of the semiconductor layer; the source electrode and the drain electrode are arranged on the patterning doped semiconductor layer and above two opposite sides of the semiconductor layer; a part of the semiconductor layer covered by the source electrode and the drain electrode has a first thickness, a part of the semiconductor layer, which is positioned between the source electrode and the drain electrode and not covered by the source electrode and the drain electrode, has a second thickness, and the second thickness is between 200 angstroms and 800 angstroms; the grid isolating layer is arranged on the source electrode, the drain electrode and a part of semiconductor layer; and the grid is arranged on the grid isolating layer. The thin film transistor provided by the invention has better element characteristics.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacturing approach thereof, and particularly relevant for a kind of thin-film transistor and manufacturing approach thereof.
Background technology
In recent years; Increasingly mature along with photoelectric technology and semiconductor fabrication; Flat-panel screens is just flourish; Wherein LCD is based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, replaces traditional cathode-ray tube display more gradually and becomes the main flow of display product in recent years.Generally speaking, LCD can be divided into two kinds of amorphous silicon film transistor (amorphous silicon thinfilm transistor) LCD and low-temperature polysilicon film transistor (low temperaturepoly-silicon thin film transistor) LCDs etc.
Because low-temperature polysilicon film transistor has higher carrier mobility and preferable element stability, so its application in product design is wider.Yet when panel develops towards large scale, the making of low-temperature polysilicon film transistor but is subject to technological temperature and board specification, makes it be difficult to be applied in the large size panel.For instance, in the technology of low-temperature polysilicon film transistor, must adopt the implantation mode to form doped region, the technology of large size panel forms low-temperature polysilicon film transistor yet existing implantation board specification but can't be arranged in pairs or groups.On the contrary, the technology of amorphous silicon film transistor meets the requirement of large tracts of land production, therefore; Someone proposes to combine polysilicon process and amorphous silicon technology to come the manufacturing polycrystalline silicon thin-film transistor; For instance, (Solid Phase Crystallization SPC) waits crystallization mode to form the crystalline portion of polycrystalline SiTFT with the solid-phase crystallization technology; Remainder is then accomplished in the production line of amorphous silicon film transistor, to avoid the use of the doping board.Yet,, can receive the influence of the etch process of channel layer with the architectural characteristic of the formed polycrystalline SiTFT of said method, and element characteristic will be influenced by the channel layer structure obviously via experiment confirm.
Summary of the invention
The present invention provides a kind of thin-film transistor and manufacturing approach thereof, makes thin-film transistor have preferable element characteristic.
The present invention proposes a kind of thin-film transistor, and it comprises a substrate, semi-conductor layer, a patterning doping semiconductor layer, one source pole and a drain electrode, a gate insulation layer and a grid.Semiconductor layer is disposed on the substrate.The patterning doping semiconductor layer is disposed at the top, relative both sides of semiconductor layer.Source electrode and drain configuration are on the patterning doping semiconductor layer and be positioned at the top, relative both sides of semiconductor layer; Wherein had one first thickness by source electrode and the part semiconductor layer that drain electrode covers; And between source electrode and drain electrode and not, being had one second thickness by source electrode and the part semiconductor layer that drain electrode covers, second thickness is between 200 dust to 800 dusts.Gate insulation layer is disposed on source electrode and drain electrode and the part semiconductor layer.Gate configuration is on gate insulation layer.
Wherein, this second thickness is between 300 dust to 400 dusts.
Wherein, this semiconductor layer comprises a polysilicon layer.
Wherein, this patterning doping semiconductor layer comprises a N type doped amorphous silicon layer.
Wherein, This patterning doping semiconductor layer comprises one first doping semiconductor layer and one second doping semiconductor layer; This first doping semiconductor layer is between this semiconductor layer and this source electrode and coat one first side surface of this semiconductor layer; This second doping semiconductor layer is between this semiconductor layer and this drain electrode and coat one second side surface of this semiconductor layer, and wherein this first side surface and this second side surface are positioned at the relative both sides of this semiconductor layer.
Wherein, align with the inside edge of this source electrode in the inside edge of this first doping semiconductor layer, and align with the inside edge of this drain electrode in the inside edge of this second doping semiconductor layer.
Wherein, the outer ledge of this first doping semiconductor layer aligns with the outer ledge of this source electrode, and the outer ledge of this second doping semiconductor layer aligns with the outer ledge of this drain electrode.
Wherein, this first thickness is substantially greater than this second thickness.
Wherein, this first thickness equals this second thickness substantially.
The present invention proposes a kind of method of manufacturing thin film transistor in addition.On a substrate, form semi-conductor layer, semiconductor layer has one first thickness.On semiconductor layer, form a patterning doping semiconductor layer.On the patterning doping semiconductor layer, form an one source pole and a drain electrode; Source electrode is positioned at above the relative both sides of semiconductor layer with drain electrode; Wherein between source electrode and drain electrode and not, had one second thickness by source electrode and the semiconductor layer that drain electrode covers, second thickness is between 200 dust to 800 dusts.Go up formation one gate insulation layer in source electrode and drain electrode, to cover source electrode and drain electrode, patterning doping semiconductor layer and semiconductor layer.On gate insulation layer, form a grid.
Wherein, this second thickness is between 300 dust to 400 dusts.
Wherein, this first thickness is substantially greater than this second thickness.
Wherein, this patterning doping semiconductor layer comprises N type admixture.
Wherein, the formation method of this patterning doping semiconductor layer comprises sedimentation.
Wherein, the formation method of this patterning doping semiconductor layer comprises chemical vapour deposition technique.
Wherein, the formation method of this patterning doping semiconductor layer comprises: on this semiconductor layer, form the semiconductor material layer; Carry out a doping process, this semiconductor material layer is transformed into a doped semiconductor material layer; And remove this doped semiconductor material layer of part, form this patterning doping semiconductor layer with top, relative both sides in this semiconductor layer.
Wherein, the formation method of the formation method of this patterning doping semiconductor layer and this source electrode and this drain electrode comprises: on this semiconductor layer, form a doped semiconductor material layer and a conductor layer in regular turn; On this conductor layer, form a patterned mask layer; And be mask with this patterned mask layer; Remove this conductor layer of part and this doped semiconductor material layer of part; Forming this source electrode and this drain electrode and this patterning doping semiconductor layer, and do not make this semiconductor layer that is covered by this source electrode and this drain electrode have this second thickness.
Wherein, remove this conductor layer of part and this doped semiconductor material layer of part after, more comprise removing not by this source electrode this semiconductor layer of part with this drain electrode covering, make this first thickness substantially greater than this second thickness.
Wherein, the formation method of this semiconductor layer comprises: on this substrate, form an amorphous silicon layer; And this amorphous silicon layer is transformed into a polysilicon layer.
Wherein, the method that this amorphous silicon layer is transformed into this polysilicon layer comprises the solid-phase crystallization method.
Wherein, this first thickness equals this second thickness substantially.
Based on above-mentioned, in thin-film transistor of the present invention, between source electrode and drain electrode and not, had thickness between 200 dust to 800 dusts by source electrode and the semiconductor layer that drain electrode covers, make thin-film transistor have preferable element characteristic.
Describe the present invention below in conjunction with accompanying drawing and specific embodiment, but not as to qualification of the present invention.
Description of drawings
Figure 1A to Fig. 1 D is the flow process generalized section of a kind of method of manufacturing thin film transistor of the first embodiment of the present invention;
Fig. 2 A to Fig. 2 D is the flow process generalized section of a kind of method of manufacturing thin film transistor of the second embodiment of the present invention.
Wherein, Reference numeral:
100,100a: thin-film transistor
102: substrate
104a, 104b: side surface
104: semiconductor layer
108: doped semiconductor material layer
110: the patterning doping semiconductor layer
112,114: doping semiconductor layer
112a, 114a, 120a, 122a: inside edge
112b, 114b, 120b, 122b: outer ledge
118: conductor layer
119: the patterned mask layer
120: source electrode
122: drain electrode
130: gate insulation layer
140: grid
150: insulating barrier
T1, t2: thickness
Embodiment
[first embodiment]
Figure 1A to Fig. 1 D is the flow process generalized section of a kind of method of manufacturing thin film transistor of the first embodiment of the present invention.Please with reference to Figure 1A, at first, on a substrate 102, form semi-conductor layer 104, semiconductor layer 104 has one first thickness t 1.In the present embodiment, substrate 102 can be glass substrate, quartz base plate or other material substrate, and the present invention does not limit.Semiconductor layer 104 for example is a polysilicon layer, and its formation method for example is sedimentation or crystallisation.In the present embodiment, for example be prior to forming an amorphous silicon layer (not illustrating) on the substrate 102, again amorphous silicon layer is transformed into polysilicon layer such as solid-phase crystallization method (SPC), PRK method crystallisations such as (ELA).Wherein, first thickness t 1 for example is between 200 dust to 800 dusts, is preferably between 300 dust to 400 dusts.
Please, then, on semiconductor layer 104, form a patterning doping semiconductor layer 110 with reference to Figure 1B.In the present embodiment, the method for formation patterning doping semiconductor layer 110 for example is prior to forming a doped semiconductor material layer (not illustrating) on the semiconductor layer 104.Then, remove the part doped semiconductor material layer, to form patterning doping semiconductor layer 110.In the present embodiment, patterning doping semiconductor layer 110 for example is to comprise N type admixture, and its formation method can be sedimentation or doping process.For instance, patterning doping semiconductor layer 110 for example is a N type doped amorphous silicon layer, and its formation method for example is a chemical vapour deposition technique.Shown in Figure 1B; Patterning doping semiconductor layer 110 for example is to comprise first doping semiconductor layer 112 and second doping semiconductor layer 114; Wherein first doping semiconductor layer 112 for example is the one first side surface 104a that coats semiconductor layer 104; Second doping semiconductor layer 114 for example is the one second side surface 104b that coats semiconductor layer 104, and wherein the first side surface 104a and the second side surface 104b are positioned at the relative both sides of semiconductor layer 104.Special one carry be; Though be that to form doped semiconductor material layer with sedimentation be example in the present embodiment; But also can be prior to forming the semiconductor material layer on the semiconductor layer 104, again semiconductor material layer being carried out doping process to form doped semiconductor material layer in another embodiment.In other words, patterning doping semiconductor layer 110 can any prior art method form, and the present invention does not limit.
Please with reference to Fig. 1 C; Then; On patterning doping semiconductor layer 110, form an one source pole 120 and a drain electrode 122; Source electrode 120 is positioned at drain electrode 122 above the relative both sides of semiconductor layer 104, wherein between source electrode 120 and drain electrode 122, is not had one second thickness t, 2, the second thickness t 2 between 200 dust to 800 dusts by source electrode 120 and the part semiconductor layer 104 that drain electrode 122 covers.In the present embodiment; For example be prior to forming a conductor layer (not illustrating) on the patterning doping semiconductor layer 110; Again conductor layer is carried out patterning, form source electrode 120 and drain electrode 122 and expose the semiconductor layer 104 between source electrode 120 and drain electrode 122 with top, relative both sides in semiconductor layer 104.Source electrode 120 for example is titanium, aluminium, molybdenum and various combination thereof or other electric conducting material with the material of drain electrode 122, and its formation method for example is a physical vaporous deposition.In the present embodiment; The inside edge 112a of first doping semiconductor layer 112 aligns in fact with the inside edge 120a of source electrode 120, and the inside edge 114a of second doping semiconductor layer 114 aligns in fact with the inside edge 122a of drain electrode 122.In another embodiment; Prior to forming a doped semiconductor material layer (not illustrating) on the semiconductor layer 104; On doped semiconductor material layer, form a conductor layer (not illustrating) again; Simultaneously conductor layer and doped semiconductor material layer are carried out patterning again, can use same light shield to reach (not illustrating), the present invention does not limit.
In the present embodiment; After forming semiconductor layer 104; Part semiconductor layer 104 is not removed step; Therefore semiconductor layer 104 has the thickness of homogeneous substantially, the part semiconductor layer 104 that just between source electrode 120 and drain electrode 122 and is not covered by source electrode 120 and drain electrode 122 with had identical thickness substantially by the part semiconductor layer 104 of source electrode 120 and drain electrode 122 coverings.Therefore, second thickness t 2 is equal to first thickness t 1 substantially, and second thickness t 2 is preferably between 300 dust to 400 dusts.
Please with reference to Fig. 1 D, then, in source electrode 120 and drain electrode 122, form a gate insulation layer 130, to cover source electrode 120 and drain electrode 122 and part semiconductor layer 104.The material of gate insulation layer 130 for example is silica, silicon nitride or other insulating material, and its formation method for example is a chemical vapour deposition technique.Then, on gate insulation layer 130, form a grid 140.The material of grid 140 for example is titanium, aluminium, molybdenum and various combination thereof or other electric conducting material, and its formation method for example is a physical vaporous deposition.Then, on grid 140, form an insulating barrier 150, with cover gate 140, gate insulation layer 130, source electrode 120 and drain electrode 122 and semiconductor layer 104.The material of insulating barrier 150 for example is silica, silicon nitride or other insulating material, and its formation method for example is a chemical vapour deposition technique.
In the present embodiment, thin-film transistor 100 comprises substrate 102, semiconductor layer 104, patterning doping semiconductor layer 110, source electrode 120 and drain electrode 122, gate insulation layer 130, grid 140 and insulating barrier 150.Semiconductor layer 104 is disposed on the substrate 102.Patterning doping semiconductor layer 110 is disposed at the top, relative both sides of semiconductor layer 104.Patterning doping semiconductor layer 110 for example is to comprise N type admixture, and patterning doping semiconductor layer 110 for example is to comprise first doping semiconductor layer 112 and second doping semiconductor layer 114.First doping semiconductor layer 112 for example is between semiconductor layer 104 and source electrode 120 and coats one first side surface 104a of semiconductor layer 104; Second doping semiconductor layer 114 for example is between semiconductor layer 104 and drain electrode 122 and coats one second side surface 104b of semiconductor layer 104 that wherein the first side surface 104a and the second side surface 104b are positioned at the relative both sides of semiconductor layer 104.In addition; In the present embodiment; The inside edge 112a of first doping semiconductor layer 112 aligns in fact with the inside edge 120a of source electrode 120, and the inside edge 114a of second doping semiconductor layer 114 aligns in fact with the inside edge 122a of drain electrode 122.Certainly; In other embodiments; The inside edge 112a of first doping semiconductor layer 112 and the inside edge 120a of source electrode 120 also can be unjustified, or the inside edge 114a of second doping semiconductor layer 114 also can be unjustified with the inside edge 122a of drain electrode 122.
In general, can influence the element characteristic of thin-film transistor as the thickness of the semiconductor layer of channel layer.Therefore; In the manufacturing approach of the thin-film transistor 100 of present embodiment; THICKNESS CONTROL with semiconductor layer 104 in forming the step of semiconductor layer 104 is 200 dust to 800 dusts, makes between source electrode 120 and drain electrode 122 and is not 200 dust to 800 dusts by the thickness of source electrode 120 and the semiconductor layer 104 of drain electrode 122 coverings.When experiment showed, that thickness when the semiconductor layer 104 that is not covered by source electrode 120 and drain electrode 122 is between 200 dust to 800 dusts, thin-film transistor 100 can have preferable element characteristic really.In addition; In the present embodiment; Can form patterning doping semiconductor layer 110 such as depositional modes such as chemical vapour deposition techniques; And need not to use the doping board to form patterning doping semiconductor layer 110, so the technology of thin-film transistor 100 need not be subject to the specification of doping board and can combine with existing amorphous silicon film transistor technology.In other words, thin-film transistor and forming method thereof can make thin-film transistor have preferable element characteristic and meet the requirement of large tracts of land production, can be applied to the thin-film transistor in the large size panel to make, and then promotes the display quality of panel.
[second embodiment]
Fig. 2 A to Fig. 2 D is the flow process generalized section of a kind of method of manufacturing thin film transistor of the second embodiment of the present invention.Please with reference to Fig. 2 A, at first, on a substrate 102, form semi-conductor layer 104, semiconductor layer 104 has one first thickness t 1.In the present embodiment, substrate 102 can be glass substrate, quartz base plate or other material substrate.Semiconductor layer 104 for example is a polysilicon layer, and its formation method for example is sedimentation or crystallisation.In the present embodiment, for example be prior to forming an amorphous silicon layer (not illustrating) on the substrate 102, again amorphous silicon layer is transformed into polysilicon layer such as solid-phase crystallization method (SPC), PRK method crystallisations such as (ELA).Wherein, first thickness t 1 for example is between 300 dust to 2000 dusts.
Please, then, on semiconductor layer 104, form a doped semiconductor material layer 108 with reference to Fig. 2 A.Doped semiconductor material layer 108 for example is a N type doped amorphous silicon layer, and its formation method for example is a chemical vapour deposition technique.Then, on doped semiconductor material layer 108, form a conductor layer 118.The material of conductor layer 118 for example is titanium, aluminium, molybdenum and various combination thereof or other electric conducting material, and its formation method for example is a physical vaporous deposition.Then, on conductor layer 118, form a patterned mask layer 119, patterned mask layer 119 covers the top, relative both sides of semiconductor layer 104.In another embodiment, can not be to use same patterned mask layer to come to define simultaneously doped semiconductor material layer 108 and conductor layer 118, the present invention does not limit yet.
, then, be mask please, remove segment conductor layer 118 and part doped semiconductor material layer 108, to form source electrode 120 and drain electrode 122 and patterning doping semiconductor layer 110 with patterned mask layer 119 with reference to Fig. 2 C.In addition; In the present embodiment; After removing segment conductor layer 118 and part doped semiconductor material layer 108; More comprise removing, make do not had second thickness t, 2, the second thickness t 2 between 200 dust to 800 dusts by source electrode 120 and the part semiconductor layer 104 that drain electrode 122 covers not by source electrode 120 and the part semiconductor layer 104 that drain electrode 122 covers.Thus; Had first thickness t 1 by source electrode 120 and the semiconductor layer 104 that drain electrode 122 covers; Between source electrode 120 and drain electrode 122 and not, had second thickness t 2, and first thickness t 1 is substantially greater than second thickness t 2 by source electrode 120 and the semiconductor layer 104 that drain electrode 122 covers.Wherein, the method that removes segment conductor layer 118, part doped semiconductor material layer 108 and part doped semiconductor material layer 108 for example is a dry etch process again after dry etch process or wet etch process or the first wet etch process.Then, remove patterned mask layer 119.Special one carry be; In the present embodiment; Be to be that mask removes part doped semiconductor material layer 108 forming patterning doping semiconductor layer 110 with patterned mask layer 119, yet, in another embodiment; Can be to form source electrode 120 and draining just to remove patterned mask layer 119 after 122 earlier in formation also, be that mask removes part doped semiconductor material layer 108 with formation patterning doping semiconductor layer 110 with source electrode 120 and drain electrode 122 again.
In the present embodiment, patterning doping semiconductor layer 110 for example is to comprise first doping semiconductor layer 112 and second doping semiconductor layer 114.Because source electrode 120 is by forming with the formed patterned mask layer 119 of light shield with drain electrode 122 and patterning doping semiconductor layer 110; Therefore the inside edge 112a of first doping semiconductor layer 112 aligns in fact with the inside edge 120a of source electrode 120, and the inside edge 114a of second doping semiconductor layer 114 aligns in fact with the inside edge 122a of drain electrode 122.The outer ledge 112b of first doping semiconductor layer 112 aligns in fact with the outer ledge 120b of source electrode 120, and the outer ledge 114b of second doping semiconductor layer 114 aligns in fact with the outer ledge 122b of drain electrode 122.In addition; First doping semiconductor layer 112 for example is between semiconductor layer 104 and source electrode 120 and coats one first side surface 104a of semiconductor layer 104; Second doping semiconductor layer 114 for example is between semiconductor layer 104 and drain electrode 122 and coats one second side surface 104b of semiconductor layer 104 that wherein the first side surface 104a and the second side surface 104b are positioned at the relative both sides of semiconductor layer 104.But in another embodiment, source electrode 120 and drain electrode 122 also can not coat the side surface of semiconductor layer 104, but the outer ledge of the outer ledge of source electrode 120 and drain electrode 122 and the side surface of semiconductor layer 104 align in fact (not illustrating).
Please with reference to Fig. 2 D, then, in source electrode 120 and drain electrode 122, form a gate insulation layer 130, to cover source electrode 120 and drain electrode 122 and part semiconductor layer 104.Then, on gate insulation layer 130, form a grid 140.Then, on grid 140, form an insulating barrier 150, with cover gate 140, gate insulation layer 130, source electrode 120 and drain electrode 122 and semiconductor layer 104.Wherein, the material of gate insulation layer 130, grid 140 and insulating barrier 150 and formation method can not given unnecessary details in this with reference to described in first embodiment.
In the present embodiment, thin-film transistor 100a comprises substrate 102, semiconductor layer 104, patterning doping semiconductor layer 110, source electrode 120 and drain electrode 122, gate insulation layer 130, grid 140 and insulating barrier 150.Semiconductor layer 104 is disposed on the substrate 102.Patterning doping semiconductor layer 110 is disposed at the top, relative both sides of semiconductor layer 104.Patterning doping semiconductor layer 110 for example is to comprise N type admixture, and patterning doping semiconductor layer 110 for example is to comprise first doping semiconductor layer 112 and second doping semiconductor layer 114.First doping semiconductor layer 112 for example is between semiconductor layer 104 and source electrode 120 and coats one first side surface 104a of semiconductor layer 104; Second doping semiconductor layer 114 for example is between semiconductor layer 104 and drain electrode 122 and coats one second side surface 104b of semiconductor layer 104 that wherein the first side surface 104a and the second side surface 104b are positioned at the relative both sides of semiconductor layer 104.In addition; In the present embodiment; The inside edge 112a of first doping semiconductor layer 112 aligns in fact with the inside edge 120a of source electrode 120, and the inside edge 114a of second doping semiconductor layer 114 aligns in fact with the inside edge 122a of drain electrode 122.The outer ledge 112b of first doping semiconductor layer 112 aligns in fact with the outer ledge 120b of source electrode 120, and the outer ledge 114b of second doping semiconductor layer 114 aligns in fact with the outer ledge 122b of drain electrode 122.
Source electrode 120 is disposed on the patterning doping semiconductor layer 110 with drain electrode 122 and is positioned at the top, relative both sides of semiconductor layer 104; Wherein had first thickness t 1 by source electrode 120 and the semiconductor layer 104 that drain electrode 122 covers; And between source electrode 120 and drain electrode 122 and not, had second thickness t, 2, the second thickness t 2 between 200 dust to 800 dusts by source electrode 120 and the semiconductor layer 104 that drain electrode 122 covers.In the present embodiment; First thickness t 1 is substantially greater than second thickness t 2; That is to say that the thickness t 1 of the semiconductor layer 104 that is covered by source electrode 120 and drain electrode 122 is substantially greater than between source electrode 120 and the drain electrode 122 and not by the thickness t 2 of source electrode 120 with the semiconductor layer 104 of drain electrode 122 coverings.Wherein, first thickness t 1 for example is between 300 dust to 2000 dusts, and second thickness t 2 for example is between 300 dust to 400 dusts.Gate insulation layer 130 is disposed on source electrode 120 and drain electrode 122 and the part semiconductor layer 104.Grid 140 is disposed on the gate insulation layer 130.Insulating barrier 150 is disposed on grid 140 and the gate insulation layer 130, with cover gate 140, gate insulation layer 130, source electrode 120 and drain electrode 122 and semiconductor layer 104.
In general; In removing doped semiconductor material layer 108 and conductor layer 118 technology with formation patterning doping semiconductor layer 110 and source electrode 120 and drain electrode 122; May remove downwards in the lump not by source electrode 120 and the semiconductor layer 104 (being channel layer) that drain electrode 122 covers, cause the element characteristic of thin-film transistor influenced.Therefore, in the present embodiment, become to make the semiconductor layer 104 that is not covered to have the thickness of 200 dust to 800 dusts the technology controlling and process that removes semiconductor layer 104 by source electrode 120 and drain electrode 122.Thus, make thin-film transistor 100a have preferable element characteristic.In addition; In the present embodiment; Can form patterning doping semiconductor layer 110 such as depositional modes such as chemical vapour deposition techniques; And need not to use the doping board to form patterning doping semiconductor layer 110, so the technology of thin-film transistor 100a need not be subject to the specification of doping board and can combine with existing amorphous silicon film transistor technology.In other words, thin-film transistor and forming method thereof can make thin-film transistor have preferable element characteristic and meet the requirement of large tracts of land production, can be applied to the thin-film transistor in the large size panel to make, and then promotes the display quality of panel.
What pay special attention to is; Though in the above embodiments be respectively with thin-film transistor 100 with the structure shown in Fig. 1 D and Fig. 2 D, 100a with and said technology be example; Yet the invention is not restricted to this; In other words, the spirit of thin-film transistor of the present invention and manufacturing approach thereof is to make not the thickness of the semiconductor layer that is covered by source electrode and drain electrode between 200 dust to 800 dusts, and therefore thin-film transistor of the present invention and manufacturing approach thereof can be applicable to have in the thin-film transistor of other structure.For instance; Though be that to equal second thickness t 2 substantially with first thickness t 1 be example in the thin-film transistor 100 shown in Fig. 1 D; But in another embodiment; In the thin-film transistor with the structure shown in Fig. 1 D, first thickness t 1 also can be substantially greater than second thickness t 2, and the thickness t 2 of the semiconductor layer that is not wherein covered by source electrode and drain electrode is between 200 dust to 800 dusts.Similarly, in another embodiment, in the thin-film transistor with the structure shown in Fig. 2 D, first thickness t 1 also can be to equal second thickness t 2 substantially, and the thickness t 2 of the semiconductor layer that is not wherein covered by source electrode and drain electrode is between 200 dust to 800 dusts.
In sum, in thin-film transistor of the present invention, between source electrode and drain electrode and not, had thickness, make thin-film transistor have preferable element characteristic between 200 dust to 800 dusts by source electrode and the semiconductor layer that drain electrode covers.In one embodiment, in the step that forms semiconductor layer, just the THICKNESS CONTROL with semiconductor layer becomes between 200 dust to 800 dusts, makes the semiconductor layer of thin-film transistor have the thickness of homogeneous in fact.In other words, the semiconductor layer that between source electrode and drain electrode and is not covered by source electrode and drain electrode with had identical thickness in fact by source electrode and the semiconductor layer that drain electrode covers, this thickness is between 200 dust to 800 dusts, and is preferably between 300 dust to 400 dusts.In another embodiment; After forming source electrode and draining; By removing the part semiconductor layer that is not covered, make do not had thickness, and be preferably between 300 dust to 400 dusts between 200 dust to 800 dusts by source electrode and the part semiconductor layer that drain electrode covers by source electrode and drain electrode.Thus, make thin-film transistor have preferable element characteristic.
Special one what carry is that the formation method of thin-film transistor of the present invention can combine with existing amorphous silicon film transistor technology, to produce top grid type polycrystalline SiTFT.Wherein, for example be amorphous silicon layer to be transformed into polysilicon layer, and use and to form the patterning doping semiconductor layer, make the technology of thin-film transistor need not use the doping board such as depositional modes such as chemical vapour deposition techniques with crystallisations such as solid-phase crystallization methods.Therefore, thin-film transistor of the present invention and forming method thereof can make thin-film transistor have preferable element characteristic and meet the requirement of large tracts of land production, can be applied to the thin-film transistor in the large size panel to make, and then promotes the display quality of panel.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (21)
1. a thin-film transistor is characterized in that, comprising:
One substrate;
Semi-conductor layer is disposed on this substrate;
One patterning doping semiconductor layer is disposed at above the relative both sides of this semiconductor layer;
An one source pole and a drain electrode; Be disposed on this patterning doping semiconductor layer and be positioned at the top, relative both sides of this semiconductor layer; Wherein had one first thickness by this semiconductor layer of part of this source electrode and this drain electrode covering; And between this source electrode and this drain electrode and not, being had one second thickness by this semiconductor layer of part of this source electrode and this drain electrode covering, this second thickness is between 200 dust to 800 dusts;
One gate insulation layer is disposed on this source electrode and this drain electrode and this semiconductor layer of part; And
One grid is disposed on this gate insulation layer.
2. thin-film transistor according to claim 1 is characterized in that, this second thickness is between 300 dust to 400 dusts.
3. thin-film transistor according to claim 1 is characterized in that this semiconductor layer comprises a polysilicon layer.
4. thin-film transistor according to claim 1 is characterized in that, this patterning doping semiconductor layer comprises a N type doped amorphous silicon layer.
5. thin-film transistor according to claim 1; It is characterized in that; This patterning doping semiconductor layer comprises one first doping semiconductor layer and one second doping semiconductor layer; This first doping semiconductor layer is between this semiconductor layer and this source electrode and coat one first side surface of this semiconductor layer; This second doping semiconductor layer is between this semiconductor layer and this drain electrode and coat one second side surface of this semiconductor layer, and wherein this first side surface and this second side surface are positioned at the relative both sides of this semiconductor layer.
6. thin-film transistor according to claim 5 is characterized in that, aligns with the inside edge of this source electrode in the inside edge of this first doping semiconductor layer, and aligns with the inside edge of this drain electrode in the inside edge of this second doping semiconductor layer.
7. thin-film transistor according to claim 6 is characterized in that, the outer ledge of this first doping semiconductor layer aligns with the outer ledge of this source electrode, and the outer ledge of this second doping semiconductor layer aligns with the outer ledge of this drain electrode.
8. thin-film transistor according to claim 1 is characterized in that, this first thickness is greater than this second thickness.
9. thin-film transistor according to claim 1 is characterized in that, this first thickness equals this second thickness.
10. a method of manufacturing thin film transistor is characterized in that, comprising:
On a substrate, form semi-conductor layer, this semiconductor layer has one first thickness;
On this semiconductor layer, form a patterning doping semiconductor layer;
On this patterning doping semiconductor layer, form an one source pole and a drain electrode; This source electrode and this drain electrode are positioned at the top, relative both sides of this semiconductor layer; Wherein between this source electrode and this drain electrode and not, had one second thickness by this semiconductor layer of this source electrode and this drain electrode covering, this second thickness is between 200 dust to 800 dusts;
Go up formation one gate insulation layer in this source electrode and this drain electrode, to cover this source electrode and this drain electrode and this semiconductor layer of part; And
On this gate insulation layer, form a grid.
11. method of manufacturing thin film transistor according to claim 10 is characterized in that, this second thickness is between 300 dust to 400 dusts.
12. method of manufacturing thin film transistor according to claim 10 is characterized in that, this first thickness is greater than this second thickness.
13. method of manufacturing thin film transistor according to claim 10 is characterized in that, this patterning doping semiconductor layer comprises N type admixture.
14. method of manufacturing thin film transistor according to claim 10 is characterized in that, the formation method of this patterning doping semiconductor layer comprises sedimentation.
15. method of manufacturing thin film transistor according to claim 14 is characterized in that, the formation method of this patterning doping semiconductor layer comprises chemical vapour deposition technique.
16. method of manufacturing thin film transistor according to claim 10 is characterized in that, the formation method of this patterning doping semiconductor layer comprises:
On this semiconductor layer, form the semiconductor material layer;
Carry out a doping process, this semiconductor material layer is transformed into a doped semiconductor material layer; And
Remove this doped semiconductor material layer of part, form this patterning doping semiconductor layer with top, relative both sides in this semiconductor layer.
17. method of manufacturing thin film transistor according to claim 10 is characterized in that, the formation method of this patterning doping semiconductor layer and the formation method of this source electrode and this drain electrode comprise:
On this semiconductor layer, form a doped semiconductor material layer and a conductor layer in regular turn;
On this conductor layer, form a patterned mask layer; And
With this patterned mask layer is mask; Remove this conductor layer of part and this doped semiconductor material layer of part; Forming this source electrode and this drain electrode and this patterning doping semiconductor layer, and do not make this semiconductor layer that is covered by this source electrode and this drain electrode have this second thickness.
18. method of manufacturing thin film transistor according to claim 17; It is characterized in that; After removing this conductor layer of part and this doped semiconductor material layer of part, more comprise removing, make this first thickness greater than this second thickness not by this semiconductor layer of part of this source electrode and this drain electrode covering.
19. method of manufacturing thin film transistor according to claim 10 is characterized in that, the formation method of this semiconductor layer comprises:
On this substrate, form an amorphous silicon layer; And
This amorphous silicon layer is transformed into a polysilicon layer.
20. method of manufacturing thin film transistor according to claim 19 is characterized in that, the method that this amorphous silicon layer is transformed into this polysilicon layer comprises the solid-phase crystallization method.
21. method of manufacturing thin film transistor according to claim 10 is characterized in that, this first thickness equals this second thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010533970XA CN102054874B (en) | 2010-11-01 | 2010-11-01 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010533970XA CN102054874B (en) | 2010-11-01 | 2010-11-01 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102054874A CN102054874A (en) | 2011-05-11 |
| CN102054874B true CN102054874B (en) | 2012-01-04 |
Family
ID=43959029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010533970XA Active CN102054874B (en) | 2010-11-01 | 2010-11-01 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102054874B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700706B (en) * | 2013-12-16 | 2015-02-18 | 京东方科技集团股份有限公司 | Preparation method of thin film transistor and array substrate |
| CN107093633B (en) * | 2017-04-21 | 2020-04-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN108091572A (en) * | 2017-12-14 | 2018-05-29 | 深圳市华星光电技术有限公司 | The production method and thin film transistor (TFT) of thin film transistor (TFT) |
| KR20200050266A (en) * | 2018-11-01 | 2020-05-11 | 엘지디스플레이 주식회사 | Panel, electronic device and transistor |
| CN110349974A (en) * | 2019-06-25 | 2019-10-18 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof, display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3636641B2 (en) * | 1999-08-20 | 2005-04-06 | セイコーエプソン株式会社 | Electro-optic device |
| KR100643038B1 (en) * | 2000-08-31 | 2006-11-10 | 엘지.필립스 엘시디 주식회사 | optical sensor array panel |
| JP4957942B2 (en) * | 2005-08-05 | 2012-06-20 | Ｎｌｔテクノロジー株式会社 | Manufacturing method of semiconductor device provided with thin film transistor |
| US7557498B2 (en) * | 2006-05-17 | 2009-07-07 | Tpo Displays Corp. | System for displaying images including electroluminescent device and method for fabricating the same |
-
2010
- 2010-11-01 CN CN201010533970XA patent/CN102054874B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102054874A (en) | 2011-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105390451B (en) | The preparation method of low temperature polycrystalline silicon TFT substrate | |
| CN101369604B (en) | Semiconductor device and manufacturing method thereof | |
| CN102664194B (en) | Thin-film transistor | |
| CN103824780B (en) | A kind of low temperature polycrystalline silicon TFT device and manufacture method thereof | |
| CN102054874B (en) | Thin film transistor and manufacturing method thereof | |
| CN103314431A (en) | Method of making oxide thin film transistor array, and device incorporating the same | |
| CN105470195B (en) | The production method of TFT substrate | |
| WO2020062483A1 (en) | Thin film transistor array substrate, fabrication method therefor and display panel | |
| CN104900712A (en) | TFT substrate structure manufacturing method and TFT substrate structure thereof | |
| CN102157562A (en) | Method for manufacturing bottom gate metal oxide thin film transistor | |
| KR20120127318A (en) | Thin Film Transistor having polysilicon active layer, method of manufacturing thereof and array substrate | |
| WO2015188476A1 (en) | Thin film transistor and manufacturing method therefor, oled back panel and display device | |
| CN101330106A (en) | Thin-film transistor substrate and thin-film transistor for display panel as well as preparation method thereof | |
| CN104505372A (en) | Manufacturing method of metal oxide thin film transistor array substrate | |
| US6432804B1 (en) | Sputtered silicon target for fabrication of polysilicon thin film transistors | |
| US20090224250A1 (en) | Top Gate Thin Film Transistor with Enhanced Off Current Suppression | |
| CN105552035A (en) | Manufacturing method for low-temperature poly-silicon TFT (thin film transistor) array substrate and structure thereof | |
| CN102810558B (en) | Thin film transistor, array substrate and preparation methods of thin film transistor and array substrate, and liquid crystal display | |
| US20170133512A1 (en) | Polycrystalline silicon thin-film transistor and method for manufacturing the same and display device | |
| CN102738081A (en) | Method for preparing ARRAY plate of thin film transistor (TFT) liquid crystal display | |
| CN106169485B (en) | Tft array substrate and preparation method thereof, display device | |
| US7678623B2 (en) | Staggered source/drain and thin-channel TFT structure and fabrication method thereof | |
| CN105514122A (en) | TFT array substrate and manufacturing method thereof | |
| CN107910378A (en) | LTPS thin film transistor (TFT)s, array base palte and preparation method thereof, display device | |
| CN105185838A (en) | Thin film transistor and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |