CN1349255A - Automatic alignment method of bit line contacting window and node conducting window - Google Patents
Automatic alignment method of bit line contacting window and node conducting window Download PDFInfo
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- CN1349255A CN1349255A CN00131448.3A CN00131448A CN1349255A CN 1349255 A CN1349255 A CN 1349255A CN 00131448 A CN00131448 A CN 00131448A CN 1349255 A CN1349255 A CN 1349255A
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- 238000000034 method Methods 0.000 title claims description 43
- 230000002093 peripheral effect Effects 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 42
- 238000004519 manufacturing process Methods 0.000 claims description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The main characteristics are as follows: the first is to change step etching interval wall of peripheral MOS being before the step inpouring ions to its source/ drain area, photic slushing layer is used by both of them as mask, the second is to form contact window slots of autoregistration bit line (node) and peripheral grid above peripheral MOS grid, the third is to change step etching interval wall of storage unit MOS being after autoregistration bit line (node) contact window slot is formed and to etch through top of peripheral MOS grid and lid layer exposed by contact window slot of peripheral grid at same time.
Description
The present invention relates to the manufacture method of a kind of memory (Memory), and particularly relate to a kind of manufacture method of aiming at (Self-aligned) bit line contacting window (Bit line Contact) and node contact hole (Node Contact) voluntarily.
In existing semiconductor making method, aim at contact hole (Self-aligned Contact voluntarily; SAC) manufacture method is commonly used to increase the aligning nargin (Alignment Margin) of contact hole.It is as follows to aim at the contact hole step of manufacturing voluntarily: at first, forming the top has metal-oxide semiconductor (MOS) (MOS) grid (Gate) of a cap layer (Cap Layer), and the sidewall (Sidewalls) in grid and cap layer forms clearance wall (Spacer) then.Next deposition one dielectric layer (Dielectric Layer) in substrate carries out a photoetching corrosion manufacture method (Lithography ﹠amp again; Etching Process), in the dielectric layer of grid both sides, to lose the voluntarily aligning contact window of width, can come out with the source/drain regions (S/D) of guaranteeing this metal-oxide-semiconductor (MOS) greater than gate pitch.In this etching process, because there are cap layer and clearance wall protection in the grid top with side, so grid can not come out.This emphasis of aiming at the contact hole manufacture method voluntarily promptly is: because it is very big to aim at the width of contact window voluntarily, even so be positioned with under the situation of obvious errors, the contact hole of follow-up formation also can touch source/drain regions, that is represents that this aligning nargin of aiming at the contact hole manufacture method voluntarily is bigger.
In the manufacture method of memory, the contact hole of aligning voluntarily of the source/drain regions required formation in top in the metal-oxide-semiconductor (MOS) of memory cell is respectively " aiming at bit line contacting window (Self-aligned Bit-lineContact) voluntarily " and " aiming at node contact hole (Self-aligned Node Contact) voluntarily ".In addition, the grid of some peripheral metal-oxide-semiconductor (MOS) (Periphery MOS) top need form the periphery gates contact hole (Periphery Gate Contact) that is electrically connected this grid, to control the switch of these peripheral MOS in the memory.The manufacture method of aiming at contact hole and periphery gates contact hole voluntarily of existing memory outlines as follows.
Please refer to Figure 1A, substrate 100 at first is provided, memory cell MOS 120 and peripheral MOS active area 110 have been formed with in this substrate 100, be formed with the cap layer 133a of the silicon nitride material of the peripheral mos gate utmost point 130a of gate dielectric layer 122, gate dielectric layer 122 tops, peripheral mos gate utmost point 130a top on the wherein peripheral MOS active area 110, and the low-doped drain (LDD) 150 in the peripheral mos gate utmost point 130a substrate on two sides 100.The cap layer 133b of silicon nitride material that comprises memory cell mos gate utmost point 130b, the memory cell mos gate utmost point 130b top of gate dielectric layer 122, gate dielectric layer 122 tops among the memory cell MOS 120, and the cell source/drain region 154 in the memory cell mos gate utmost point 130b substrate on two sides 100, and isolate with separator 102.Then form conformal lining oxide layer 142 and silicon nitride layer (not shown) in substrate 100 in regular turn, wherein the function of lining oxide layer 142 is for reducing the stress of silicon nitride layer.Follow anisotropically this silicon nitride layer of etching, form clearance wall 143a with the sidewall in peripheral mos gate utmost point 130a and cap layer 133a, the sidewall in memory cell mos gate utmost point 130b and cap layer 133b forms clearance wall 143b simultaneously.What should be specified is herein, only represents the NMOS active area in the peripheral circuit and the processing procedure of PMOS active area with the processing procedure of peripheral MOS 110 active areas in this manual, so that its description also is succinct.
Please refer to Figure 1B, then carry out Twi-lithography manufacture craft (respectively at NMOS active area in the peripheral circuit and PMOS active area), on memory cell MOS 120, to cover photoresist layer 158.Because only represent NMOS active area and PMOS active area in the peripheral circuit in this specification with peripheral MOS 110 active areas, so photoresist layer 158 is represented in formed two the photoresist layers of Twi-lithography manufacture craft, be positioned at the part of memory cell MOS 120 tops.Be mask with photoresist layer 158, cap layer 133a and clearance wall 143a then, inject ion 159,, and finished peripheral MOS 110a with the peripheral source/drain regions 160 of formation in clearance wall 143a substrate on two sides 100.Because only represent NMOS active area and PMOS active area in the peripheral circuit in this specification with peripheral MOS 110 active areas, after so clearance wall 143a etching herein and ion 159 implantation steps are also represented each time photoetching making technology, spacer etch and ion implantation step that peripheral NMOS active area (PMOS active area) is carried out.
Please refer to Fig. 1 C, follow capping oxidation silicon layer 170 in substrate 100, carry out the 3rd a photoetching making technology and a corrosion manufacture craft again, aim at bit line contacting window opening 175 voluntarily in silicon oxide layer 170, to form, to aim at node contact window 176 and periphery gates contact window 177 voluntarily, and to remove the lining oxide layer 142 that exposes in passing.This aims at bit line contacting window opening 175 voluntarily and aims at node contact window 176 voluntarily and expose cell source/drain region 154, and its width is greater than the spacing of memory cell mos gate utmost point 130b; 177 of periphery gates contact windows expose the cap layer 133a of peripheral MOS 110a.
Please refer to Fig. 1 D, then carry out the 4th photoetching making technology,, protect cap layer 133b and the clearance wall 143b of memory cell MOS 120 by this on memory cell MOS 120, to cover photoresist layer 180.Carry out a silicon nitride etch step then,, and expose this peripheral mos gate utmost point 130a, make the peripheral mos gate utmost point 130a contact hole that forms to be connected with follow-up with the cap layer 133a of eating thrown periphery mos gate utmost point 130a top.
By foregoing with the diagram as can be known, aim at voluntarily in contact hole and the periphery gates contact hole manufacture method in existing memory, after the low-doped drain (LDD) 150 of cell source/drain region 154 and peripheral MOS 110a forms, up to finishing each contact window (175,176 ， ﹠amp; 177) till, need photoetching making technology altogether four times, need twice when wherein (1) forms peripheral source/drain regions 160; Needs once when (2) forming periphery gates contact window 177 and aiming at bit line (node) contact window 175 (176) voluntarily; (3) also need once during the cap layer 133a of eating thrown periphery MOS 110a.Because the step of photoetching making technology is a lot, so existing manufacture method comparatively bothers.Moreover, owing to form when aiming at bit line (node) contact window 175 (176) voluntarily in etching, the cap layer 133b of silicon nitride material also can lose much, so cap layer 133b must have suitable thickness, and usually causes the excessive problem of stress (Stress).
The objective of the invention is to propose a kind of bit line contacting window and node contact hole manufacture method of aiming at voluntarily, it only needs the third photo etching manufacture craft can form peripheral MOS source/drain regions, periphery gates contact window and aims at bit line (node) contact window voluntarily, and the cap layer of eating thrown periphery mos gate utmost point top.
For achieving the above object, of the present inventionly a kind ofly aim at bit line contacting window voluntarily and node contact hole step of manufacturing is as follows: at first provide a substrate, a peripheral MOS active area and a memory cell MOS have been formed with in this substrate, be formed with first cap layer of first grid and its top on the wherein peripheral MOS active area, and second cap layer that comprises second grid, second grid top among the memory cell MOS, and the cell source/drain region in the substrate of second grid both sides.
Continuous epimere then forms a conformal insulating barrier in substrate, this insulating barrier is identical with the material of first cap layer and second cap layer.Going up in memory cell MOS then and cover a photoresist layer, is mask with this photoresist layer again, and anisotropically the insulating barrier of etching periphery MOS active area top forms first clearance wall with the sidewall in the first grid and first cap layer.Next be that mask carries out the ion implantation step with this photoresist layer, first clearance wall and first cap layer,, and finish a peripheral MOS with formation one peripheral source/drain regions in the first clearance wall substrate on two sides.Then remove the photoresist layer, deposit a dielectric layer again in substrate, formation one is aimed at the bit line contacting window opening voluntarily and is aimed at the node contact window voluntarily with one in the dielectric layer of two of second grids then, and exposes partial insulating layer; In the dielectric layer of first grid top, form a periphery gates contact window simultaneously, and expose first cap layer.Insulating barrier during reserve anisotropy ground etching is aimed at the bit line contacting window opening voluntarily and aimed at the node contact window voluntarily forms second clearance wall with the sidewall in the second grid and second cap layer; First cap layer in the while eating thrown periphery gates contact window, and expose first grid.
In the invention described above, the material of dielectric layer for example is a silica, and this manufacture method also can comprise and be in the substrate to form before the insulating barrier, prior to forming the step of a conformal lining oxide layer in the substrate, and after second clearance wall forms, follow the lining oxide layer that etching off exposes.In addition, above-mentioned peripheral MOS active area former also comprises a low-doped drain (LDD), and it is to be arranged in the first grid substrate on two sides.In addition, above-mentioned periphery gates contact window for example is a peripheral bit line contacting window opening (Periphery Bit-line Contact).
As mentioned above; aim at voluntarily in bit line contacting window and the node contact hole manufacture method of the present invention; the spacer etch step of memory cell MOS is delayed; and merge with the cap layer eating thrown step of peripheral MOS; so needn't use the 4th photoetching making technology to protect the zone of memory cell MOS, that is to say that required photoetching making technology number of times can be kept to three times.Moreover; because when the present invention aims at bit line (node) contact hole voluntarily in etching formation; the grid top of memory cell MOS is except having the protection of first cap layer; first cap layer top still has insulating barrier to can be used as protection; so the required thickness of this first cap layer can reduce, and is reduced stress.The present invention also has a special character, and the spacer etch of peripheral exactly MOS and the shared same photoresist layer of the source/drain regions ion implantation step of itself are mask, can't increase the number of times of photoetching making technology.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Figure 1A-1D illustrate is the existing flow process profile of bit line contacting window and node contact hole manufacture method of aiming at voluntarily; And
Fig. 2 A-2D illustrate is the flow process profile of aiming at bit line contacting window and node contact hole manufacture method voluntarily of the preferred embodiment of the present invention.
The label declaration of accompanying drawing:
100,200: substrate
102,202: separator (Isolation)
110,210: peripheral MOS active area (Periphery MOS Active Region)
110a, 210a: peripheral MOS
120,220: memory cell (Memory Cell) MOS
122,222: gate dielectric layer (Gate Dielectric)
130a, 230a: the peripheral mos gate utmost point
130b, 230b: the memory cell mos gate utmost point
133a, 133b, 233a, 233b: cap layer (Cap Layer)
142,242: lining oxide layer (Liner Oxide)
143a, 143b, 243a, 243b: clearance wall (Spacer)
150,250: low-doped drain (LDD)
154,254: cell source/drain region
158,180,258,280: photoresist layer (Photoresist Layer)
159,259: ion (Ion)
160,260: peripheral source/drain regions
170,270: silicon oxide layer, dielectric layer (Dielectric Layer)
175,275: aim at bit line contacting window opening (Self-aligned Bit-1ine Contact voluntarily
Opening)
176,276: aim at node contact window (Self-aligned Node Contact voluntarily
Opening)
177,277: periphery gates contact window (Periphery Gate Contact Opening)
Please refer to Fig. 2 A, substrate 200 at first is provided, peripheral MOS active area 210 and memory cell MOS 220 have been formed with in this substrate 200, be formed with the cap layer 233a of the peripheral mos gate utmost point 230a of gate dielectric layer 222, gate dielectric layer 222 tops, peripheral mos gate utmost point 230a top on the wherein peripheral MOS active area 210, and the low-doped drain (LDD) 250 in the peripheral mos gate utmost point 230a substrate on two sides 200.Memory cell MOS 220 comprises the cap layer 233b of memory cell mos gate utmost point 230b, the memory cell mos gate utmost point 230b top of gate dielectric layer 222, gate dielectric layer 222 tops, and the cell source/drain region 254 in the memory cell mos gate utmost point 230b substrate on two sides 200.What should be specified is herein, only represents the NMOS active area in the peripheral circuit and the processing procedure of PMOS active area with the processing procedure of a peripheral MOS active area 210 in this specification, so that its description is more succinct.
Please continue the A with reference to Fig. 2, then form conformal lining oxide layer 242 and insulating barrier 243 in regular turn in substrate 200, wherein insulating barrier 243 is as the predecessor of clearance wall, and lining oxide layer 242 is used for the stress of reduced insulation layer 243.This insulating barrier 243 is identical with the material of cap layer 233a (b), and the three all for example is a silicon nitride layer, and the thickness of the insulating barrier 243 of silicon nitride material between 500 between 1000 .
Please refer to Fig. 2 B, next carry out Twi-lithography manufacture craft (respectively at NMOS active area and PMOS active area), on memory cell MOS 220, to cover photoresist layer 258.Owing to only represent NMOS active area and PMOS active area in the peripheral circuit in this specification with a peripheral MOS active area 210, so this photoresist layer 258 is represented in formed two the photoresist layers of Twi-lithography manufacture craft, be positioned at the part of memory cell MOS 220 tops.Be mask with photoresist layer 258 then, anisotropically the insulating barrier 243 of etching periphery MOS active area 210 tops forms clearance wall 243a with the sidewall in peripheral mos gate utmost point 230a and cap layer 233a.Be that mask carries out the ion injection with photoresist layer 258, cap layer 233a and clearance wall 243a then,, and finish peripheral MOS 210a with the peripheral source/drain regions 260 of formation in clearance wall 243a substrate on two sides 200.Owing to only represent NMOS active area and PMOS active area in the peripheral circuit in this specification with a peripheral MOS active area 210, after so clearance wall 243a etching herein and ion 259 implantation steps are also represented each time photoetching making technology, spacer etch and ion implantation step that peripheral NMOS active area (PMOS active area) is carried out.
Please refer to Fig. 2 C, follow dielectric layer 270 in substrate 200, its material for example is a silica, carries out photoetching making technology for the third time again, to form the photoresist layer 280 of patterning on dielectric layer 270.Be mask etching dielectric layer 270 then with photoresist layer 280, with formation " aiming at bit line contacting window opening 275 voluntarily " and " aiming at node contact window 276 voluntarily " in the dielectric layer 270 of memory cell mos gate utmost point 230b both sides, and expose partial insulating layer 243.Simultaneously, in the dielectric layer 270 of peripheral mos gate utmost point 230a top, form periphery gates contact window 277, and exposing cap layer 233a altogether, this periphery gates contact window 277 for example is a peripheral bit line contacting window opening (Periphery Bit-line Contact).
Please refer to Fig. 2 D, be mask then with photoresist layer 280, insulating barrier 243 during anisotropically etching is aimed at bit line contacting window opening 275 voluntarily and aimed at node contact window 276 voluntarily forms clearance wall 243b with the sidewall in memory cell mos gate utmost point 230b and cap layer 233b; Cap layer 233a in the while eating thrown periphery gates contact window 277, and expose peripheral mos gate utmost point 230a, for after a while the grid contact hole that forms being connected.Carry out the silicon monoxide etching step then, the lining oxide layer 242 that etching off exposes, and expose cell source/drain region 254, for after a while the bit line contacting window that forms being connected with the node contact hole.
As mentioned above, in the bit line contacting window of aligning voluntarily and node contact hole manufacture method of the preferred embodiment of the present invention, the etching step of the clearance wall 243b of memory cell MOS 220 is delayed, and merged (Fig. 2 D) with the eating thrown step of the cap layer 233a of peripheral MOS 210a.Therefore; using to need to carry out cap layer 133b and the clearance wall 143b (Fig. 1 D) that the 4th photoetching making technology is protected memory cell MOS 120 when of the present invention as prior art; that is to say that the required photoetching making technology number of times of the preferred embodiment of the present invention can be kept to three times.Moreover; please refer to Fig. 2 C; because the preferred embodiment of the present invention forms when aiming at bit line (node) contact hole 275 (276) voluntarily in etching; memory cell mos gate utmost point 230b top is except having cap layer 233b protection; cap layer 233b top still has insulating barrier 243 to can be used as protection; so the thickness of required cap layer 233b can reduce, and is reduced stress.The present invention also has a special character, and the clearance wall 243a etching of peripheral exactly MOS 210a and peripheral source/drain regions 260 ions inject shared same photoresist layer 258 and are mask (Fig. 2 B), can't increase the number of times of photoetching making technology.
Though the present invention discloses as above in conjunction with a preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can make various changes and retouching, so protection scope of the present invention should be as the criterion with defining of accompanying Claim.
Claims (14)
1. aim at bit line contacting window and node contact hole manufacture method voluntarily for one kind, comprise the following steps:
One substrate is provided, a peripheral MOS active area and a memory cell MOS have been formed with in this substrate, be formed with one first cap layer of first grid and this first grid top on wherein should periphery MOS active area, and this memory cell MOS comprises a second grid, is positioned at one second cap layer of this second grid top, and is arranged in the one cell source/drain region of this substrate of these second grid both sides;
Form a conformal insulating barrier in this substrate, this insulating barrier, this first cap layer are all identical with the material of this second cap layer;
Go up covering one photoresist layer in this memory cell MOS;
With this photoresist layer is mask, anisotropically etching should periphery MOS active area this insulating barrier of top, form one first clearance wall with sidewall in this first grid and this first cap layer;
With this photoresist layer, this first cap layer and this first clearance wall is that mask carries out the ion implantation step, with formation one peripheral source/drain regions in this substrate of these first clearance wall both sides, and finishes a peripheral MOS;
Remove this photoresist layer;
Deposition one dielectric layer in this substrate;
Formation one is aimed at the bit line contacting window opening voluntarily and is aimed at the node contact window voluntarily with one in this dielectric layer of these second grid both sides, and expose the part this insulating barrier, form a periphery gates contact window in this dielectric layer above this first grid simultaneously, and expose this first cap layer; And
Anisotropically etching this aim at the bit line contacting window opening voluntarily and aim at this insulating barrier in the node contact window voluntarily with this, form one second clearance wall with sidewall at this second grid and this second cap layer, eating thrown is exposed to this first cap layer in this periphery gates contact window simultaneously, and exposes this first grid.
2. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 1, this manufacture method also comprises and is in this substrate to form before this insulating barrier, prior to forming the step of a conformal lining oxide layer in this substrate, and after this second clearance wall forms, follow this lining oxide layer that etching off exposes.
3. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 1, wherein this insulating barrier comprises a silicon nitride layer.
4. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 3, wherein the thickness of this silicon nitride layer between 500 between 1000 .
5. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 1, wherein the material of this dielectric layer comprises silica.
6. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 1, wherein should periphery MOS active area on the former also comprise a low-doped drain (LDD), it is arranged in this substrate of these first grid both sides.
7. bit line contacting window and the node contact hole manufacture method of aiming at voluntarily as claimed in claim 1, this periphery gates contact window is a peripheral bit line contacting window opening.
8. a contact hole manufacture method comprises the following steps:
One substrate is provided, a neighboring area and a memory cell region have been formed with in this substrate, wherein, this neighboring area forms one first cap layer of a first grid and this first grid top, and this memory cell region forms a memory cell transistor, and this transistor comprises a second grid and second cap layer that is positioned at this second grid top;
Form a conformal insulating barrier in this substrate, this insulating barrier, this first cap layer are all identical with the material of this second cap layer;
Cover a photoresist layer on this memory cell region;
With this photoresist layer is mask, forms a peripheral transistor, and wherein this peripheral transistor comprises that one first clearance wall of a grid, sidewall and a pair of peripheral source/drain regions are in this substrate of these first clearance wall both sides;
Remove this photoresist layer;
Deposition one dielectric layer in this substrate;
In this dielectric layer of these second grid both sides, form a contact window, and expose this insulating barrier of part, form a peripheral contact window simultaneously in this dielectric layer above this first grid, and expose first cap layer; And
Remove this insulating barrier of part in this contact window, with sidewall one second clearance wall that is formed at this second grid and this second cap layer, eating thrown is exposed to this first cap layer in this periphery gates contact window simultaneously, and exposes this first grid.
9. contact hole manufacture method as claimed in claim 8, this manufacture method also is included in and forms this insulating barrier before in this substrate, the step of a lining oxide layer conformal prior to formation in this substrate, and after this second clearance wall forms, follow this lining oxide layer that etching off exposes.
10. contact hole manufacture method as claimed in claim 8, wherein this insulating barrier comprises a silicon nitride layer.
11. contact hole manufacture method as claimed in claim 10, wherein the thickness of this silicon nitride layer between 500 between 1000 .
12. contact hole manufacture method as claimed in claim 8, wherein the material of this dielectric layer comprises silica.
13. contact hole manufacture method as claimed in claim 8, wherein on this neighboring area the former also comprise a low-doped drain (LDD), it is arranged in this substrate of these first grid both sides.
14. contact hole manufacture method as claimed in claim 8, this periphery gates contact window are a peripheral bit line contacting window opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001314483A CN1168134C (en) | 2000-10-16 | 2000-10-16 | Automatic alignment method of bit line contacting window and node conducting window |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001314483A CN1168134C (en) | 2000-10-16 | 2000-10-16 | Automatic alignment method of bit line contacting window and node conducting window |
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| CN1349255A true CN1349255A (en) | 2002-05-15 |
| CN1168134C CN1168134C (en) | 2004-09-22 |
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| CNB001314483A Expired - Lifetime CN1168134C (en) | 2000-10-16 | 2000-10-16 | Automatic alignment method of bit line contacting window and node conducting window |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303651C (en) * | 2003-07-16 | 2007-03-07 | 旺宏电子股份有限公司 | Method for forming self alignment contact window |
| CN101165875A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Semiconductor device and method for forming thereof |
| CN100421218C (en) * | 2005-04-18 | 2008-09-24 | 力晶半导体股份有限公司 | Semiconductor with self-aligning contact window and its production |
| CN101593753B (en) * | 2008-05-30 | 2011-09-28 | 和舰科技(苏州)有限公司 | Nonvolatile memory and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136455A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing complementary metallic oxide semiconductor device |
| EP4181202A4 (en) | 2020-09-29 | 2023-12-27 | Changxin Memory Technologies, Inc. | Semiconductor device and preparation method therefor |
-
2000
- 2000-10-16 CN CNB001314483A patent/CN1168134C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1303651C (en) * | 2003-07-16 | 2007-03-07 | 旺宏电子股份有限公司 | Method for forming self alignment contact window |
| CN100421218C (en) * | 2005-04-18 | 2008-09-24 | 力晶半导体股份有限公司 | Semiconductor with self-aligning contact window and its production |
| CN101165875A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Semiconductor device and method for forming thereof |
| CN101593753B (en) * | 2008-05-30 | 2011-09-28 | 和舰科技(苏州)有限公司 | Nonvolatile memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1168134C (en) | 2004-09-22 |
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