KR100347537B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and deteriorates the characteristics of the device due to misalignment during the attack and self-aligned source (SAS) etching processes of the anti-reflection film generated in the cell region of the flash memory device. By using the gate mask, the cell source mask, and the cell drain mask to form the gate, the cell source region, and the cell drain region of the peripheral circuit region, respectively, to prevent the Disclosed is a method of manufacturing a flash memory device capable of preventing an attack on a drain region.

Description

Method of manufacturing a flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device. In particular, the characteristics of the device due to misalignment during the attack and self-aligned source (SAS) etching processes of the anti-reflection film generated in the cell region of the flash memory device A method of manufacturing a flash memory device for preventing deterioration.

Flash memory devices use the Hot Carrier Injection and FN tunneling to electrically write and erase data by storing or erasing charges in floating gates. It is divided into cells. The stack gate cell is formed of a floating gate and a control gate. The floating gate serves to store data in the cell, and the control gate determines read, write and erase operations of the cell by controlling the potential of the floating gate through the dielectric layer. Play a role.

The source region of the flash memory cell is formed through a Self Aligned Sour (SAS) etching process. In this case, the misalignment degree is different for each region, and in extreme cases, an attack is applied to the drain region. There is a possibility.

1A and 1B are layout views of devices in a self-aligned source process of a flash memory device.

FIG. 1A illustrates a state in which the self-aligned source mask 12 is normally formed without misalignment during the self-aligned source etching process. The drain line D is not attacked and the common source line S is disposed between the gate lines G. FIG. Indicates that it was formed. Reference numeral 11 denotes a field oxide film, and reference numeral 13 denotes a portion where a minimum field oxide film 11 is removed to form a source line SL during self-aligned source etching.

FIG. 1B illustrates a state in which the self-aligned source mask 12 is misaligned and the drain line D is attacked during the self-aligned source etching process. As the self-aligned source mask 12 is misaligned as described above, the field oxide film is removed from the drain D portion where the misalignment has occurred (14 portions), and the neighboring drains are short-circuited.

A manufacturing process of a general flash memory device will be described below.

After the device isolation process, a tunnel oxide film and a first polysilicon layer (for floating gate) are formed on the substrate, and the first polysilicon layer is first etched. Thereafter, the dielectric film, the second polysilicon layer (for the control gate) and the antireflection film are sequentially formed, and then the antireflection film, the second polysilicon layer and the dielectric film are etched to form a control gate, and then a self-aligned etching process is performed. To form a floating gate. Next, source and drain regions are formed, and a source line is formed by performing a self-aligned source etching process. However, since the cell regions are all open during the etching process using the self-aligned etching mask, the anti-reflection film serving as a hard mask must be attacked, and the tungsten silicide layer, which is the lower layer of the anti-reflection film, is damaged.

Therefore, after the cell is formed by the self-aligned etching process, the anti-reflection film is attacked along the gate line of the cell region. In particular, the vicinity of the source tab where the source contact is to be formed is more severe. This attack also tends to deepen as the gate length decreases.

As described above, in the related art, the cell drain region is attacked according to the degree of misalignment generated during the self-aligned source mask operation, and a phenomenon occurs in which the drain region to be insulated for each cell is shorted. As a result, the device characteristics are fatal. In addition, due to the attack of the anti-reflection film generated after the cell self-alignment etching process, even a tungsten silicide layer used as a gate of the cell during subsequent self-alignment source etching is attacked, thereby degrading the reliability of the cell.

Accordingly, the present invention improves the reliability of the device by preventing attack from being applied to the anti-reflection film and the drain formed on the top of the gate by using a mask according to the purpose of each process when forming the gate, source and drain of the flash memory device. It is an object of the present invention to provide a method of manufacturing a flash memory device.

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method including: defining an active region by forming a field oxide film in a cell region and a peripheral circuit region of a semiconductor substrate; Forming a tunnel oxide layer and a first polysilicon layer pattern in an active region of the cell region, and then forming a dielectric layer, and forming a gate oxide layer in an active region of the peripheral circuit region; Forming a second polysilicon layer, a tungsten silicide layer and an antireflection film on the entire structure including the dielectric film and the gate oxide film; Forming a gate in the peripheral circuit area using a gate mask; Etching a portion of the field oxide layer to be exposed using a cell source mask, and then forming a source line by source ion implantation; And etching a portion of the tunnel oxide film exposed using a cell drain mask to form a drain isolated by the field oxide film by drain ion implantation, and forming a floating gate by the cell source mask and the cell drain mask process. And forming a control gate.

1A and 1B are layout views of a device in a self-aligned source process of a flash memory device.

2A to 2D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

101 semiconductor substrate 102 tunnel oxide film

103: gate oxide film 104: first polysilicon layer

105: dielectric film 106: second polysilicon layer

107: tungsten silicide layer 108: antireflection film

109: first photoresist pattern 110: second photoresist pattern

111: third photoresist pattern

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2A to 2D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to the present invention.

Referring to FIG. 2A, a field oxide film is formed in a cell region and a peripheral circuit region of the semiconductor substrate 101 to define an active region, and the tunnel oxide layer 102 and the first polysilicon layer are formed in the active region of the cell region C. A pattern and a dielectric film 105 are formed, and a gate oxide film 103 is formed in the active region of the peripheral circuit region P. Next, the second polysilicon layer 106, the tungsten silicide layer 107, and the antireflection film 108 are sequentially formed on the entire structure including the dielectric film 105 and the gate oxide film 103. In this state, the anti-reflection film 108, the tungsten silicide layer 108, the second polysilicon layer 106 and the gate oxide film in the peripheral circuit region P are formed using the first photoresist pattern 109 using the gate mask. The 103 is sequentially etched to form a gate of the transistor.

Referring to FIG. 2B, the first photoresist pattern 109 is removed, the second photoresist pattern 110 using the cell source mask is etched and the source oxide film (not shown) is etched to the exposed portion and the source ions are exposed. Injection forms source lines. The source ion implantation process may be performed after defining a source line formation region using a cell source mask and then completing formation of a floating gate and a control gate. At this time, the active region is controlled so that no substrate loss occurs. As such, when the cell source mask is used instead of the existing self-aligned source mask, the source line is not misaligned because only a portion of the cell source is opened correctly.

Referring to FIG. 2C, the second photoresist pattern 110 is removed, the third photoresist pattern 111 using the cell drain mask is etched to the exposed portion of the tunnel oxide layer, and the cell drain is drained. Form an area. The drain ion implantation may be performed after defining the drain formation region using the cell drain mask and after completion of the formation of the floating gate and the control gate. Accordingly, both the control gate and the floating gate of the cell region C are completed to form the stack gate.

FIG. 2D illustrates a state in which the manufacture of the flash memory device is completed by removing the third photoresist pattern 111 and performing a subsequent process such as source ion implantation to form a source line.

It is also possible to reverse the order of each process step using the gate mask, cell source mask and cell drain mask described above.

As described above, in the present invention, the gate, source and drain regions are formed using the gate mask, the cell source mask, and the cell drain mask, respectively, so that a reliable flash memory device can be manufactured without adding a mask process step.

As described above, the present invention uses the gate mask, the cell source mask, and the cell drain mask to form the gate, the cell source region, and the cell drain region of the peripheral circuit region, respectively, so that the reflection formed on the top of the cell during the self-aligned etching process. It is possible to prevent the attack of the barrier layer and the drain region of the cell. In addition, since the cell source region and the drain region are opened in separate processes, ion implantation conditions suitable for the characteristics of each junction region can be optimized. Accordingly, the operating characteristics of the device can be stabilized, and the reliability and yield of the device can be improved.

Claims (4)

Forming a field oxide film in a cell region and a peripheral circuit region of the semiconductor substrate to define an active region; Forming a tunnel oxide layer and a first polysilicon layer pattern in an active region of the cell region, and then forming a dielectric layer, and forming a gate oxide layer in an active region of the peripheral circuit region; Forming a second polysilicon layer, a tungsten silicide layer and an antireflection film on the entire structure including the dielectric film and the gate oxide film; Forming a gate in the peripheral circuit area using a gate mask; Etching a portion of the field oxide layer to be exposed using a cell source mask, and then forming a source line by source ion implantation; And After etching to the portion where the tunnel oxide film is exposed using a cell drain mask, a drain is implanted to form a drain isolated by the field oxide film, and the floating gate and the control are performed by the cell source mask and the cell drain mask process. A method of manufacturing a flash memory device comprising the step of forming a gate. The method of claim 1, And forming a source line by etching and drain ion implantation using the cell drain mask and then forming a source line by etching and source ion implantation using the cell source mask. Forming a field oxide film in a cell region and a peripheral circuit region of the semiconductor substrate to define an active region; Forming a tunnel oxide layer and a first polysilicon layer pattern in an active region of the cell region, and then forming a dielectric layer, and forming a gate oxide layer in an active region of the peripheral circuit region; Forming a second polysilicon layer, a tungsten silicide layer and an antireflection film on the entire structure including the dielectric film and the gate oxide film; Forming a gate in the peripheral circuit area using a gate mask; Etching to the exposed portion of the field oxide layer using a cell source mask, thereby defining a source line forming region; The cell drain mask is etched to the exposed portion of the tunnel oxide layer, thereby defining a drain formation region isolated by the field oxide layer, and the floating gate and the control gate are formed by the cell source mask and the drain mask process. Forming; And A method of manufacturing a flash memory device comprising forming a source line and a drain by a cell source / drain ion implantation process. The method of claim 3, wherein And defining a drain formation region by an etching process using the cell drain mask, and then defining a source line forming region by an etching process using the cell source mask.