CN1303651C - Method for forming self alignment contact window - Google Patents
Method for forming self alignment contact window Download PDFInfo
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- CN1303651C CN1303651C CNB03147683XA CN03147683A CN1303651C CN 1303651 C CN1303651 C CN 1303651C CN B03147683X A CNB03147683X A CN B03147683XA CN 03147683 A CN03147683 A CN 03147683A CN 1303651 C CN1303651 C CN 1303651C
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Abstract
The present invention provides a method for forming a self-alignment contact window, which comprises at least a grid-superposed structure arranged on a semiconductor substrate, a first dielectric layer formed on the semiconductor substrate and the grid-superposed structure, and a second dielectric layer formed on the first dielectric layer, wherein the second dielectric layer has the selectivity of etching corresponding to the first dielectric layer. The second dielectric layer is etched to expose the first dielectric layer formed on a top surface of the grid-superposed structure and at the upper part of partial side wall of the grid-superposed structure. The first dielectric layer exposed is removed, and a third dielectric layer is formed on the side wall of the grid-superposed structure.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly the self-aligned contacts window shape becomes method in the semiconductor integrated circuit.
Background technology
Field-effect transistor (FET) generally includes: the insulating barrier that forms on Semiconductor substrate, be formed on the polysilicon gate on the insulating barrier, be formed on a pair of source/drain regions in the Semiconductor substrate, and the channel region that is formed on the gate insulator below and separates with this source/drain regions.In the field-effect transistor manufacturing process, the conventional flash memory technology comprises the metallization manufacturing process of circuit source/drain duplet.Metallization manufacturing process is included in the screen of composition is set on the Semiconductor substrate, and exposes source electrode or the drain region that is formed in the Semiconductor substrate.Particularly, pass through the screen formation opening of composition, then deposit contacting metal in opening with traditional optical lithography.Yet in deep-submicron flash memory (deep sub-micronflash) manufacturing process, because component density is higher on the Semiconductor substrate, size of components is less, the integrated circuit microminiaturization; Therefore, the opening size that forms metallic contact must be littler, so that may be difficult to aim at.For lowering the restriction of mask alignment tolerance, use self-aligned contacts (SAC) technology, realize the mask fine registration.
Fig. 1 is the profile that shows existing flash cell 10.Flash cell 10 is formed on the Semiconductor substrate 12, comprise: grid stacked structure 14, be formed on the Semiconductor substrate 12, be deposited on the gate insulator 16 on the grid stacked structure 14, be formed on source/drain in the Semiconductor substrate 12 to 18, source/drain is to 18 with channel region 20 separately, and around the side wall layer 22 of the sidewall of grid stacked structure 14.Grid stacked structure 14 can comprise: the polysilicon gate 24 that conductor mixes, refractory metal bar 28 and interlayer dielectric layer (ILD) 26 is to isolate polysilicon gate 24 and refractory metal bar 28.Flash cell 10 also comprises the identical silicon oxide layer of shape 30 usually, and it covers on gate insulator 16 and the grid stacked structure 14, with as stress-buffer layer.
Form source/drain to after 18 with the ion injection mode, form self-aligned contacts window (not indicating among the figure).The method that tradition forms the self-aligned contacts window comprises: dielectric layer 32 is set, it for example is oxide layer, it covers Semiconductor substrate 12, and etching dielectric layer 32, resilient coating 30, gate insulator 16, to expose source/drain to 18, thereby form contact openings 34, for later in deposit contacting metal (not indicating among the figure) wherein.Because dielectric layer 32 and resilient coating 30 usefulness silica are formed, make that cleaning employed etching gas or etching solution at contact hole etching or contact hole also can damage the resilient coating 30 that is positioned at 22 of grid stacked structure 14 and side wall layer, and expose metal level 28, cause metal level 28 and insert short circuit between contacting metal in the opening 34.
Summary of the invention
In view of this, the invention provides a kind of self-aligned contacts window shape and become method, address the above problem.
For achieving the above object, the purpose of this invention is to provide a kind of self-aligned contacts window shape and become method, comprising: on Semiconductor substrate, form at least one grid stacked structure; On above-mentioned Semiconductor substrate and above-mentioned grid stacked structure, form first dielectric layer; Form one second dielectric layer on said first dielectric layer, said second dielectric layer has etching selectivity with respect to said first dielectric layer; The etching said second dielectric layer is to expose the said first dielectric layer of the above-mentioned grid stacked structure of the top surface at least a portion side wall upper part that is formed on above-mentioned grid stacked structure; Remove the said first dielectric layer that has exposed to the open air; And on the sidewall of above-mentioned grid stacked structure, form the 3rd dielectric layer.
By one embodiment of the present of invention, form the first dielectric layer step and comprise: oxidation grid stacked structure and Semiconductor substrate.
According to one embodiment of present invention, also comprise first dielectric layer that shape is identical.
The present invention provides a kind of self-aligned contacts window shape to become method again, comprising: on Semiconductor substrate, form at least one grid stacked structure; Above-mentioned grid stacked structure of oxidation and above-mentioned Semiconductor substrate are to form first oxide layer; Form sacrifice layer on above-mentioned first oxide layer, above-mentioned relatively first oxide layer of above-mentioned sacrifice layer has etching selectivity; The above-mentioned sacrifice layer of etching is to expose above-mentioned first oxide layer that is positioned at above-mentioned grid stacked structure top and side wall upper part to the open air; Remove above-mentioned first oxide layer that exposes, to expose above-mentioned grid stacked structure top and side wall upper part; Along the sidewall of above-mentioned grid stacked structure, form a side wall layer on above-mentioned side wall layer and above-mentioned Semiconductor substrate; Form second oxide layer, the above-mentioned relatively sidewall of above-mentioned second oxide layer has etching selectivity; And above-mentioned first oxide layer of above-mentioned second oxide layer of etching, to expose contact zone in abutting connection with above-mentioned grid stacked structure.
According to one embodiment of present invention, wherein, this grid stacked structure of oxidation comprises with oxygen and hydrogen and carries out quick thermal treatment process.
According to another embodiment of the invention, wherein, this grid stacked structure of oxidation comprises with oxygen and hydrogen and carries out a fluid stream generating routine on the spot.
By below in conjunction with the accompanying drawing DETAILED DESCRIPTION OF THE PREFERRED, make above and other objects of the present invention, feature and the advantage can be clearer.
Description of drawings
Fig. 1 is the profile of existing flash memory device;
Fig. 2-8 becomes an embodiment profile of method for self-aligned contacts window shape of the present invention.
Symbol description
10～flash cell;
12,50～Semiconductor substrate;
14,52～grid stacked structure;
16～gate insulator;
18～source/drain is right
20～channel region;
22～side wall layer;
24～polysilicon gate;
26,58～interlayer dielectric layer;
28～refractory metal bar;
30～shape identical layer;
32～dielectric layer;
34～contact openings;
54～gate insulator;
56～the first metal layer;
60～the second metal levels;
62～the 3rd metal levels;
64～hard screen;
66～the first dielectric layers;
62～the 3rd metal levels;
64～hard screen;
66～the first dielectric layers;
68～the second dielectric layers;
70～side wall upper part;
72～top surface;
74～the 3rd dielectric layers;
76～the 4th dielectric layers;
78～contact openings
Embodiment
Fig. 2-8 shows that self-aligned contacts window shape of the present invention becomes an embodiment of method.See also Fig. 2, Semiconductor substrate 50 be provided, on Semiconductor substrate 50, form grid stacked structure 52, can be as required, this stage in Semiconductor substrate, form source/drain to and raceway groove.Grid stacked structure 52 comprise gate insulator 54, the second metal levels 60 and be formed on the first metal layer 56 and second metal level 60 between interlayer dielectric layer 58, provide two metal interlevels to be electrically insulated.In one embodiment, gate insulator 54 is formed with silica, and the first metal layer 56 comprises polysilicon, and second metal level 60 comprises the metal level of an infusibility.In another embodiment, the 3rd metal level 62 that is formed on second metal level 60 that includes polysilicon comprises tungsten silicide.The 3rd metal level 62 can be strengthened the conductivity of grid stacked structure 52.
See also Fig. 3, behind the formation grid stacked structure 52, first dielectric layer 66 is formed on grid stacked structure 52 and the Semiconductor substrate 50, and first dielectric layer 66 also can be identical for shape.In one embodiment, first dielectric layer 66 comprises silica, and it can oxygen and hydrogen carries out quick thermal treatment process (RTP) or carrying out on the spot a fluid stream with oxygen and hydrogen produces and handle (ISSG) and form.First dielectric layer 66 also can form by the deposit mode, and first dielectric layer 66 will be as the stress-buffer layer of the side wall layer that forms backward.
See also Fig. 4, on first dielectric layer 66, form second dielectric layer, 68, the second dielectric layers 68 and have the height etching selectivity to promote etching manufacturing process subsequently with respect to first dielectric layer 66.In one embodiment, second dielectric layer 68 comprises silicon nitride, and first dielectric layer 66 comprises silica, and second dielectric layer 68 is deposited on first dielectric layer 66 in high density chemistry vapor deposition mode (HDCVD).Because the characteristic of high density chemistry vapor deposition mode, the side wall upper part 70 that second dielectric layer 68 is positioned at grid stacked structure 52 is roughly a lot of than the thin thickness that is positioned at Semiconductor substrate 50 and grid stacked structure 52 top surfaces 72.In one embodiment, second dielectric layer 68 is used as sacrifice layer.
See also Fig. 5, etching second dielectric layer 68, to expose first dielectric layer 66 on the side wall upper part 70 that partly is positioned at grid stacked structure 52 top surfaces 72 and is positioned at grid stacked structure 58, in one embodiment, with phosphoric acid etch second dielectric layer 68.
See also Fig. 6, first dielectric layer, 66 parts that etching second dielectric layer 68 is exposed also are removed, for example with etch mode etching first dielectric layer 66, with the top surface 72 that exposes grid stacked structure 52 and the side wall upper part 70 of grid structure 58.Because second dielectric layer 68 has the height etching selectivity with respect to first dielectric layer 66, this etching manufacturing process only can be removed first dielectric layer 66 that few part has come out at most, remaining second dielectric layer, 68 shielding protections of remainder.
See also Fig. 7, after removing first dielectric layer 66 of not using 68 shielding protections of second dielectric layer, next the sidewall 80 along grid stacked structure 52 forms the 3rd dielectric layer 74, remains in first dielectric layer 66 on grid stacked structure 52 sidewalls 80 with coating.In one embodiment, before deposit the 3rd dielectric layer 74, remove etched second dielectric layer 68 last time fully.In another embodiment, second dielectric layer 68 and the 3rd dielectric layer 74 all include silicon nitride, and then second dielectric layer 68 also can keep in the 3rd dielectric layer 74 forming processes.The 3rd dielectric layer 74 is as the side wall layer around grid stacked structure 52.
See also Fig. 8, after forming the 3rd dielectric layer 74, form the 4th dielectric layer 76, cover on the 3rd dielectric layer and the Semiconductor substrate 50, the 4th dielectric layer 76 has the height etching selectivity with respect to the 3rd dielectric layer 74, in one embodiment, the 4th dielectric layer 76 comprises silica, and the 3rd dielectric layer 74 comprises silicon nitride.Next, determine the figure of the 4th dielectric layer 76 with a photoresist mask (not indicating among the figure), the part that the 4th dielectric layer 76 and residual first dielectric layer 66 are not covered by the photoresist mask with etched to form at least one contact openings 78, to expose the contact zone (not label) in the Semiconductor substrate 50.The source electrode or the drain region that can comprise field-effect transistor in the contact zone.Again the photoresist mask is removed at last.
The present invention also provides an integrated circuit, comprise: be formed on the grid stacked structure on the Semiconductor substrate, be formed on the oxide layer on the lower sides of grid stacked structure, along the gate dielectric side wall ring around the side wall layer that forms with the capping oxidation layer, and be formed on contact zone in the Semiconductor substrate, the contact zone and with grid stacked structure adjacency.Wherein, the grid stacked structure comprises the first metal layer, second metal level, and be formed on dielectric layer between the first metal layer and second metal level.In one embodiment, the first metal layer comprises polysilicon, and second metal level comprises the metal of infusibility, for example tungsten silicide.In one embodiment, side wall layer comprises silicon nitride, and has etching selectivity with respect to silica.Because oxide layer is covered by side wall layer, therefore can avoid in the autoregistration etching process etching solution infringement gate metal that oxide layer caused and the short circuit phenomenon between contacting metal.
Though more than with embodiment the present invention has been described; but embodiment does not limit the present invention, the technical staff of industry, without departing from the spirit and scope of the present invention; change and improve when doing some, so protection scope of the present invention is as the criterion with the scope that accompanying claims were defined.
Claims (20)
1. a self-aligned contacts window shape becomes method, comprising:
On Semiconductor substrate, form at least one grid stacked structure;
On this Semiconductor substrate and this grid stacked structure, form first dielectric layer;
Form second dielectric layer on this first dielectric layer, this second dielectric layer has etching selectivity with respect to this first dielectric layer;
This second dielectric layer of etching is to expose the top surface that is formed at this grid stacked structure and this first dielectric layer of this grid stacked structure side wall upper part of at least a portion;
Remove this first dielectric layer that has exposed; And
On the sidewall of this grid stacked structure, form the 3rd dielectric layer.
2. self-aligned contacts window shape as claimed in claim 1 becomes method, also comprises: form the first identical dielectric layer of a shape.
3. self-aligned contacts window shape as claimed in claim 1 becomes method, and wherein, the formation step of this grid stacked structure comprises:
On this Semiconductor substrate, form gate insulator;
On this gate insulator, form the first metal layer;
On this first metal layer, form the 4th dielectric layer; And
On the 4th dielectric layer, form second metal level.
4. become method as 1 described self-aligned contacts window shape of claim the, also comprise forming silicon oxide layer as this first dielectric layer.
5. self-aligned contacts window shape as claimed in claim 1 becomes method, also comprises forming silicon nitride layer as second dielectric layer.
6. become method as claim 1 a described self-aligned contacts window shape, also comprise forming silicon nitride layer as the 3rd dielectric layer.
7. self-aligned contacts window shape as claimed in claim 1 becomes method, wherein forms this first dielectric layer step and comprises: this grid stacked structure of oxidation and this Semiconductor substrate.
8. self-aligned contacts window shape as claimed in claim 7 becomes method, and wherein, this grid stacked structure step of oxidation comprises: carry out quick thermal treatment process with oxygen and hydrogen.
9. self-aligned contacts window shape as claimed in claim 7 becomes method, and wherein, this grid stacked structure step of oxidation comprises: carry out a fluid stream generating routine on the spot with oxygen and hydrogen.
10. self-aligned contacts window shape as claimed in claim 1 becomes method, also comprises: form one the 4th dielectric layer on the 3rd dielectric layer and this Semiconductor substrate, the 4th dielectric layer the 3rd dielectric layer relatively has etching selectivity.
11. self-aligned contacts window shape as claimed in claim 10 becomes method, also comprises: etching the 4th dielectric layer and this first dielectric layer, to expose the contact zone in this Semiconductor substrate in abutting connection with this grid stacked structure.
12. self-aligned contacts window shape as claimed in claim 10 becomes method, also comprises forming silicon oxide layer as the 4th dielectric layer.
13. become method as claim 1 a described self-aligned contacts window shape, comprise that also the vapor deposition of high density chemistry forms this second dielectric layer.
14. self-aligned contacts window shape as claimed in claim 1 becomes method, also comprises to embathe engraving method removing this first dielectric layer.
15. become method as claim 1 a described self-aligned contacts window shape, also comprise: before forming the 3rd dielectric layer, remove this second dielectric layer on this grid stacked structure sidewall.
16. a self-aligned contacts window shape becomes method, comprising:
On Semiconductor substrate, form at least one grid stacked structure;
This grid stacked structure of oxidation and this Semiconductor substrate are to form first oxide layer;
Form a sacrifice layer on this first oxide layer, this sacrifice layer this first oxide layer relatively has etching selectivity;
This sacrifice layer of etching is positioned at this first oxide layer of this grid stacked structure top and side wall upper part with exposure;
Remove this first oxide layer that exposes, to expose this grid stacked structure top and side wall upper part;
Along the sidewall of this grid stacked structure, form a side wall layer;
Form second oxide layer on this side wall layer and this Semiconductor substrate, this second oxide layer this sidewall relatively has etching selectivity; And
This second oxide layer of etching and this first oxide layer are to expose in abutting connection with the contact zone of this grid stacked structure.
17. self-aligned contacts window shape as claimed in claim 16 becomes method, at least one grid stacked structure step wherein is set comprises:
Form a gate insulator;
Form the first metal layer that covers this gate insulator;
Form the dielectric layer that covers this first metal layer; And
Form second metal level that covers this dielectric layer.
18. self-aligned contacts window shape as claimed in claim 16 becomes method, comprises forming silicon nitride layer as this sacrifice layer.
19. self-aligned contacts window shape as claimed in claim 16 becomes method, wherein, this grid stacked structure of oxidation comprises with oxygen and hydrogen and carries out the Rapid Thermal manufacturing process.
20. self-aligned contacts window shape as claimed in claim 16 becomes method, wherein, this grid stacked structure of oxidation comprises with oxygen and hydrogen and carries out a fluid stream generating routine on the spot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03147683XA CN1303651C (en) | 2003-07-16 | 2003-07-16 | Method for forming self alignment contact window |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03147683XA CN1303651C (en) | 2003-07-16 | 2003-07-16 | Method for forming self alignment contact window |
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| Publication Number | Publication Date |
|---|---|
| CN1571120A CN1571120A (en) | 2005-01-26 |
| CN1303651C true CN1303651C (en) | 2007-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB03147683XA Expired - Fee Related CN1303651C (en) | 2003-07-16 | 2003-07-16 | Method for forming self alignment contact window |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106356299B (en) * | 2015-07-13 | 2021-04-13 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103608A (en) * | 1998-04-20 | 2000-08-15 | United Integrated Circuit Corp. | Method of forming a contact window |
| US6245625B1 (en) * | 1999-06-19 | 2001-06-12 | United Microelectronics Corp. | Fabrication method of a self-aligned contact window |
| JP2002057124A (en) * | 2000-08-01 | 2002-02-22 | Hynix Semiconductor Inc | Method of manufacturing semiconductor element |
| CN1349255A (en) * | 2000-10-16 | 2002-05-15 | 联华电子股份有限公司 | Automatic alignment method of bit line contacting window and node conducting window |
| CN1400649A (en) * | 2001-08-08 | 2003-03-05 | 旺宏电子股份有限公司 | Method for reducing stress of isolated component to active zone and etching effect |
| CN1404129A (en) * | 2001-09-06 | 2003-03-19 | 旺宏电子股份有限公司 | Method of reducing stress of shallow-channel isolating side wall oxide layer |
-
2003
- 2003-07-16 CN CNB03147683XA patent/CN1303651C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103608A (en) * | 1998-04-20 | 2000-08-15 | United Integrated Circuit Corp. | Method of forming a contact window |
| US6245625B1 (en) * | 1999-06-19 | 2001-06-12 | United Microelectronics Corp. | Fabrication method of a self-aligned contact window |
| JP2002057124A (en) * | 2000-08-01 | 2002-02-22 | Hynix Semiconductor Inc | Method of manufacturing semiconductor element |
| CN1349255A (en) * | 2000-10-16 | 2002-05-15 | 联华电子股份有限公司 | Automatic alignment method of bit line contacting window and node conducting window |
| CN1400649A (en) * | 2001-08-08 | 2003-03-05 | 旺宏电子股份有限公司 | Method for reducing stress of isolated component to active zone and etching effect |
| CN1404129A (en) * | 2001-09-06 | 2003-03-19 | 旺宏电子股份有限公司 | Method of reducing stress of shallow-channel isolating side wall oxide layer |
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| CN1571120A (en) | 2005-01-26 |
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