CN1378264A - Automatic aligning contact method and sacrifical filling column - Google Patents
Automatic aligning contact method and sacrifical filling column Download PDFInfo
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- CN1378264A CN1378264A CN 01110194 CN01110194A CN1378264A CN 1378264 A CN1378264 A CN 1378264A CN 01110194 CN01110194 CN 01110194 CN 01110194 A CN01110194 A CN 01110194A CN 1378264 A CN1378264 A CN 1378264A
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Abstract
The present invention provides a technological method of self-aligning contact with sacrified packed column, which does not damage other isolated layers to affect the isoalting effect so to occur the current leakage, and moreover, the said method needs not to use etching agent with high selectivity ratio of silicon oxide to silicon nitride to achieve the self-aligning contact course in the reactive ion etching process. In addition, the thickness of insulation layer covered on the conductor formed by this method can be reduced so as to decrease the aspect ratio in order to obtain a better gap-filled insulation layer so that the insulation material applied by this method can greatly reduce the parasitic capacitance between the conductor layer.
Description
The invention relates to a kind of method of aiming at contact voluntarily, particularly relevant for a kind of process of aiming at contact voluntarily with sacrifice type packed column.
The making of semiconductor integrated circuit is extremely complicated process, and purpose is various electronic building bricks and circuit that particular electrical circuit is required, dwindles being produced in the small size substrate.Wherein, each assembly must electrically connect by suitable internal connecting line (interconnect), and the side is brought into play desired function.The metallization process of general so-called integrated circuit (metallization), except making each layer conductor figure, and with interlayer hole (contact/via) structure, between assembly contact zone and lead, or the channel of getting in touch between the multi-layer conductor leads.The development of deep submicron process technology more highlights the importance of some particular semiconductor manufacturing technology, as technologies such as etching lithography process (lithography process) and dry-etchings.The development of high-accuracy type exposure instrument and high photosensitive material has made the sub-micron image on the photoresist layer easily obtain, moreover the equipment and the technology of advanced dry-etching are applied to also make in the VLSI (very large scale integrated circuit) chip manufacturing sub-micron image on the photoresist layer accurately to depict on the etched material.Yet, further dwindle semiconductor chip size except the innovation of above-mentioned advanced person's technology, also must research and develop other special process or structure.
Aim at contact process voluntarily,, and can dwindle semiconductor inner assembly size because of it can reduce the step of etching lithography process, thus the size of dwindling chip, and it is applied in the deep submicron process widely.At present, because the processing of integrated circuit develops towards ULSI, therefore inner current densities more and more increases, along with the integration of integrated circuit increases day by day, aim at voluntarily now contact process still some technology barrier remain to be broken through.Below will sketch traditional contact process of aligning voluntarily and technical deficiency thereof.
At first, see also 1A figure, it is presented on the surface of substrate 2, form a conductor structure of being formed by silicon oxide liner bottom 4, polysilicon layer 6 and tungsten silicide layer 8, and form on the silicon nitride cap rock 10 on the conductor structure and on silicon nitride cap rock and conductor structure both sides sidewall form silicon nitride spacers 12.Secondly, see also 1B figure, it is presented on the conductor structure comprehensive formation one dielectric layer (silicon oxide layer) and implements etching offset printing and etching program again, form to define this dielectric layer as shown in the figure dielectric layer 14 and the contact hole 16 between between this dielectric layer.Then, see also 1C figure, comprehensive formation one conductive layer 18, it fills up contact hole 16 and electrically connects with the semiconductor-based end 20, again with this conductive layer 18 of cmp, makes and exposes dielectric layer 14, and make conductive layer 18 form the contact plunger that is insulated isolation.
When above-mentioned traditional contact process of aligning voluntarily forms contact hole 16 steps, and when implementing etching offset printing and etching oxidation silicon dielectric layer, if adopt the anisotropic reactive ion etching to use CHF
3During as etchant, must make the silicon oxide layer and the ratio of the etched speed of silicon nitride layer is more than 20 to 1, in order to avoid be damaged to cap rock 10 and silicon nitride spacers 12 on the silicon nitride, and present manufacturing technology still can't reach this target.2A figure shows that the desirable contact process of aligning voluntarily carries out anisotropic contact hole that reactive ion etching forms 16, and 2B figure show carry out the anisotropic reactive ion etching after, the actual contact hole 16 that forms, cap rock 10 and silicon nitride spacers 12 have been subjected to etched loss on the silicon nitride as seen from the figure, if and damage is too serious, insulation and isolation effect be will have influence on, conductor structure and contact plunger short circuit caused.
Above shortcoming makes assembly will dwindle yardstick the many of difficulty that seem again, especially in deep sub-micron processes, only allow the live width and the high-aspect-ratio of smaller szie, and also want difficulty at present if will significantly improve the high selectivity of reactive ion etching, therefore if no new technology breaks through, to make that product percent of pass is difficult to promote, and can't reach the volume production of economic scale.
The object of the present invention is to provide a kind of contact process of aligning voluntarily method with sacrifice type packed column, this method can not damage other separator when implementing to aim at contact procedure voluntarily, makes leakage current generating and influence isolation effect.
Another purpose of the present invention is to provide a kind of contact process of aligning voluntarily method with sacrifice type packed column, and this method need not to use in reactive ion etching process high oxidation silicon to select the etchant of ratio to reach for silicon nitride and aims at contact procedure voluntarily.
The present invention still has another purpose to be to provide a kind of and has sacrifice type packed column and aim at the contact process method voluntarily, and the insulating material that this method adopts can significantly lower the parasitic capacitance between conductor layer.
Simply say, the present invention discloses a kind of contact method of aligning voluntarily with sacrifice type packed column, at first, the semiconductor substrate is provided, in substrate, form the conductor structure of forming by silicon oxide liner bottom, polysilicon layer and tungsten silicide layer in regular turn, afterwards, on conductor structure, form an insulation and go up cap rock, then define conductor structure figure.Then, form a wire insulation wall in last cap rock of insulation and conductor structure both sides sidewall.Secondly, compliance forms an insulation liner layer to cover wire insulation wall and conductor structure surface.Secondly, comprehensive formation one sacrifice layer is implemented printing of etching dry plate and etching program again, defines this sacrifice layer to form sacrifice type packed column and the opening between between this sacrifice type packed column.Then, comprehensive formation one is different from the insulating barrier of insulating cell layer material to fill up the opening between this sacrifice type packed column.Then, grind this insulating barrier, make the upper surface that exposes this sacrifice type packed column.Moreover, remove this sacrifice type packed column and form a contact window.Secondly, utilize the anisotropic reactive ion etching process to remove to be covered in and the insulation liner layer between between this wire insulation wall via contact window at semiconductor-based the end.At last, comprehensive formation one conductive layer fills up this contact window and electrically connects with the semiconductor-based end, grinds this conductive layer again, makes and exposes insulating barrier, and make conductive layer form the contact plunger that is insulated isolation.
In sum, a kind of contact method of aligning voluntarily provided by the present invention with sacrifice type packed column, this method can not damage other separator when implementing to aim at the contact process step voluntarily, and then influence isolation effect and make leakage current generating, and the method need not to use in reaction ionic etching method high oxidation silicon to select the etchant of ratio to reach for silicon nitride and aims at contact voluntarily, in addition, the thickness that this method forms cap rock in the insulation that covers on the lead can reduce, thereby dwindle vertical wide ratio, obtain preferable gap insulation layer and fill, the insulating material that this method adopts can significantly lower the parasitic capacitance between conductor layer.
For allow state on the present invention with other purpose, feature, and advantage can become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
1A to 1C figure is the manufacturing process profile of aiming at contact process voluntarily of known technology.
2A figure shows the desirable profile of aiming at the formed contact hole of contact process voluntarily.
After the anisotropic reactive ion etching is carried out in 2B figure demonstration, the profile of the actual contact hole that forms.
3A to 3F figure is the manufacturing process profile of aiming at contact process voluntarily with sacrifice type packed column according to the embodiment of the invention 1.
4A to 4F figure is the manufacturing process profile of aiming at contact process voluntarily with sacrifice type packed column according to the embodiment of the invention 2.
5A to 5F figure is the manufacturing process profile of aiming at contact process voluntarily with sacrifice type packed column according to the embodiment of the invention 3.
Symbol description
20,40, the 60 ~ semiconductor-based end; 22,42,62 ~ silicon oxide liner bottom; 24,44,64 ~ polysilicon layer; 26,46,66 ~ tungsten silicide layer; 28, cap rock is gone up in 48,68 insulation; 30,52 ~ dielectric spacer layer; 32,50 ~ insulation liner layer; 70 ~ the first insulation liner layer; 72 ~ the second insulation liner layer; 34,54,74 ~ sacrifice type packed column; 36,56,76 ~ opening; 37,57,77 ~ contact window; 38,58,78 ~ insulating barrier; 39,59,79 ~ conductive layer.
Embodiment 1
Present embodiment illustrates a preferred embodiment of improving one's methods according to the present invention for scheming with reference to 3A to 3F.At first, shown in 3A figure, providing semiconductor substrate 20, for example is a silicon wafer, can form any required semiconductor subassembly on it, for example is transistor component, herein for simplicity, and only with smooth substrate 20 expressions.On the surface of substrate 20, form in regular turn by silicon monoxide substrate layer 22, the conductor structure that one polysilicon layer 24 and a tungsten silicide layer 26 are formed, for example utilize a thermal oxidation technology to form a thin silicon oxide substrate layer 22 earlier, then with a plasma enhanced chemical vapor deposition (PECVD) shaping one polysilicon layer 24 and a tungsten silicide layer 26, afterwards, forming an insulation and go up cap rock 28 on conductor structure, is the silicon dioxide layer of 200 to 2500 with a plasma (plasma) enhancing chemical vapour deposition (CVD) (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness for example, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer.Then, carry out etching offset printing and etching program, the conductor structure figure that cap rock 28 is formed is gone up in the silicon oxide liner bottom 22, polysilicon layer 24, tungsten silicide layer 26 and the insulation that define as shown in the figure.Then, forming a wire insulation wall 30 in last cap rock of insulation and conductor structure both sides sidewall, is silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or the silicon carbide layer of 100 to 600 with a plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness also.This thin layer of etch-back (etching-back) forms a dielectric spacer layer 30 again.Secondly, compliance forms an insulation liner layer 32 to cover wire insulation wall and conductor structure surface, is silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or the silicon carbide layer of 100 to 400 with plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness also.
Secondly, see also 3B figure, comprehensive formation one sacrifice layer is implemented etching offset printing and etching program again, defines this sacrifice layer to form sacrifice type packed column 34 and the opening 36 between between this sacrifice type packed column.This sacrifice layer can be a polysilicon layer since before formed dielectric spacer layer 30 and insulation liner layer 32, cause electrical short circuit so produce residue can prevent this polysilicon layer of etching the time.
Then, see also 3C figure, form an insulating barrier that is different from the insulating cell layer material to fill up the opening 36 between this sacrifice type packed column, for example with the be shaped oxide skin(coating) of a thickness 5000 to 8000 of a plasma enhanced chemical vapor deposition (PECVD) comprehensively.
Then, utilize flatening process, as cmp, grind this insulating barrier, make the upper surface that exposes this sacrifice type packed column, form the pattern of insulating barrier 38 as shown in the figure, the rotary speed in the adjusting process parameter for example, downforce, grinding pad type and grinding agent kind are with the rate that removes in the control technology, uniformity and selectivity, the top of worn this insulating barrier.
Moreover, see also 3D figure, utilizations tropism's dry etching process such as grade or etc. tropism's wet etching process sacrifice type packed column carried out etch-back form a contact window 37 to remove this sacrifice type packed column.
Secondly, see also 3E figure, utilize anisotropic reactive ion etching processing procedure to be covered in and the insulation liner layer between between this wire insulation wall at semiconductor-based the end with removal via contact window 37.
At last, see also 3F figure, form a conductive layer 39 comprehensively, fill up this contact window 37 and electrically connect with the semiconductor-based ends 20, with this conductive layer 39 of cmp, make and expose insulating barrier 38 again, and make conductive layer 39 form the contact plunger that is insulated isolation, wherein, this conductive layer is sputter polysilicon layer or tungsten layer.
Present embodiment illustrates another preferred embodiment of improving one's methods according to the present invention for scheming with reference to 4A to 4F.At first, shown in 4A figure, on the surface at the semiconductor-based end 40, form in regular turn by silicon monoxide substrate layer 42, the conductor structure that one polysilicon layer 44 and a tungsten silicide layer 46 are formed, for example utilize a step of thermal oxidation to form a thin silicon oxide substrate layer 42 earlier, then with a plasma enhanced chemical vapor deposition (PECVD) shaping one polysilicon layer 44 and a tungsten silicide layer 46, afterwards, forming an insulation and go up cap rock 48 on conductor structure, is the silicon dioxide layer of 200 to 2500 with a plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness for example, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer.Then, carry out etching offset printing and etching program, the conductor structure figure that cap rock 48 is formed is gone up in the silicon oxide liner bottom 42, polysilicon layer 44, tungsten silicide layer 46 and the insulation that define as shown in the figure.Then, compliance forms an insulation liner layer 50 to cover the conductor structure surface, is silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or the silicon carbide layer of 100 to 400 with plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness also.Secondly, forming a wire insulation wall 52 in the insulation liner layer both sides sidewall that covers conductor structure, is silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or the silicon carbide layer of 100 to 600 with plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness also.This thin layer of etch-back (etching-back) forms a dielectric spacer layer 52 again.
Secondly, see also 4B figure, form a sacrifice layer comprehensively and implement etching offset printing and etching program again, define this sacrifice layer to form sacrifice type packed column 54 and the opening 56 between between this sacrifice type packed column.This sacrifice layer can be a polysilicon layer since before formed dielectric spacer layer 50 and insulation liner layer 52, cause electrical short circuit so produce residue can prevent this polysilicon layer of etching the time.
Then, see also 4C figure, form an insulating barrier that is different from the insulating cell layer material to fill up the opening 56 between this sacrifice type packed column, for example with the be shaped oxide skin(coating) of a thickness 5000 to 8000 of a plasma enhanced chemical vapor deposition (PECVD) comprehensively.
Then, utilize flatening process, as cmp, grind this insulating barrier, make the upper surface that exposes this sacrifice type packed column, form the pattern of insulating barrier 58 as shown in the figure, the rotary speed in the adjusting process parameter for example, downforce, grinding pad type and grinding agent kind are with the rate that removes in the control technology, uniformity and selectivity, the top of worn this insulating barrier.
Moreover, see also 4D figure, utilizations tropism's dry etching process such as grade or etc. tropism's wet etching process sacrifice type packed column carried out etch-back form a contact window 57 to remove this sacrifice type packed column.
Secondly, see also 4E figure, utilize the anisotropic reactive ion etching process to be covered in and the insulation liner layer between between this wire insulation wall at semiconductor-based the end with removal via contact window 57.
At last, see also 4F figure, comprehensive formation one conductive layer 59, it passes insulating barrier 58 and electrically connects with the semiconductor-based end 40, with this conductive layer 59 of cmp, make and expose insulating barrier 58 again, and make conductive layer 59 form the contact plunger that is insulated isolation, wherein, this conductive layer is sputter polysilicon layer or tungsten layer.
Embodiment 3
Present embodiment illustrates another preferred embodiment of improving one's methods according to the present invention for scheming with reference to 5A to 5F.At first, shown in 5A figure, on the surface at the semiconductor-based end 60, form in regular turn by silicon monoxide substrate layer 62, the conductor structure that one polysilicon layer 64 and a tungsten silicide layer 66 are formed, for example utilize a step of thermal oxidation to form a thin silicon oxide substrate layer 62 earlier, then with a plasma enhanced chemical vapor deposition (PECVD) shaping one polysilicon layer 64 and a tungsten silicide layer 66, afterwards, forming an insulation and go up cap rock 68 on conductor structure, is the silicon dioxide layer of 200 to 2500 with plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) shaping one thickness for example, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer.Then, implement etching offset printing and etching program, the conductor structure figure that cap rock 68 is formed is gone up in the silicon oxide liner bottom 62, polysilicon layer 64, tungsten silicide layer 66 and the insulation that define as shown in the figure.Then, compliance forms one first insulation liner layer 70 and one second insulation liner layer 72 to cover the conductor structure surface, is the silicon nitride layer 70 of 100 to 600 and the oxide skin(coating) 72 that a thickness is 100 to 600 with a plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) thickness that is shaped also.
Secondly, see also 5B figure, comprehensive formation one sacrifice layer is implemented etching offset printing and etching program again, defines this sacrifice layer to form sacrifice type packed column 74 and the opening 76 between between this sacrifice type packed column.This sacrifice layer can be a polysilicon layer since before formed dielectric spacer layer 70 and insulation liner layer 72, cause electrical short circuit so produce residue can prevent this polysilicon layer of etching the time.
Then, see also 5C figure, comprehensive formation one is different from the insulating barrier of insulating cell layer material to fill up the opening 76 between this sacrifice type packed column, for example with the be shaped oxide skin(coating) of a thickness 5000 to 8000 of a plasma enhanced chemical vapor deposition (PECVD).
Then, utilize flatening process, as cmp, grind this insulating barrier, make the upper surface that exposes this sacrifice type packed column, form the pattern of insulating barrier 78 as shown in the figure, the rotary speed in the adjusting process parameter for example, downforce, grinding pad type and grinding agent kind are with the rate that removes in the control technology, uniformity and selectivity are on worn this insulating barrier.
Moreover, see also 5D figure, utilizations tropism's dry etching process such as grade or etc. tropism's wet etching process sacrifice type packed column carried out etch-back form a contact window 77 to remove this sacrifice type packed column.
Secondly, see also 5E figure, utilize the anisotropic reactive ion etching process to be covered in and the insulation liner layer between between this wire insulation wall at semiconductor-based the end with removal via contact window 77.
At last, see also 5F figure, comprehensive formation one conductive layer 79, it passes insulating barrier 78 and electrically connects with the semiconductor-based end 60, with this conductive layer 79 of cmp, make and expose insulating barrier 78 again, and make conductive layer 79 form the contact plunger that is insulated isolation, wherein, this conductive layer is sputter polysilicon layer or tungsten layer.
Though the present invention discloses as above with preferred embodiment; yet be not in order to limit the present invention; anyly know art technology person; without departing from the spirit and scope of the invention; when can doing to change and retouching, so protection scope of the present invention should be looked the accompanying Claim scope and is as the criterion with reference to specification and the accompanying drawing person of defining.
Claims (20)
1. the contact process of the aligning voluntarily method with sacrifice type packed column is applicable to the semiconductor substrate, and this method comprises the following steps:
(a) on this semiconductor-based end, form a conductor structure;
(b) on this conductor structure, form an insulation and go up cap rock;
(c) form a wire insulation wall in last cap rock of this insulation and conductor structure both sides sidewall;
(d) form an insulation liner layer to cover this wire insulation wall and this conductor structure surface;
(e) form a sacrifice layer, and define this sacrifice layer to form sacrifice type packed column and the opening between between this sacrifice type packed column;
(f) form one and be different from the insulating barrier of this insulating cell layer material to fill up the opening between this sacrifice type packed column;
(g) remove this sacrifice type packed column and form a contact window;
(h) remove via this contact window and be covered on this semiconductor-based end and this insulation liner layer between between this wire insulation wall; And
(i) formation one conductive layer fills up this contact window and electrically connects with this semiconductor-based end.
2. the method for claim 1 is characterized in that, the conductor structure in this step (a) is made up of silicon oxide liner bottom, polysilicon layer and tungsten silicide layer.
3. the described method of claim 1 is characterized in that, it is to be silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer that cap rock, this wire insulation wall and this insulation liner layer are gone up in this insulation.
4. the described method of claim 1 is characterized in that, this step (f) also comprises with this insulating barrier of cmp, makes and exposes surface on this sacrifice type packed column.
5. the described method of claim 1 is characterized in that, this sacrifice type packed column of the removal in this step (g), utilization wait tropism's dry etching process or etc. tropism's wet etching process this sacrifice type packed column is carried out etch-back.
6. the described method of claim 1 is characterized in that, removes in this step (h) to be covered on this semiconductor-based end and the insulation liner layer between between this wire insulation wall is to utilize the anisotropic reactive ion etching process to finish.
7. the described method of claim 1 is characterized in that, the conductive layer in this step (i) is to be polysilicon layer or tungsten layer, and adopts this conductive layer of cmp, makes and exposes this insulating barrier, and make this conductive layer form the contact plunger that is insulated isolation.
8. the contact process of the aligning voluntarily method with sacrifice type packed column is applicable to the semiconductor substrate, and this method comprises the following steps:
(a) on this semiconductor-based end, form a conductor structure;
(b) on this conductor structure, form an insulation and go up cap rock;
(c) form an insulation liner layer to cover this conductor structure surface;
(d) form a wire insulation wall in this insulation liner layer both sides sidewall that covers this conductor structure;
(e) form a sacrifice layer, and define this sacrifice layer to form sacrifice type packed column and the opening between between this sacrifice type packed column;
(f) form one and be different from the insulating barrier of this insulating cell layer material to fill up the opening between this sacrifice type packed column;
(g) remove this sacrifice type packed column and form a contact window;
(h) remove via this contact window and be covered on this semiconductor-based end and the described insulation liner layer between between this wire insulation wall; And
(i) formation one conductive layer fills up this contact window and electrically connects with this semiconductor-based end.
9. the described method of claim 8 is characterized in that, the conductor structure in this step (a) is made up of silicon oxide liner bottom, polysilicon layer and tungsten silicide layer.
10. the described method of claim 8 is characterized in that, it is to be silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer that cap rock, this wire insulation wall and this insulation liner layer are gone up in this insulation.
11. the described method of claim 8 is characterized in that, this step (f) also comprises this insulating barrier of employing cmp, makes the upper surface that exposes this sacrifice type packed column.
12. the described method of claim 8 is characterized in that, this sacrifice type packed column of the removal in this step (g), be utilization wait tropism's dry etching process or etc. tropism's wet etching process this sacrifice type packed column is carried out etch-back.
13. the described method of claim 8 is characterized in that, the removal in this step (h) was covered on this semiconductor-based end and these insulating cell series of strata between between this wire insulation wall utilize the anisotropic reactive ion etching process to finish.
14. the described method of claim 8 is characterized in that, the conductive layer in this step (i) is polysilicon layer or tungsten layer, and adopts this conductive layer of cmp, makes and exposes this insulating barrier, and make this conductive layer form the contact plunger that is insulated isolation.
15. the contact process of the aligning voluntarily method with sacrifice type packed column is applicable to the semiconductor substrate, this method comprises the following steps:
(a) on this semiconductor-based end, form a conductor structure;
(b) on this conductor structure, form an insulation and go up cap rock;
(c) form one first insulation liner layer to cover this conductor structure surface;
(d) form one second insulation liner layer to cover this first insulation liner layer;
(e) form a sacrifice layer, and define this sacrifice layer to form sacrifice type packed column and the opening between between this sacrifice type packed column;
(f) form one and be different from the insulating barrier of this first insulating cell layer material to fill up the opening between this sacrifice type packed column;
(g) remove this sacrifice type packed column and form a contact window;
(h) remove via this contact window and be covered on this semiconductor-based end and first insulation liner layer, second insulation liner layer between between this conductor structure; And
(i) formation one conductive layer fills up this contact window and electrically connects with this semiconductor-based end.
16. as the method as described in the 15th of the claim, wherein, it is to be silicon dioxide layer, silicon nitride layer, silicon oxynitride layer, alumina layer or silicon carbide layer that cap rock, this wire insulation wall and this insulation liner layer are gone up in this insulation.
17. as the method as described in the 15th of the claim, wherein, this step (f) also comprises and adopts this insulating barrier of cmp, makes and exposes surface on this sacrifice type packed column.
18. as the method as described in the 15th of the claim, wherein, this sacrifice type packed column of the removal in this step (g), be utilization wait tropism's dry etching process or etc. tropism's wet etching process this sacrifice type packed column is carried out etch-back.
19. as the method as described in the 15th of the claim, wherein, the removal in this step (h) was covered on this semiconductor-based end, and this insulation liner layer between between this wire insulation wall is to utilize the anisotropic reactive ion etching process to finish.
20. as the method as described in the 15th of the claim, wherein, the conductive layer in this step (i) is to be polysilicon layer or tungsten layer, and adopts this conductive layer of cmp, makes and exposes this insulating barrier, and make this conductive layer form the contact plunger that is insulated isolation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011101946A CN1153273C (en) | 2001-03-29 | 2001-03-29 | Automatic aligning contact method and sacrifical filling column |
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| CNB011101946A CN1153273C (en) | 2001-03-29 | 2001-03-29 | Automatic aligning contact method and sacrifical filling column |
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| CN1378264A true CN1378264A (en) | 2002-11-06 |
| CN1153273C CN1153273C (en) | 2004-06-09 |
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| CN105609471A (en) * | 2014-11-14 | 2016-05-25 | 朗姆研究公司 | Plated metal hard mask for vertical NAND hole etch |
| CN105609471B (en) * | 2014-11-14 | 2019-05-28 | 朗姆研究公司 | Metal lining hard mask for the etching of vertical nand hole |
| CN105895510A (en) * | 2015-02-13 | 2016-08-24 | 台湾积体电路制造股份有限公司 | A method of forming a semiconductor device and methods of patterning |
| CN105895510B (en) * | 2015-02-13 | 2019-04-12 | 台湾积体电路制造股份有限公司 | Form the manufacturing method and patterning method of semiconductor device |
| CN106298669A (en) * | 2015-06-24 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| CN106356299A (en) * | 2015-07-13 | 2017-01-25 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method of semiconductor structure with self-aligned spacer |
| CN106356299B (en) * | 2015-07-13 | 2021-04-13 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method thereof |
| CN113140569A (en) * | 2020-01-20 | 2021-07-20 | 华邦电子股份有限公司 | Method for manufacturing memory device |
| CN113140569B (en) * | 2020-01-20 | 2024-04-30 | 华邦电子股份有限公司 | Method for manufacturing memory device |
| CN111739839A (en) * | 2020-06-23 | 2020-10-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing self-aligned contact hole and method for manufacturing semiconductor device |
| CN111739839B (en) * | 2020-06-23 | 2021-07-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing self-aligned contact hole and method for manufacturing semiconductor device |
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