TW575917B - method and semiconductor structure for preventing over etching of barrier layer, and forming method of contact using the same - Google Patents

Abstract

A kind of method for preventing over etching of barrier layer is provided in the present invention. The invention includes the following steps: providing a semiconductor substrate where plural gate structures are formed; forming a conformal barrier layer to cover these gate structures; forming a conformal passivation dielectric layer on the barrier layer; and forming an interlayer dielectric layer to cover these gate structures and to fill up in between these gate structures.

Description

575917

FIELD OF THE INVENTION The present invention relates to a novel semiconductor process, and more particularly, to a method for preventing the P resist layer from being excessively left over. In the prior art, with the continuous efforts to improve the packaging density of integrated circuits and reduce the size of the wafer, the alignment error between different pattern layers is the main obstacle, so there are many self-aligned processes. , To reduce the distance between components and increase the density of components. Taking the manufacturing process of a borderless contact window as an example, 'as shown in FIG. 1A' is performed on a semiconductor substrate 10 having a plurality of gate structures g formed thereon. After forming the source-drain region, it conforms to cover a barrier layer. 4 is mostly oxyn 1 tr ide. Its role is to prevent the resistance of ion diffusion during the subsequent formation of the borophosphosilicate glass layer (BPSG). A barrier layer and an etch stop layer when a contact window is subsequently formed. Next, an interlayer dielectric layer (LD) 12, usually Borophosphosilicate glass (BPSG), covers the above-mentioned plurality of gate structures G and fills the gaps between the gates. In order to display the contact window more clearly, please refer to Figures 丨 B and 1C. Figures IB and 1C are cross-sectional views of the contact window in the conventional borderless contact window manufacturing process. A photoresist layer on the interlayer dielectric layer 12? After 1 ^, a lithography technique and a #etching step are used to open between the gates to form a contact window in Fig. 丨 c. However, in the traditional process described above, the steam f low step in the formation of borophosphosilicate glass will cause the following reactions:… P2 05 + 3 H20 2H3P04 ~

575917 V. Description of the invention (2) Production code: acid 'and side stone Xiyou tired ^ n ^ 澧 produces ancient ^ p ^ phosphorus (p) between the glass and the early layer of resistance P: ίί: ϊ 二ϊί Ϊ thinning of the barrier layer 'cause Λ, in the subsequent process ΐ: ί = = the role of the protection of the structure of the interelectrode structure: 部分 Figure 1C' X indicates that the barrier layer is over-etched (〇 二 和As shown in Figure 1D, the short-circuit phenomenon of the contact window affects the source / drain resistance and greatly reduces the yield rate of the process. Π Summary of the Invention In view of this, the object of the present invention is to address the aforementioned helmet method 'avoid In the BPSG process, the thickness k of the barrier layer is thin, which leads to a decrease in yield, thereby improving product yield and improving product performance. To achieve the above object, the present invention provides a method for preventing the barrier layer from being over-etched, including: A semiconductor substrate having a plurality of gate structures is formed, and a barrier layer is formed to cover the gate structures in compliance; a protective dielectric layer is formed on the barrier layer in compliance; and an interlayer dielectric layer is formed to cover The gate structures and fill the space between the gate structures In the above method, the barrier layer is preferably an oxynitride, the protective dielectric layer is an undoped glass layer (USG) or a shed stone glass (BSG), and the interlayer dielectric layer is a commonly used boron. Phosphosilicate glass layer (BPSG). The semiconductor structure for preventing the barrier layer from being over-etched according to the present invention includes a semiconductor substrate; a plurality of gate structures are formed on the semiconductor substrate; and a barrier layer is compliantly formed. On the semiconductor substrate and the gate structures; a protective dielectric layer formed on the barrier layer; and an interlayer dielectric layer formed on the barrier layer and filled between the gate structures .

575917 V. Description of the invention (3) By the method for preventing the barrier layer from being over-etched, the formation of a protective dielectric layer between the interlayer dielectric layer 'that is, borophosphosilicate glass and the barrier layer' can reduce the overall Content of phosphorus, which can prevent the formation of phosphoric acid; In addition, the 'protective dielectric layer' also has a barrier function, which can avoid the invasion of acid, and the etching rate of the acid to the oxide is relatively low. It can isolate the original barrier layer (nitrogen oxide), avoid acid attack, and then prevent the contact window from being short-circuited. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and the accompanying drawings are described in detail as follows: Embodiment 2A to 2E A cross-sectional view showing a process of a method for preventing over-engraving of a barrier layer according to an embodiment of the present invention. 9 First, a semiconductor silicon substrate 100 is provided, and a plurality of array gates are formed on the semi-conductive plate 100 in a conventional manner. Then, a thickness of about 200 to 2 is formed using a marginal material. After the 00A insulation layer, such as Ba Shixi or nitride nitride. Next, use SFe, cf4, CHF3 or as the last name ... Use the reactive ion plutonium process to perform the material-oriented anisotropic etching, such as plasma etching, plasma etching, and other insulating layers on the substrate. So: two; the spacer 104 on both sides of the semiconductor interrogation structure shown in FIG. 2A is next to the gate structure 10 and the gap body substrate 10 as described above. Ion implantation is used to form a source 2 on the source. The above ion implantation uses phosphorus ions or arsenic ions.

575917 V. Description of the invention (4) 1X1 015 ~ 6x 1 015cnr2, you can! ^ n] implantation under the conditions of v ^ tf. The above-mentioned steps for forming the gate can use conventional techniques, and the gate structure usually includes gas & cut @ ^ ^ 赝 is used ... Crane Λ complex V: layer ... evening layer ... Gei :: Ui = B picture Compliance formation-barrier layer 108 overlay = gate, "冓 106. The above barrier layer is preferably a dielectric material, such as SiON. The thickness of the above barrier layer is preferably 100 angstroms. Then As shown in FIG. 2C, the compliance layer 120 is formed to cover the above barrier layer.] [〇8. Only ice %% on the ice φ # From only "Dianguang ^ ^ Πκγ ^ I The above dielectric layer is preferably not It is doped glass glass (BSG), but it is better to use undoped glass. The above-mentioned USG deposition method can be carried out by the reaction of tetraethoxysilane (TEOS) and ozone (ozone), while using tetraethoxyfane, triethylboron (TEB) and ozone reaction. Next, as shown in FIG. 2D, an inter-layer dielectric layer (ILD) 122 is comprehensively formed to cover the protective dielectric layer 120. The above interlayer dielectric layer is preferably a dielectric material, such as spin-on glass (SOG), silicon oxide, borophosphosilicate glass (BPSG), and the like. This embodiment uses borophosphosilicate glass (BPSG) with better trench filling ability. For example, it can be formed under the environment of SiH4, pi, using atmospheric pressure chemical vapor deposition (APCVD). Then, a planarization process can be performed to obtain a flat upper surface. Once the semiconductor device for preventing the barrier layer from being over-etched according to the present invention is prepared through the above steps, the semiconductor device includes a semiconductor substrate; a plurality of gate structures 10 6 'are formed on the semiconductor substrate;丨 〇8, compliance is formed on the semiconductor substrate 100 and the gate structures 丨 〇6; protection dielectric

0593-9221twf (nl); 91070tw; phoebe.ptd page 8 575917 V. Description of the invention (5) A layer 1 2 0 is formed on the barrier layer 108; and an interlayer dielectric layer 22 is formed on The barrier layer 108 is filled between the gate structures. After forming the above-mentioned interlayer dielectric layer at 70%, the interlayer dielectric layer and the protective dielectric layer between the gate electrodes can be removed by micro-shirt technology and etching in a conventional manner to form the layer shown in FIG. 2E. Contact window 丨 2 4. The method for preventing the barrier layer from being over-etched according to the present invention has the following advantages: It slows down the thickness of the barrier layer during the subsequent BPSG steam step, and the experiment proves that even at a high phosphorus concentration (such as 5.0%) Can achieve excellent = separation effect, that is to say, the process conditions become wider, which is less affected by changes in phosphorus concentration. Furthermore, according to the method of the present invention, the barrier layer is less affected by the process, and it is sufficient to retain its effective thickness Furthermore, the effect of the barrier layer as an etch stop layer is strengthened, and it can provide better process control for the subsequent contact window etching, which will greatly improve the yield. 2. From the viewpoint of mass production, the protective dielectric layer (USg) and interlayer dielectric layer (BPSG) can be formed by the conventional BpsG process, and only the deposition formula used by the original BJSG needs to be changed. The process compatibility is the same, and it will not increase in process cost and product cycle time. -Although the present invention has been disclosed as above with a preferred embodiment, it is not invented by anyone. Those skilled in the art will not be departed from the spirit of the present invention. The scope of the patent is defined in the appended file as follows: quasi. Compliance

575917 Brief Description of Drawings Figure 1A is a sectional view showing a conventional borderless contact. Figures 1B and 1C are cross-sectional views showing the steps of forming a contact window in a conventional borderless contact process. Figure 1D is a SEM image showing a conventional contact window short circuit. Figures 2A to 2E are cross-sectional views showing a process of a method for preventing the barrier layer from being over-etched according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10, 100 ~ semiconductor silicon substrate; 12 ~ interlayer dielectric layer; 14 ~ barrier layer; G ~ gate structure, 16 ~ contact window; 102 ~ doped region; 10 4 ~ spacer wall; 106 ~ gate structure; 108 ~ barrier layer; 120 ~ protection dielectric layer; 122 ~ interlayer dielectric layer 1 24 ~ contact window.

0593-9221twf (nl); 91070tw; phoebe.ptd Page 10

Claims (1)

575917 6. Method for preventing patents from being excessively etched, including: providing a semiconductor substrate formed with a plurality of gate structures; compliantly forming a barrier layer to cover the gate structures; compliant Forming a protective dielectric layer on the barrier layer; and an interlayer dielectric layer covering the gate structures and filling the structures. Μ t ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ The protective layer described in item 1 above is to prevent the barrier layer from being over-exposed # 2 ΐ ^ ^ also includes the formation of a source / drain region between the gate electrodes on the semiconductor substrate. 3 · As claimed in the patent application] Fang 丨 Recognition 7. Preventing the barrier layer from being over-explained as described in item 1 of # 1. # 4 / You 4 barrier layer is nitrogen oxides (0 father and 1 ^ 1: 1 ^ (16). 4 · The method for preventing the barrier layer from being excessively engraved for 14 minutes as described in the patent application 1 t \\ ^ ^ rtr member, wherein the protection refers to thunder). The electrical layer is an undoped silicon glass (USG 5) The method as described in the scope of the patent application, wherein the protective medium and the barrier layer are prevented from being over-etched. 6. The scope of the patent application is the second! Borosilicate glass (BSG). A method of engraving, in which the interlayer dielectric 屛, to prevent the obstruction of the early layer is excessive. 7. A contact window is formed; ^ Phosphophosphite glass (BPSG). Provides a formation of a plurality of The steps of each gate include: forming a semiconducting Q structure of the source / drain doped region, and the compliance between the gate structures forms a barrier layer f body substrate; the compliance forms a protectionϋ These gate structures; forming an inter-layer dielectric layer covering; = edge barrier layer, special gate structure and filling these gates 0593-9221twf (nl); 91070tw; phoebe.ptd $ 11 pages Between structures; and iJs L '^ dielectric layer, protection ^: etch :? Except for the interlayer / drain doped regions between the gate structures. A contact window is formed by θ P layer to expose the above source, wherein the resistance: 々Η j [f: f The method for forming a contact window as described in item 7, θ is oxynitride.中 中 二! Ϊ́ The method of forming a contact window as described in item 7 of the scope of interest, "Dry violation guarantees that the remote interface layer is undoped silica glass (USG). The method of forming a contact window ', the u protective dielectric layer is borosilicate glass (BSG). · The method of forming a contact window as described in item 7 of the scope of patent application', wherein the interlayer dielectric layer is borophosphosilicate glass (BpSG). A semiconductor structure that prevents the barrier layer from being over-etched, including: a semiconductor substrate; a plurality of gate structures formed on the semiconductor substrate; a barrier layer formed on the compliance A semiconductor substrate and the gate structures; a protective dielectric layer formed on the barrier layer; and an interlayer dielectric layer formed on the barrier layer and filled between the gate structures. 3. The semiconductor structure for preventing the barrier layer from being over-etched as described in item 12 of the scope of patent application, wherein the barrier layer is an oxynitride. Barrier 0593-9221twf (nl); 91070tw; phoebe.ptd Page 12 575917 VI. Patent-etched semiconductor structure, in which the protective dielectric layer is undoped silicon glass (USG) 〇1 5.If the scope of patent application The semiconductor structure for preventing the barrier layer from being over-etched according to item 12, wherein the protective dielectric layer is borosilicate glass (BSG) ° 1 6. The barrier for preventing layer according to item 12 of the scope of patent application An over-etched semiconductor structure, wherein the interlayer dielectric layer is borophosphosilicate glass (BPSG). 0593-9221twf (nl); 91070tw; phoebe.ptd Page 13