CN1348141A - Discrete 3780-point Fourier transformation processor system and its structure - Google Patents
Discrete 3780-point Fourier transformation processor system and its structure Download PDFInfo
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- CN1348141A CN1348141A CN 01140060 CN01140060A CN1348141A CN 1348141 A CN1348141 A CN 1348141A CN 01140060 CN01140060 CN 01140060 CN 01140060 A CN01140060 A CN 01140060A CN 1348141 A CN1348141 A CN 1348141A
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Abstract
3780 points discrete Fourier transform processer system includes 63 points DFT module, complex multiplicator moduel, line and column crossing processor module and 60 points DFT module to be connected in sequence according to the calculation, of which the position of each module in the abovelisted modules can be interchangeable. The processor is structuralized by two modules in front and back to share one FPGA chip and two FPGA chips being connected by two-part RAM. According to the calculation and connecting sequence 63 point DFT module will be formed by 7 point (or 9 point) DFT module-label mapping module under 63 point DFT prime factor calculation-9 point (or 7 point) DFT module, 60 point DFT module can be also decomposed similarly as 3X20, 4X15, 5X12 point DFT as well as 12 point and 15 point DFT module can be decomposed as 3X4, 3X5 point DFT module. The whole 3780 point DFT processor needs only two FPGA chips of three hundred thousand gates for saving a great deal of the cost.
Description
Technical field
A kind of 3780 DFT (discrete Fourier transformation) processor systems and structure thereof belong to the hardware of DFT fast algorithm and realize, particularly multi-carrier signal DFT processor system technical field.
Background technology
The present invention relates to DFT application in the orthogonal frequency multi-carrier modulation demodulation techniques in the communication technology.In order to realize the orthogonal frequency multi-carrier modulation, need and to carry out discrete fourier inverse transformation (IDFT) to obtain the subcarrier of OFDM multi-carrier modulation usefulness through the single carrier baseband signal of quadrature phase modulation.Separating timing, multi-carrier signal carried out discrete Fourier transformation, obtaining the code element of information again through quadrature phase demodulation to obtain single carrier baseband signal through the quadrature phase modulation.According to digital signal processing theory, DFT can realize by IDFT.The IDFT computing of ordering for N, the method that realizes with DFT is exactly: at first the input data are got complex conjugate, through the DFT computing, operation result got complex conjugate again and the result divided by N, just can obtain the operation result of IDFT.So the fast algorithm that calculates DFT that is useful on also can be used for IDFT simultaneously and calculates.This shows that the DFT processor is its core processing unit in the hardware of orthogonal frequency multi-carrier modulation demodulating system is realized.During realization, its resource consumption is that the hundreds of thousands door arrives doors up to a million, and the DFT processor takies the very big proportion of hardware resource.So it is to reducing system cost, the application of promoting orthogonal frequency multi-carrier modulation demodulating system is significant.
3780 DFT processors only are used for the digital TV ground transmission scheme that Tsing-Hua University proposes at present, and it has adopted the orthogonal frequency multi-carrier modulation technology with 3780 subcarriers.3780 DFT modules that it adopts realize with 3 400,000 FPGA in model machine, hardware resource consumption is big, cost is higher, its reason is that 3780 DFT calculate like this: at first 3780 DFT are decomposed into 3 DFT and 1260 DFT, ranks interleaving treatment and twiddle factor multiplication by 3 * 1260 are combined to; Wherein 1260 DFT are decomposed into 3 DFT and 420 DFT again, and ranks interleaving treatment and twiddle factor multiplication by 3 * 420 are synthesized; Wherein 420 DFT are decomposed into 4 DFT and 35 DFT again, and ranks interleaving treatment and twiddle factor multiplication by 4 * 35 are synthesized; Wherein 35 DFT are decomposed into 5 DFT and 7 DFT again, and ranks interleaving treatment and twiddle factor multiplication by 5 * 7 combine.Hardware consumption in the computation process is except small point DFT computing unit, used the storage space that adds up to 3780+1260+420+35=5635 complex digital to interweave as ranks, with 5 twiddle factor multipliers be complex multiplier, it is equivalent to 20 real multipliers and adds up to the twiddle factor coefficient memory of 5635 complex digital.Its system architecture block scheme is seen Fig. 1.
Summary of the invention
The object of the present invention is to provide a kind of hardware consumption seldom and computing 3780 DFT processor systems and structure thereof faster.
3780 DFT processor systems that the present invention proposes is characterized in that:
According to the computing and the order of connection shown in the following arrow, it adopts any in the following system:
(1) 63 DFT module → complex multiplier module → ranks amount of interleaver module → 60 DFT module;
(2) 63 DFT module → ranks amount of interleaver module → complex multiplier module → 60 DFT modules;
(3) 60 DFT module → complex multiplier module → ranks amount of interleaver module → 63 DFT modules;
(4) 60 DFT module → ranks amount of interleaver module → complex multiplier module → 63 DFT modules;
Wherein, 63 and 60 DFT modules be a kind of will be by 7,9 or 3,4,5 DFT modules of decomposing of small point.
The structure of 3780 DFT processor systems that the present invention proposes, it is characterized in that: according to the computing and the order of connection shown in the above-mentioned arrow, in above-mentioned any system, the shared chip FPGA of front two modules, shared another chip of next two modules FPGA, the centre connects with dual port RAM.
Wherein, described 63 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 9 of the prime factor algorithm of (1) 7 DFT module → 63 a DFT DFT module;
Subscript mapping block → 7 of the prime factor algorithm of (2) 9 DFT module → 63 a DFT DFT module.
Described 60 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 20 of the prime factor algorithm of (1) 3 DFT module → 60 a DFT DFT module:
Subscript mapping block → 3 of the prime factor algorithm of (2) 20 DFT module → 60 a DFT DFT module;
Subscript mapping block → 15 of the prime factor algorithm of (3) 4 DFT module → 60 a DFT DFT module;
Subscript mapping block → 4 of the prime factor algorithm of (4) 15 DFT module → 60 a DFT DFT module;
Subscript mapping block → 12 of the prime factor algorithm of (5) 5 DFT module → 60 a DFT DFT module;
Subscript mapping block → 5 of the prime factor algorithm of (6) 12 DFT module → 60 a DFT DFT module.
Described 12 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 4 of the prime factor algorithm of (1) 3 DFT module → 12 a DFT DFT module;
Subscript mapping block → 3 of the prime factor algorithm of (2) 4 DFT module → 12 a DFT DFT module.
Described 15 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 5 of the prime factor algorithm of (1) 3 DFT module → 15 a DFT DFT module;
Subscript mapping block → 3 of the prime factor algorithm of (2) 5 DFT module → 15 a DFT DFT module.
Described 20 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 5 of the prime factor algorithm of (1) 4 DFT module → 20 a DFT DFT module;
Subscript mapping block → 4 of the prime factor algorithm of (2) 5 DFT module → 20 a DFT DFT module.
Use proof: it has reached purpose of design.
Description of drawings
Fig. 1: the structured flowchart of existing 3780 DFT disposal systems.
Fig. 2～Fig. 5: the structured flowchart of four kinds of 3780 different DFT disposal systems that the present invention proposes.
Fig. 6～Fig. 7: the structured flowchart of 2 kinds of 63 different DFT modules that the present invention proposes.
Fig. 8～Figure 13: the structured flowchart of 6 kinds of 60 different DFT modules that the present invention proposes.
Figure 14～Figure 15: the structured flowchart of 2 kinds of 12 different DFT modules that the present invention proposes.
Figure 16～Figure 17: the structured flowchart of 2 kinds of 15 different DFT modules that the present invention proposes.
Figure 18～Figure 19: the structured flowchart of 2 kinds of 20 different DFT modules that the present invention proposes.
Figure 20: the circuit system theory diagram of a kind of 3780 DFT disposal systems that the present invention proposes.
Figure 21: the hardware structure diagram of a kind of 3780 DFT disposal systems that the present invention proposes.
Figure 22: the schematic block circuit diagram of the subscript mapping block of the DFT prime factor algorithm that the present invention proposes.
Figure 23: the schematic block circuit diagram of any one DFT module of counting in 3,5,7,9 of the present invention's proposition.
Embodiment
Asking for an interview Fig. 2～Fig. 5, is example with 63 DFT modules → complex multiplier module → ranks amount of interleaver module → 60 these DFT disposal systems of DFT module, and its calculation step is illustrated;
(1) input data sequence carries out 63 DFT computings;
(2) to carrying out complex multiplication operation through the data after the step (1);
(3) to the data procession interleaving treatment computing after the process step (2);
(4) to carrying out 60 DFT computings through the data of step (2) and (3).
Ask for an interview Fig. 6～Fig. 7: existing these 63 DFT modules of subscript mapping block → 9 a DFT module with 7 DFT module → 63 DFT prime factor algorithm are that example describes its calculation step:
(1) the input data are carried out 7 DFT computings earlier;
(2) data through step (1) are carried out the data line rearrangement with the subscript mapping block of 63 DFT prime factor algorithms;
(3) data of resetting through step (2) are carried out 9 DFT computings.
Ask for an interview Fig. 8～Figure 13: the calculation step of its various modular structures is similar to 63 DFT modules, no longer repeats.
Ask for an interview Figure 14～Figure 15, Figure 16～Figure 17 and Figure 18～19, the calculation step of its various sub modular structures is similar with 63 DFT modules also, no longer repeats.
Ask for an interview Figure 20: this is the schematic block circuit diagram of the system of a kind of 63 DFT modules → ranks amount of interleaver simulation → complex multiplier module → 60 DFT module formations, and other system is similar to it.Wherein the modular structure of 63 DFT modules is: subscript mapping block → 9 a DFT module of 7 DFT module → 63 DFT prime factor algorithms; The modular structure of 60 DFT modules is: subscript mapping block → 4 a DFT module of DFT module → 60, subscript mapping block → 5 a DFT prime factor algorithm of 3 DFT module → 15 DFT prime factor algorithms.
Ask for an interview Figure 21: this is the hardware structure diagram of DFT processor system of the present invention.Read/write address that contains in 63 (or 60) some DFT module and the ranks interleaving treatment module and read-write control signal produce the shared chip FPGA of circuit, the complex multiplier module contains the twiddle factor coefficient memory that plural musical instruments used in a Buddhist or Taoist mass and output terminal link to each other with above-mentioned complex multiplier, above-mentioned complex multiplier module and shared another chip of 60 (or 63) some DFT module FPGA, their model all is VirtexE XCV300E.The dual port RAM that is MCM69D618TQ6 with a model between two FPGA links to each other.Each data of N data to be transformed are through 63 DFT unit of 1～M bar data line DATA input, and the latter produces circuit to 63 DFT operation results through 1～M bar data line DATA and read/write address and read-write control signal and writes dual port RAM.It is that 1～14 address wire ADDR by dual port RAM writes 2 under latter's write order WR control
14In the individual address location.Then, produce under the read command RD control of circuit, at read/write address and read-write control signal from 2
14In the individual address 1～N data are read through data line DATA and be sent to complex multiplier, above-mentioned complex multiplier makes both make plural multiplication take out 1～N twiddle factor ROTATOR from the twiddle factor storer under control signal after, 1～N product data are sent to 60 DFT modules through complex multiplier 1～M bar data line DATA do 60 DFT computings, its result as conversion after data totally 1～N export by data line DATA.
Figure 22 is the schematic block circuit diagram of subscript mapping block.It contains: import/go out the storer that end links to each other with 1～m bar data sense wire DATA READ with 1～m bar data writing line DATA WRITE respectively, under start signal START control, after above-mentioned storer sends the write control circuit of write order WR, write address order WR ADDRESS and receiving the enabling signal of write control circuit, can send sense order READ, read the control circuit of reading of address instruction RD ADDRESS to above-mentioned storer.After reading end, the above-mentioned control circuit of reading sends the instruction START NEXT that starts next program.
Goodbye Figure 23: it is the schematic block circuit diagram of small point as 3,5,7,9 DFT modules.It is to adopt Winograd algorithm commonly used in the digital signal processing to realize.Its formulation formula is X (k)=ODI * (n), I matrix and O matrix be only by-1,0,1 three kind of ordinary matrix that element constitutes, I matrix and O matrix and certain vectorial product can each be realized with the totalizer group; The D matrix is a diagonal matrix, and the element on its diagonal line is real number or pure imaginary number, and complex multiplication just can be finished by two real multipliers, and whole diagonal matrix multiplying can produce submodule and two real multipliers realizations by multiplication coefficient, as shown in figure 23.After the data input totalizer group 1, produce and the add-subtract control logical circuit sends to totalizer group 1 and enables control signal EN and add-subtract control logical signal AS to finish the I matrix multiplication by the I matrix coefficient, its output is sent into two general purpose multipliers to finish the diagonal matrix multiplication through multi-channel gating device 1, its output is transported to totalizer group 2, produce and the add-subtract control logical circuit sends enables to finish the O matrix multiplication under control signal EN and the add-subtract control logical signal AS at the O matrix coefficient, finally export its DFT results through multi-channel gating device 2.The difference of 3,5,7,9 DFT only is the coefficient difference of O, I, D, 4 DFT can be expressed as X (k)=A * (n), the A matrix is ordinary matrix, 4 DFT can be produced and the add-subtract control logical circuit constitutes by one group of totalizer and ordinary coefficient, and the I matrix among its schematic block circuit diagram and Figure 23 or the schematic block circuit diagram of O matrix are identical.
This shows, the present invention has only used the storage space that adds up to 3780+63+60+15=3918 complex digital to interweave as ranks and the mapping of prime factor algorithm subscript is used, also has a twiddle factor multiplier, be equivalent to the twiddle factor coefficient memory that 4 real multipliers and capacity are 3780 complex digital, wherein the complicacy of the subscript mapping block of DFT prime factor algorithm is mainly by the storer decision, because the resource consumption of its read-write control unit seldom.Except the small point DFT module, the present invention has been equivalent to save 30% storage space and 80% real multipliers.Because each real multipliers need consume nearly 10,000 approximately, prior art is used 3 400,000 FPGA, be equivalent to use 1,200,000 logical resource, and the present invention only uses 2 300,000 FPGA, be equivalent to use 600,000 logical resource, and with main storage resource consumption, i.e. the storer of needed 3780 complex digital of 63 * 60 ranks interleaving treatment modules, from the FPGA of costliness, put forward to realize that with more cheap relatively twoport PAM cost can descend greatly.
Claims (8)
1. one kind 3780 DFT (discrete Fourier transformation) processor system contains the DFT module, complex multiplier module and ranks amount of interleaver module, it is characterized in that: according to the computing and the order of connection shown in the following arrow, it adopts any in the following system:
(1) 63 DFT module → complex multiplier module → ranks amount of interleaver module → 60 DFT module;
(2) 63 DFT module → ranks amount of interleaver module → complex multiplier module → 60 DFT modules;
(3) 60 DFT module → complex multiplier module → ranks amount of interleaver module → 63 DFT modules;
(4) 60 DFT module → ranks amount of interleaver module → complex multiplier module → 63 DFT modules;
Wherein, 63 and 60 DFT modules be a kind of will be by 7,9 or 3,4,5 DFT modules of decomposing of small point.
2,3780 system architectures that the DFT processor system is designed according to claim 1, it is characterized in that: according to the computing and the order of connection shown in the above-mentioned arrow, in above-mentioned any system, the shared chip FPGA of front two modules, shared another chip of next two modules FPGA, the centre connects with dual port RAM.
3,3780 DFT processor systems according to claim 1 is characterized in that: described 63 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 9 of the prime factor algorithm of (1) 7 DFT module → 63 a DFT DFT module;
Subscript mapping block → 7 of the prime factor algorithm of (2) 9 DFT module → 63 a DFT DFT module.
4,3780 DFT processor systems according to claim 1 is characterized in that: described 60 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 20 of the prime factor algorithm of (1) 3 DFT module → 60 a DFT DFT module:
Subscript mapping block → 3 of the prime factor algorithm of (2) 20 DFT module → 60 a DFT DFT module;
Subscript mapping block → 15 of the prime factor algorithm of (3) 4 DFT module → 60 a DFT DFT module;
Subscript mapping block → 4 of the prime factor algorithm of (4) 15 DFT module → 60 a DFT DFT module;
Subscript mapping block → 12 of the prime factor algorithm of (5) 5 DFT module → 60 a DFT DFT module;
Subscript mapping block → 5 of the prime factor algorithm of (6) 12 DFT module → 60 a DFT DFT module.
5, according to claim 1 or 4 described DFT disposal systems, it is characterized in that: described 12 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 4 of the prime factor algorithm of (1) 3 DFT module → 12 a DFT DFT module;
Subscript mapping block → 3 of the prime factor algorithm of (2) 4 DFT module → 12 a DFT DFT module.
6, according to claim 1 or 4 described DFT disposal systems, it is characterized in that: described 15 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 5 of the prime factor algorithm of (1) 3 DFT module → 15 a DFT DFT module;
Subscript mapping block → 3 of the prime factor algorithm of (2) 5 DFT module → 15 a DFT DFT module.
7, according to claim 1 or 4 described DFT disposal systems, it is characterized in that: described 20 DFT modules are by the computing and the order of connection shown in the following arrow, and it adopts any in the following modular structure:
Subscript mapping block → 5 of the prime factor algorithm of (1) 4 DFT module → 20 a DFT DFT module;
Subscript mapping block → 4 of the prime factor algorithm of (2) 5 DFT module → 20 a DFT DFT module.
8,3780 DFT disposal systems according to claim 1 and 2 and structure thereof is characterized in that: it is the chip of VirtexE XCV300E that described FPGA adopts model.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1750206A1 (en) | 2005-08-04 | 2007-02-07 | THOMSON Licensing | 3780-point Discrete Fourier Transformation processor |
| CN1909548B (en) * | 2002-10-02 | 2010-11-03 | 三星电子株式会社 | Multicarrier system with 3780-point IDFT/DFT processor and method therefor |
| CN101136891B (en) * | 2007-08-09 | 2011-12-28 | 复旦大学 | 3780-point quick Fourier transformation processor of pipelining structure |
| CN102880591A (en) * | 2012-08-02 | 2013-01-16 | 成都凯腾四方数字广播电视设备有限公司 | 3780-point discrete Fourier transformation processing method and circuit |
| CN101933012B (en) * | 2008-01-31 | 2013-07-17 | 高通股份有限公司 | Device and method for DFT calculation |
| CN103294642A (en) * | 2012-02-28 | 2013-09-11 | 中兴通讯股份有限公司 | DFT (discrete Fourier transform)/IDFT (inverse discrete Fourier transform) processing method and processor |
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| CN108111458A (en) * | 2017-12-29 | 2018-06-01 | 中山大学花都产业科技研究院 | A kind of inverse Fourier transform algorithm applied to NB-IoT |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1909548B (en) * | 2002-10-02 | 2010-11-03 | 三星电子株式会社 | Multicarrier system with 3780-point IDFT/DFT processor and method therefor |
| EP1750206A1 (en) | 2005-08-04 | 2007-02-07 | THOMSON Licensing | 3780-point Discrete Fourier Transformation processor |
| CN1909529B (en) * | 2005-08-04 | 2012-05-09 | 汤姆逊许可公司 | 3780-point discrete fourier transformation processor |
| CN101136891B (en) * | 2007-08-09 | 2011-12-28 | 复旦大学 | 3780-point quick Fourier transformation processor of pipelining structure |
| CN101933012B (en) * | 2008-01-31 | 2013-07-17 | 高通股份有限公司 | Device and method for DFT calculation |
| CN103294642A (en) * | 2012-02-28 | 2013-09-11 | 中兴通讯股份有限公司 | DFT (discrete Fourier transform)/IDFT (inverse discrete Fourier transform) processing method and processor |
| CN102880591A (en) * | 2012-08-02 | 2013-01-16 | 成都凯腾四方数字广播电视设备有限公司 | 3780-point discrete Fourier transformation processing method and circuit |
| CN102880591B (en) * | 2012-08-02 | 2015-10-21 | 成都凯腾四方数字广播电视设备有限公司 | Leaf transformation disposal route and circuit in a kind of 3780 point discrete Fouriers |
| CN108037765A (en) * | 2017-12-04 | 2018-05-15 | 国网山东省电力公司电力科学研究院 | A kind of unmanned plane obstacle avoidance system for polling transmission line |
| CN108111458A (en) * | 2017-12-29 | 2018-06-01 | 中山大学花都产业科技研究院 | A kind of inverse Fourier transform algorithm applied to NB-IoT |
| CN112822139A (en) * | 2021-02-04 | 2021-05-18 | 展讯半导体(成都)有限公司 | Data input and data conversion method and device |
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