CN1909548B - Multicarrier system with 3780-point IDFT/DFT processor and method therefor - Google Patents
Multicarrier system with 3780-point IDFT/DFT processor and method therefor Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
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- H04L27/2626—Arrangements specific to the transmitter only
- H04L27/2627—Modulators
- H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
- H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2602—Signal structure
- H04L27/2605—Symbol extensions, e.g. Zero Tail, Unique Word [UW]
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Abstract
An OFDM(Orthogonal Frequency Division Multiplexing) system having a 3780-point IDFT(Inverse Discrete Fourier Transform)/DFT(Discrete Fourier Transform) processor and a structure of the 3780-point IDFT/DFT processor are provided to improve the structure of the 3780-point IDFT/DFT processor to be used efficiently in a transmitter and in a receiver. CONSTITUTION: A FEC(Forward Error Correction) part(120) codes an OFDM signal in a frequency domain to sense an error in a receiver side and to correct the error. A mapping part(210) maps the coded OFDM signal in the frequency domain by a mapping method. A 3870-point IDFT processor modulates the OFDM signal in the frequency domain into an OFDM signal in a time domain using a DFT module. And a guard interval insertion part(240) inserts a guard interval to the OFDM signal in the time domain. The 3870-point IDFT processor is constituted with one assembly among an assembly of a 252-point DFT module and a 15-point DFT module, an assembly of a 315-point DFT module and a 12-point DFT module and an assembly of a 420-point DFT module and a 9-point DFT module.
Description
The application be that March 17, application number in 2003 are 03107204.6 the applying date, denomination of invention divides an application for the application for a patent for invention of " multicarrier system and method thereof with 3780 IDFT/DFT processors ".
Technical field
The present invention relates to a kind of multi-carrier digital broadcast system and method thereof, more particularly, relate to and a kind ofly have 3780 the multicarrier transmission of IDFT/DFT (contrary discrete Fourier transform (DFT)/discrete Fourier transform (DFT)) processor and receiving system, a kind ofly be used to have 3780 the multicarrier method of sending and receiving of IDFT/DFT processor and the structure of 3780 IDFT/DFT processors.
Background technology
OFDM (OFDM) is one of multi-carrier modulation method, and it has good performance under multipath and mobile condition of acceptance.
The OFDM method uses a plurality of carrier waves that have orthogonality mutually to improve frequency utilization efficient.When use was used for the multicarrier means of cable or wireless channel, the OFDM method was suitable for high data rate transfers.When using the single carrier means to come to send when having at interval high data rate of short code unit,, improve in the complexity of receiving terminal along with the aggravation of the interference between code element by radio communication channel with multipath fading.On the other hand, because the multicarrier means can extend to the symbol interval of each subcarrier the quantity of subcarrier and keep data transmission rate simultaneously, therefore by using the equalizer that simply has a tap, can easily tackle the serious frequency Selective Fading Channel that causes owing to multipath.
In the OFDM method, use, in order to improve frequency utilization efficient, mutually have a plurality of carrier waves of orthogonality can be by carrying out IFFT/FFT (contrary fast fourier transform/fast fourier transform) at transmissions/receiving terminal by high velocity modulation/demodulation, described execution IFFT/FFT has the identical result with execution IDFT/DFT (against discrete Fourier transform (DFT)/discrete Fourier transform (DFT)).
Figure 1A is the functional-block diagram that one of TDS-OFDM (Domain Synchronous-OFDM) transmitting system or OFDM transmission system are shown.Figure 1B is the functional-block diagram that one of a TDS-OFDM receiving system or OFDM receiving system are shown.
Referring to Figure 1A, described TDS-OFDM transmitting system comprises: FEC (forward error correction) unit 11 is used for coded data so that make receiving terminal detect and the correction mistake; Map unit 21 is used to utilize QPSK (quadriphase PSK), 16QAM (quadrature amplitude modulation) and 64QAM to wait the data of mapping code; 3780 IDFT unit 31 are used for frequency domain ofdm signal is modulated to time domain OFDM signal; Protection is at interval inserted unit 41, is used for inserting before ofdm signal the GI (protection at interval) that the afterbody by modulated ofdm signal constitutes, so that prevent the ISI (inter symbol interference) under the multipath situation; Synchronizing information is inserted unit 51, is used for inserting a synchronizing signal before time-domain signal, and this is a feature of TDS-OFDM method; Shaping filter unit 61, the synchronizing information that is used for the shaping filter insertion is so that shaping pulse; RF (radio frequency) unit 71 is used for sending ofdm signal on desired band.
Fig. 2 A is the more detailed block diagram that 3780 IDFT unit 31 among Figure 1A are shown.3780 IDFT modules of 3780 IDFT unit 31 are divided into 60 * 63 or 63 * 60 module, and it is constituted by 60 IDFT modules and 63 IDFT, module, on the contrary or order.
Shown in Fig. 2 A, 3780 IDFT unit 31 comprise: 60 IDFT modules 311 are used for the input data are carried out 60 IDFT; Complex multiplier 312, the data that are used for carrying out 60 IDFT multiply by a plural number; Matrix interleaver 313 is used for that the data of product are carried out matrix and interweaves; 63 IDFT modules 314, the data that are used for described matrix is interweaved are carried out 63 IDFT.At this, their order that can allow that complex multiplier 312 and matrix interleaver 313 change.Similarly, also can allow 60 IDFT modules 311 and 63 IDFT module 314 their orders of change.
Owing to only utilizing 60 IDFT modules 311 and 63 IDFT modules 314 to design 3780 IDFT unit 31 of above-mentioned tradition, therefore there is a shortcoming, promptly can not carry out IDFT to the number except 3780 greater than 63.
Figure 1B is the functional-block diagram that traditional TDS-OFDM receiving system is shown.Described TDS-OFDM receiving system comprises: antenna 82, I/Q generator 12, synchronized signal detector 22, demultiplexer 32, a DFT unit 42, the 2nd DFT unit 52, channel compensator 62 and FEC unit 72.
I/Q generator 12 produces baseband I/Q signal from the signal that receives via antenna 82.Synchronized signal detector 22 detects the PN sequence start bit and puts.Demultiplexer 32 is divided into PN sequence, protection interval and ofdm signal with baseband I/Q signal.The 42 pairs of PN sequences in the one DFT unit are carried out DFT, and the 52 pairs of ofdm signals in DFT unit are carried out DFT.Channel compensator 62 compensate for channel effects.Error signal is corrected in FEC unit 72.
Fig. 2 B illustrates 3780 DFT unit 42 among Figure 1B and 52 more detailed block diagram.
Shown in Fig. 2 B, a DFT unit 42 comprises: 60 DFT modules 321 are used for the data of input are carried out 60 DFT; Complex multiplier 322, the data that are used for carrying out 60 DFT multiply by a plural number; Matrix interleaver 323 is used for that the data of product are carried out matrix and interweaves; 63 DFT modules 324, the data that are used for described matrix is interweaved are carried out 63 DFT.At this, their order that can allow that complex multiplier 322 and matrix interleaver 323 change.Similarly, also can allow 60 DFT modules 321 and 63 DFT module 324 their orders of change.
Owing to only utilizing 60 DFT modules 321 and 63 DFT modules 324 to design 3780 DFT unit of above-mentioned tradition, therefore there is a shortcoming, promptly can not carry out DFT to the number except 3780 greater than 63.Require receiving terminal that length is carried out DFT from 250 o'clock to 420 o'clock PN (pseudo noise) sequence, so that measured channel more accurately.Further require the receiving terminal DFT module new, or in 3780 DFT, insert 0 and fill, therefore cause efficient low so that the PN sequence is carried out DFT with respect to the PN sequences Design.
Summary of the invention
Therefore, in order to address the above problem and/or shortcoming, an object of the present invention is to provide a kind of multicarrier transmitting system and a kind of multicarrier receiving system, they have 3780 IDFT/DFT processors that improve structure, are used for receiving terminal and transmitting terminal.
According to one aspect of the present invention, a kind of multicarrier transmitting system comprises: the FEC unit is used to the frequency domain ofdm signal of encoding, so that make receiving terminal detect and the correction mistake; Map unit is used for coming according to the predetermined mapped method frequency domain ofdm signal of mapping code; 3780 IDFT processors are used to utilize the IDFT module that frequency domain ofdm signal is modulated to time domain OFDM signal; Protection is at interval inserted the unit, is used for inserting protection at interval before described time domain OFDM signal, and it is one of following that wherein said 3780 IDFT processors comprise: the combination of 84 IDFT modules and 45 IDFT modules; The combination of 105 IDFT modules and 36 IDFT modules; The combination of 180 IDFT modules and 21 IDFT modules; The combination of 252 IDFT modules and 15 IDFT modules; The combination of 315 IDFT modules and 12 IDFT modules; The combination of 420 IDFT modules and 9 IDFT modules; The combination of 1260 IDFT modules and 3 IDFT modules.
According to another aspect of the present invention, a kind of multi-carrier transmission method comprises step: the coding frequency domain ofdm signal, so that make receiving terminal detect and the correction mistake; Come the frequency domain ofdm signal of mapping code according to the predetermined mapped method; Utilize 3780 IDFT processors that frequency domain ofdm signal is modulated to time domain OFDM signal; Inserted protection at interval before described time domain OFDM signal, it is one of following that wherein said 3780 IDFT processors comprise: the combination of 84 IDFT modules and 45 IDFT modules; The combination of 105 IDFT modules and 36 IDFT modules; The combination of 180 IDFT modules and 21 IDFT modules; The combination of 252 IDFT modules and 15 IDFT modules; The combination of 315 IDFT modules and 12 IDFT modules; The combination of 420 IDFT modules and 9 IDFT modules; The combination of 1260 IDFT modules and 3 IDFT modules.
According to another aspect of the present invention, a kind of multicarrier receiving system comprises: the I/Q generator is used for producing baseband I/Q signal from the signal that is received; Synchronized signal detector is used for detecting and puts at the PN of described baseband I/Q signal sequence start bit, and provides demultiplexing control signal and many output to select signal; Demultiplexer is used for according to described demultiplexing control signal described baseband I/Q signal being divided into PN sequence, protection interval and ofdm signal; Multiplexer is used for selecting signal multiplexing PN sequence and ofdm signal from described demultiplexer output according to described many outputs; Many output DFT unit, be used for carrying out operating from the ofdm signal of described multiplexer output and the DFT of PN sequence according to many output DFT input signals, wherein said many output DFT unit comprises the 3780DFT processor, the ofdm signal that is used for inserting PN sequence or Domain Synchronous information is demodulated into frequency domain ofdm signal, wherein said 3780 DFT processors comprise K point DFT module and M point DFT module, at this 3780=K * M, and the output signal of 3780 DFT processors according to selecting control signal from or K point DFT module or M point DFT module.
According to another aspect of the present invention, a kind of multicarrier receiving method comprises step: produce baseband I/Q signal from the signal that is received; The PN sequence start bit of detection in described baseband I/Q signal put, and provides demultiplexing control signal and many output to select signal; According to described demultiplexing control signal described baseband I/Q signal is divided into PN sequence, protection interval and ofdm signal; Select multiplexing described PN sequence of signal and ofdm signal according to described many outputs; The DFT that utilizes the DFT of output more than one unit to carry out ofdm signal and PN sequence according to many output DFT input signals operates, wherein said many output DFT unit comprises the 3780DFT processor, the ofdm signal that is used for inserting PN sequence or Domain Synchronous information is demodulated into frequency domain ofdm signal, wherein said 3780 DFT processors comprise K point DFT module and M point DFT module, at this 3780=K * M, and the output signal of 3780 DFT processors according to selecting control signal from or K point DFT module or M point DFT module.
Because the design of above-mentioned 3780 IDFT/DFT processors is to utilize multiple combination rather than the only combination of 60 IDFT/DFT modules and 63 IDFT/DFT modules, so it has an advantage and is and might carries out IDFT/DFT to the number greater than 63 except 3780.
And 3780 above-mentioned IDFT/DFT processors can be carried out IDFT/DFT from 250 o'clock to 420 o'clock PN (pseudo noise) sequence to length, so that measured channel more accurately.Therefore can not provide a new IDFT/DFT module at receiving terminal, perhaps in 3780 IDFT/DFT, do not insert 0 and fill, therefore improved efficient PN sequence execution IDFT/DFT at the PN sequence.
Description of drawings
To describe the present invention in detail by the reference accompanying drawing, wherein identical Reference numeral is represented components identical, wherein:
Figure 1A is the functional-block diagram that traditional TDS-OFDM transmitting system is shown;
Figure 1B is the functional-block diagram that traditional TDS-OFDM receiving system is shown;
Fig. 2 A is the structure that is illustrated in 3780 IDFT processors among Figure 1A;
Fig. 2 B is the structure that is illustrated in 3780 DFT processors among Figure 1B;
Fig. 3 A illustrates the functional-block diagram that has the TDS-OFDM transmitting system of improved 3780 IDFT processors according to of the present invention;
Fig. 3 B illustrates the functional-block diagram that has the TDS-OFDM receiving system of improved 3780 DFT processors according to of the present invention;
Fig. 4 A is the functional-block diagram that the structure of 3780 IDFT processors is shown;
Fig. 4 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors of one embodiment of the present of invention;
Fig. 5 A is the functional-block diagram that the structure of 3780 IDFT processors is shown;
Fig. 5 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors of an alternative embodiment of the invention;
Fig. 6 A is the functional-block diagram that the structure of 3780 IDFT processors is shown;
Fig. 6 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors of another embodiment of the present invention.
Embodiment
Below, be described according to a preferred embodiment of the present invention with reference to accompanying drawing.
Fig. 3 A illustrates the functional-block diagram that has the TDS-OFDM transmitting system of improved 3780 IDFT processors according to of the present invention.
The TDS-OFDM transmitting system comprises FEC (forward error correction) unit 100 and OFDM modulator 200.OFDM modulator 200 comprises that 210,3780 IDFT unit 400 of map unit, protection are inserted unit 240 at interval, synchronizing information is inserted unit 250, shaping filter unit 260 and RF unit 270.
Coding for receiving terminal is carried out to detect and to correct mistake in FEC unit 100.Map unit 210 is mapped as the I/Q constellation with the FEC coded data.
3780 IDFT unit 400 comprise that to 3780 sub-carrier allocation the frequency domain ofdm signal of 3780 parallel datas is so that therefore modulation exports the time domain OFDM signal that comprises 3780 data from the sample survey.3780 IDFT unit 400 are made of one of following combination:
1) combination of 84 IDFT modules and 45 IDFT modules,
2) combination of 105 IDFT modules and 36 IDFT modules,
3) combination of 180 IDFT modules and 21 IDFT modules,
4) combination of 252 IDFT modules and 15 IDFT modules,
5) combination of 315 IDFT modules and 12 IDFT modules,
6) combination of 420 IDFT modules and 9 IDFT modules, the structure of 3780 IDFT unit 400 that will describe in detail below,
7) combination of 1260 IDFT modules and 3 IDFT modules.
Protection is inserted unit 240 at interval and insert a GI when carrying out IDFT before the OFDM code element of exporting.Specifically, the GI that duplicates from the data from the sample survey of ofdm signal afterbody intercepting is inserted into before each ofdm signal so that prevent ISI under multipath conditions.
Synchronizing information is inserted unit 250 and is inserted a PN sequence in the GI front, and described PN sequence is to make receiving terminal realize the information of time synchronized and channel equalization.
The ofdm signal of the 260 pairs of insertions in shaping filter unit PN sequence carries out the shaping filter of PN sequence, and RF unit 270 sends it by the RF channel.
Fig. 3 B illustrates the functional-block diagram that has according to the TDS-OFDM receiving system of improved 3780 DFT processors of the present invention.The TDS-OFDM receiving system comprises antenna 600, I/Q generator 601, synchronized signal detector 602, demultiplexer 603, exports DFT unit 604, channel compensator 605, FEC unit 606 and multiplexer 607 more.
I/Q generator 601 produces baseband I/Q signal from the signal that receives via antenna 600.Synchronized signal detector 602 detects the starting position of PN sequence, and provides the demultiplexing control signal to demultiplexer 603, provides many outputs to select signal to multiplexer 607 and many output DFT unit 604.Demultiplexer 603 selects signal that baseband I/Q signal is divided into PN sequence, protection interval and ofdm signal according to described many outputs.Multiplexer 607 is selected PN sequence and the ofdm signal of signal multiplexing from demultiplexer 603 outputs according to described many outputs.The many output of described selection signal indication DFT input signal is PN sequence or ofdm signal.Many output DFT carry out the DFT operation for ofdm signal and PN sequence in unit 604.Channel compensator 605 compensate for channel effects.Error signal is corrected in FEC unit 606.
Below with reference to the structure of Fig. 4-6 explanation according to 3780 IDFT/DFT processors of embodiments of the invention.
By utilizing 3780=3 * 4 * 5 * 7 * 9,3780 IDFT/DFT modules can be by utilizing WFTA (Winograd fourier transform algorithm) the constituting by 3 IDFT/DFT modules, 4 IDFT/DFT modules, 5 IDFT/DFT modules, 7 IDFT/DFT modules and 9 IDFT/DFT modules of the little N that the smallest number multiplexer realizes.PFA (Prime Factor Algorithm, prime factor algorithm) and Coorley-Turkey algorithm can be used to make up each module.
That is, if module is separated from each other, can use the PFA that does not need plural multiplexer so, otherwise can use the Coorley-Turkey algorithm.
Fig. 4 A is the functional-block diagram that illustrates according to the structure of 3780 IDFT processors 410 of one embodiment of the present of invention, described 3780 IDFT processors 410 by the Coorley-Turkey algorithm combination 252 IDFT modules and 15 IDFT modules.
3780 IDFT processors 410 comprise: 252 IDFT modules 413 are used for the input data are carried out 252 IDFT; Plural number multiplexer 415, the data that are used for being transformed multiply by a plural number; Matrix interleaver 417 is used for that the product data are carried out matrix and interweaves; 15 IDFT modules 419, the data that are used for matrix is interweaved are carried out 15 IDFT.At this, can allow complex multiplier 415 and matrix interleaver 417 to change their order.
252 IDFT modules 413 can utilize PFA to be made of 4 IDFT modules, 7 IDFT modules and 9 IDFT modules, and 15 IDFT modules 419 can utilize PFA to be made of 3 IDFT modules and 5 IDFT modules.
At receiving terminal, can by select control signal from or 3780 IDFT processors 410 or 252 IDFT module 413 output signals.
Fig. 4 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors 710 of one embodiment of the present of invention, described 3780 DFT processors 710 by the Coorley-Turkey algorithm combination 252 DFT modules and 15 DFT modules.
3780 DFT processors 710 comprise: 252 DFT modules 713 are used for the input data are carried out 252 DFT; Complex multiplier 715, the data that are used for being transformed multiply by a plural number: matrix interleaver 717 is used for that the product data are carried out matrix and interweaves; 15 DFT modules 719, the data that are used for matrix is interweaved are carried out 15 DFT.At this, can allow complex multiplier 715 and matrix interleaver 717 to change their order.
252 DFT modules 713 can utilize PFA (prime factor algorithm) to be made of 4 DFT modules, 7 DFT modules and 9 DFT modules, and 15 DFT modules 719 can utilize PFA to be made of 3 DFT modules and 5 DFT modules.
Fig. 5 A is the functional-block diagram that illustrates according to the structure of 3780 IDFT processors of an alternative embodiment of the invention, and described 3780 IDFT processors utilize the Coorley-Turkey algorithm to be made of 315 IDFT modules and 12 IDFT modules.
3780 IDFT processors 420 comprise: 315 IDFT modules 423 are used for the input data are carried out 315 IDFT; Complex multiplier 425, the data that are used for being transformed multiply by a plural number; Matrix interleaver 427 is used for that the product data are carried out matrix and interweaves; 12 IDFT modules 429, the data that are used for matrix is interweaved are carried out 12 IDFT.At this, can allow complex multiplier 425 and matrix interleaver 427 to change their order.
315 IDFT modules 423 can utilize PFA to be made of 5 IDFT modules, 7 IDFT modules and 9 IDFT modules, and 12 IDFT modules 429 can utilize PFA to be made of 3 IDFT modules and 4 IDFT modules.
At receiving terminal, can by select control signal from or 3780 IDFT processors 420 or 315 IDFT module 423 output signals.
Fig. 5 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors of an alternative embodiment of the invention, and described 3780 DFT processors utilize the Coorley-Turkey algorithm to be made of 315 DFT modules and 12 DFT modules.
3780 DFT processors 720 comprise: 315 DFT modules 723 are used for the input data are carried out 315 DFT; Complex multiplier 725, the data that are used for being transformed multiply by a plural number; Matrix interleaver 727 is used for that the product data are carried out matrix and interweaves; 12 DFT modules 729, the data that are used for matrix is interweaved are carried out 12 DFT.At this, can allow complex multiplier 725 and matrix interleaver 727 to change their order.
315 DFT modules 723 can utilize PFA to be made of 5 DFT modules, 7 DFT modules and 9 DFT modules, and 12 DFT modules 729 can utilize PFA to be made of 3 DFT modules and 4 DFT modules.
Fig. 6 A is the functional-block diagram that illustrates according to the structure of 3780 IDFT processors of another embodiment of the present invention, and described 3780 IDFT processors utilize the Coorley-Turkey algorithm by 420 IDFT modules and 9 IDFT modules.
3780 IDFT processors 430 comprise: 420 IDFT modules 433 are used for the input data are carried out 420 IDFT; Complex multiplier 435, the data that are used for being transformed multiply by a plural number; Matrix interleaver 437 is used for that the product data are carried out matrix and interweaves; 9 IDFT modules 439, the data that are used for matrix is interweaved are carried out 9 IDFT.At this, can allow complex multiplier 435 and matrix interleaver 437 to change their order.
420 IDFT modules 433 can utilize PFA to be made of 3 IDFT modules, 4 IDFT modules, 5 IDFT modules and 7 IDFT modules.
At receiving terminal, can by select control signal from or 3780 IDFT processors 430 or 420 IDFT module 433 output signals.
Fig. 6 B is the functional-block diagram that illustrates according to the structure of 3780 DFT processors of another embodiment of the present invention, and described 3780 DFT processors are made of 420 DFT modules and 9 DFT modules by the Coorley-Turkey algorithm.
3780 DFT processors 730 comprise: 420 DFT modules 733 are used for the input data are carried out 420 DFT; Complex multiplier 735, the data that are used for being transformed multiply by a plural number; Matrix interleaver 737 is used for that the product data are carried out matrix and interweaves; 9 DFT modules 739, the data that are used for matrix is interweaved are carried out 9 DFT.At this, can allow complex multiplier 735 and matrix interleaver 737 to change their order.
420 DFT modules 733 can utilize PFA to be made of 3 DFT modules, 4 DFT modules, 5 DFT modules and 7 DFT modules.
As mentioned above, at receiving terminal the PN sequence of length 80-130 being carried out DFT is effective with the measured channel characteristic.When using 3780 the traditional IDFT/DFT processors that constitute by 60 IDFT/DFT modules and 63 IDFT/DFT modules to come that the PN sequence carried out IDFT/DFT, need carry out 0 for 3780 IDFT/DFT performances and fill, or even need the new IDFT/DFT module of design.But, according to embodiments of the invention, can be via selecting control signal by 413,315 IDFT/DFT modules 423 of 252 IDFT/DFT modules or 420 signals that IDFT/DFT module 433 is modulated the PN sequence and exported from 3780 IDFT/DFT processors, 413,315 IDFT/DFT modules 423 of 252 IDFT/DFT modules or 433 pairs of PN sequences of 420 IDFT/DFT modules have similar length.
In addition, according to 3780 IDFT/DFT processors of the present invention can be one of following combination: the combination of 84 point (3 * 4 * 7) IDFT/DFT modules and 45 point (5 * 9) IDFT/DFT modules, the combination of 105 point (3 * 5 * 7) IDFT/DFT modules and 36 point (4 * 9) IDFT/DFT modules, the combination of 180 point (4 * 5 * 9) IDFT/DFT modules and 21 point (3 * 7) IDFT/DFT modules, the combination of 1260 point (4 * 5 * 7 * 9) IDFT/DFT modules and 3 IDFT/DFT modules.For example, the combination of 105 point (3 * 5 * 7) IDFT/DFT modules and 36 point (4 * 9) IDFT/DFT modules represents that 105 IDFT/DFT modules can utilize PFA to be made of 3 IDFT/DFT modules, 5 IDFT/DFT modules and 7 IDFT/DFT modules, and 36 IDFT/DFT modules can utilize PFA to be made of 4 IDFT/DFT modules and 9 IDFT/DFT modules.
In brief, compared with prior art, the various structures of 3780 IDFT/DFT processors have enabled the processing more than 63.Receiving terminal uses 84,105,180,252,315,420 or IDFT/DFI, modules of 3780 IDFT/DFT processors to be used for modulation at 1260, has therefore produced efficient and the reliability of having improved performance.
Though illustrated and illustrated the present invention with reference to the preferred embodiments of the present invention, it will be understood by those skilled in the art that, under the situation that does not break away from the appended the spirit and scope of the present invention that claim limited, can carry out the various changes on form and the details.
Aforesaid embodiment and advantage only are exemplary, are not interpreted as limitation of the invention.This instruction can be applied to the device of other types easily.Explanation of the present invention is intended for indicative rather than will limits the scope of claim.To one skilled in the art, many substitute modes, improvement and variation are obvious.In the claims, the statement that device adds function is intended to cover the structure of the described function of execution described herein, the equivalent of structure still not, and be the structure of equivalence.
Claims (20)
1. multicarrier receiving system comprises:
The I/Q generator is used for producing baseband I/Q signal from the signal that is received;
Synchronized signal detector is used for detecting and puts at the PN of described baseband I/Q signal sequence start bit, and provides demultiplexing control signal and many output to select signal;
Demultiplexer is used for according to described demultiplexing control signal described baseband I/Q signal being divided into PN sequence, protection interval and ofdm signal;
Multiplexer is used for selecting signal multiplexing PN sequence and ofdm signal from described demultiplexer output according to described many outputs;
Many output DFT unit is used for according to many output DFT input signals ofdm signal and PN sequence from described multiplexer output being carried out the DFT operation,
Wherein said many output DFT unit comprises 3780 DFT processors, the ofdm signal that is used for inserting PN sequence or Domain Synchronous information is demodulated into frequency domain ofdm signal, wherein said 3780 DFT processors comprise K point DFT module and M point DFT module, at this 3780=K * M, and the output signal of 3780 DFT processors according to selecting control signal from or K point DFT module or M point DFT module.
2. according to the multicarrier receiving system of claim 1, wherein in ofdm signal, insert the PN sequence, and K is corresponding to the length of PN sequence.
3. according to the multicarrier receiving system of claim 1, it is one of following that wherein said 3780 DFT processors comprise:
The combination of 84 DFT modules and 45 DFT modules;
The combination of 105 DFT modules and 36 DFT modules;
The combination of 180 DFT modules and 21 DFT modules;
The combination of 252 DFT modules and 15 DFT modules;
The combination of 315 DFT modules and 12 DFT modules;
The combination of 420 DFT modules and 9 DFT modules;
The combination of 1260 DFT modules and 3 DFT modules.
4. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 252 DFT modules and 15 DFT modules, 252 DFT modules are constituting by 4 DFT modules, 7 DFT modules and 9 DFT modules, 15 DFT modules are by the constituting of 3 DFT modules and 5 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 252 DFT modules outputs.
5. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 315 DFT modules and 12 DFT modules, 315 DFT modules are constituting by 5 DFT modules, 7 DFT modules and 9 DFT modules, 12 DFT modules are by the constituting of 3 DFT modules and 4 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 315 DFT modules outputs.
6. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 420 DFT modules and 9 DFT modules, 420 DFT modules are by the constituting of 3 DFT modules, 4 DFT modules, 5 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 420 DFT modules outputs.
7. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 84 DFT modules and 45 DFT modules, 84 DFT modules are by the constituting of 3 DFT modules, 4 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 84 DFT modules outputs.
8. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 105 DFT modules and 36 DFT modules, 105 DFT modules are by the constituting of 3 DFT modules, 5 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 105 DFT modules outputs.
9. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 180 DFT modules and 21 DFT modules, 180 DFT modules are by the constituting of 4 DFT modules, 5 DFT modules and 9 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 180 DFT modules outputs.
10. according to the multicarrier receiving system of claim 2 or 3, wherein when 3780 DFT processors are made of 1260 DFT modules and 3 DFT modules, 1260 DFT modules are by the constituting of 4 DFT modules, 5 DFT modules, 7 DFT modules and 9 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 1260 DFT modules outputs.
11. a multicarrier receiving method comprises step:
Produce baseband I/Q signal from the signal that is received;
The PN sequence start bit of detection in described baseband I/Q signal put, and provides demultiplexing control signal and many output to select signal;
According to described demultiplexing control signal described baseband I/Q signal is divided into PN sequence, protection interval and ofdm signal;
Select multiplexing described PN sequence of signal and ofdm signal according to described many outputs;
The DFT that utilizes the DFT of output more than one unit to carry out ofdm signal and PN sequence according to many output DFT input signals operates,
Wherein said many output DFT unit comprises 3780 DFT processors, the ofdm signal that is used for inserting PN sequence or Domain Synchronous information is demodulated into frequency domain ofdm signal, wherein said 3780 DFT processors comprise K point DFT module and M point DFT module, at this 3780=K * M, and the output signal of 3780 DFT processors according to selecting control signal from or K point DFT module or M point DFT module.
12., wherein in ofdm signal, insert the PN sequence, and K is corresponding to the length of PN sequence according to the multicarrier receiving method of claim 11.
13. according to the multicarrier receiving method of claim 11, it is one of following that wherein said 3780 DFT processors comprise:
The combination of 84 DFT modules and 45 DFT modules;
The combination of 105 DFT modules and 36 DFT modules;
The combination of 180 DFT modules and 21 DFT modules;
The combination of 252 DFT modules and 15 DFT modules;
The combination of 315 DFT modules and 12 DFT modules;
The combination of 420 DFT modules and 9 DFT modules;
The combination of 1260 DFT modules and 3 DFT modules.
14. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 252 DFT modules and 15 DFT modules, 252 DFT modules are constituting by 4 DFT modules, 7 DFT modules and 9 DFT modules, 15 DFT modules are by the constituting of 3 DFT modules and 5 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 252 DFT modules outputs.
15. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 315 DFT modules and 12 DFT modules, 315 DFT modules are constituting by 5 DFT modules, 7 DFT modules and 9 DFT modules, 12 DFT modules are by the constituting of 3 DFT modules and 4 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 315 DFT modules outputs.
16. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 420 DFT modules and 9 DFT modules, 420 DFT modules are by the constituting of 3 DFT modules, 4 DFT modules, 5 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 420 DFT modules outputs.
17. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 84 DFT modules and 45 DFT modules, 84 DFT modules are by the constituting of 3 DFT modules, 4 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 84 DFT modules outputs.
18. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 105 DFT modules and 36 DFT modules, 105 DFT modules are by the constituting of 3 DFT modules, 5 DFT modules and 7 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 105 DFT modules outputs.
19. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 180 DFT modules and 21 DFT modules, 180 DFT modules are by the constituting of 4 DFT modules, 5 DFT modules and 9 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 180 DFT modules outputs.
20. multicarrier receiving method according to claim 12 or 13, wherein when 3780 DFT processors are made of 1260 DFT modules and 3 DFT modules, 1260 DFT modules are by the constituting of 4 DFT modules, 5 DFT modules, 7 DFT modules and 9 DFT modules, wherein by a predetermined control signal modulation PN sequence with by 1260 DFT modules outputs.
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| KR10-2002-0060245 | 2002-10-02 | ||
| KR1020020060245 | 2002-10-02 | ||
| KR1020020060245A KR100884407B1 (en) | 2002-10-02 | 2002-10-02 | TDS-OFDM transmission system having 3780-????? ????/??? procseeor and structure of 3780- ?? procseeor |
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| CNB031072046A Division CN100518025C (en) | 2002-10-02 | 2003-03-17 | Multi-carrier wale system with 3780 point IDFT/DFT processor and method thereof |
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| CN1909548B true CN1909548B (en) | 2010-11-03 |
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| CNB031072046A Expired - Fee Related CN100518025C (en) | 2002-10-02 | 2003-03-17 | Multi-carrier wale system with 3780 point IDFT/DFT processor and method thereof |
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| EP1750206A1 (en) * | 2005-08-04 | 2007-02-07 | THOMSON Licensing | 3780-point Discrete Fourier Transformation processor |
| WO2010031493A1 (en) | 2008-09-19 | 2010-03-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Technique for transmitting on multiple frequency resources in a telecommunication system |
| GB2511796A (en) * | 2013-03-13 | 2014-09-17 | Sony Corp | Transmitters, receivers and methods of transmitting and receiving |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1317903A (en) * | 2001-04-27 | 2001-10-17 | 清华大学 | Time domain synchronized orthogonal frequency-division complex modulation method |
| CN1348141A (en) * | 2001-11-23 | 2002-05-08 | 清华大学 | Discrete 3780-point Fourier transformation processor system and its structure |
| CN1398118A (en) * | 2002-08-16 | 2003-02-19 | 清华大学 | Method based on slide window for estimating and equalizing channels of block signals containing pilot |
| CN1398120A (en) * | 2002-08-30 | 2003-02-19 | 清华大学 | Interactive digital multimedia cable TV system |
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| JP2000115115A (en) * | 1998-09-30 | 2000-04-21 | Victor Co Of Japan Ltd | Generation method and decoding method for orthogonal multi-carrier signals |
| JP2000261402A (en) * | 1999-03-10 | 2000-09-22 | Toyota Central Res & Dev Lab Inc | Orthogonal frequency division multiplex modulator and modulation system for compensating for high frequency deterioration |
| JP2000278238A (en) * | 1999-03-23 | 2000-10-06 | Toyota Central Res & Dev Lab Inc | System and device for guard interval insertion type orthogonal frequency division multiplex modulation |
| JP3582707B2 (en) * | 1999-12-27 | 2004-10-27 | 日本ビクター株式会社 | Orthogonal multicarrier signal transmission apparatus and orthogonal multicarrier signal transmission method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1317903A (en) * | 2001-04-27 | 2001-10-17 | 清华大学 | Time domain synchronized orthogonal frequency-division complex modulation method |
| CN1348141A (en) * | 2001-11-23 | 2002-05-08 | 清华大学 | Discrete 3780-point Fourier transformation processor system and its structure |
| CN1398118A (en) * | 2002-08-16 | 2003-02-19 | 清华大学 | Method based on slide window for estimating and equalizing channels of block signals containing pilot |
| CN1398120A (en) * | 2002-08-30 | 2003-02-19 | 清华大学 | Interactive digital multimedia cable TV system |
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| CN1487680A (en) | 2004-04-07 |
| CN100518025C (en) | 2009-07-22 |
| CN1909548A (en) | 2007-02-07 |
| KR100884407B1 (en) | 2009-02-17 |
| KR20040029821A (en) | 2004-04-08 |
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