CN105095152A - Configurable 128 point fast Fourier transform (FFT) device - Google Patents

Abstract

The invention discloses a configurable 128 point fast Fourier transform (FFT) device, which comprises a first and a second serial to parallel register random access memories (RAM), a first and a second base 8 FFT calculation modules, a first and a second multiplier modules, a first and a second group rotation factor memory read only memories (ROM), a first and a second register RAM and base 2FFT operation modules, wherein a data processing mode is that 128 point data is sorted in an odd-even mode according to a sequence, an odd sequence is x1(r), an even sequence is x2(r), odd-even sequence data is X1(k), X2(k) after 64 points transformation, and a twiddle factor (img file='DDA 0000774622560000011.TIF' wi='79' he='70'/) and Xi(k) is multiplied by the X2(r) and is added with the X1(k) to obtain front 64 X(k) of 128 point FFT, is reduced to obtain rear 64 X(N/2+k) of the 128 point FFT. The configurable 128 point FFT device, and is a novel low hardware complexity configurable 128 point FFT device which can be configured in 64 points. The configurable 128 point FFT device meets the real-time process demands of an orthogonal frequency division multiplexing (OFDM) system, and achieves the design purpose of system on chips with low power dissipation and low resource consumption rate.

Description

A kind of configurable 128 FFT devices

Technical field

The present invention relates to communication code field, configurable 128 the FFT devices of one in the encoding and decoding field of particularly WLAN (wireless local area network) digital baseband part.

Background technology

OFDM (OrthogonalFrequencyDivisionMultiplexing, OFDM) thought is a kind of modulation technique put forward the sixties in 20th century, it is a kind of special multi-carrier transmission scheme, can regard a kind of multiplex technique, basic thought adopts to allow sub-channel spectra overlapping and not interactional frequency division multiplexing (FDM) technology.So not only can not use high speed balanced device, and the availability of frequency spectrum is higher, anti-impulsive noise and anti-multipath fading ability stronger.But higher owing to being suitable for the system complexity that analog filter implements, so never grow up.Nineteen sixty-five J.W.Cooley and T.W.Tukey proposes Fast Fourier Transform (FFT) (FFT, FastFourierTransformation) thought, then 20 century 70s, S.B.Weinstein proposes with discrete Fourier transformation (DFT, DiscreteFourierTransform) multi-carrier modulation is realized, for the practical of OFDM has established theoretical foundation.

Traditional Parallel Data Transmission System, that whole signal frequency range is divided into N number of subchannel, these subchannels transmit separately independently modulation signal, then by N number of subchannel frequency division multiplexing, avoid channel spectrum overlapping although this Frequency Division Multiplexing system can reduce frequency selective fading, effectively can not utilize frequency spectrum resource, and this system needs N number of modulator and demodulator, if when subchannel number is many, then use system for implementing hardware will be very complicated, and price comparison be expensive.

Over nearly 10 years, due to digital signal processing (DSP, DigitalSignalProcessing) develop rapidly of technology, Fast Fourier Transform (FFT) can be processed, and OFDM technology is due to its high bandwidth, characteristic that antijamming capability is strong, in the wireless communication systems such as therefore OFDM is applied to WLAN, LTE.FFT device wherein in OFDM modulation and demodulation can the quality of direct influential system performance.Existing much for the implementation method of the FFT calculation element of ofdm system at present, but mostly adopt traditional base-2 or base-4FFT algorithm, not only the cascade progression of butterfly unit is many, and need the multiplier of at substantial, cause designed FFT calculation element Shortcomings part in arithmetic speed, hardware resource utilization etc. like this, remain in some gaps with the requirement of high-performance OFDM system.

Traditional FFT generally adopts the algorithm of base-2FFT structure, the butterfly unit cascade number that the device of 128 FFT produces will reach 7 grades, the multiplier needed increases thereupon, and this Hardware Implementation is simple, but cost is hardware resource utilization, and not high and spent by 7 grades storer is more.The algorithm adopting pure base-2 structure is not generally advised at the FFT in the face of multiple spot.And adopt the algorithm of base-4 structure, due to 128 be not 4 integer power, therefore cannot with the algorithm of pure base-4 structure.128 traditional FFT adopt mixed base algorithm to need the butterfly unit of 3 bases 4 and the butterfly unit of 1 base 2, and the resource that storer and multiplier take is also quite large.

Summary of the invention

The present invention, for overcoming at least one defect (deficiency) described in above-mentioned prior art, provides configurable 128 the FFT devices of a kind of novel low hardware complexity (can be set to 64 points).Not only meet ofdm system high rate bioreactor demand, and reach the purpose of design of system level chip of low-power consumption, low-resource occupancy.

For solving the problems of the technologies described above, technical scheme of the present invention is as follows:

A kind of configurable 128 FFT devices, comprise first and second transformation from serial to parallel buffer RAM, first and second base 8FFT computing module, first and second multiplication module, first and second twiddle factor ROM ROM, first and second buffer RAM and base 2FFT computing module;

Data input connects the input end of the first transformation from serial to parallel buffer RAM, the input end of the output termination first base 8FFT computing module of the first transformation from serial to parallel buffer RAM, an input end of output termination first multiplication module of the first base 8FFT computing module, first twiddle factor ROM ROM connects another input end of the first multiplication module, the input end of the output termination second transformation from serial to parallel buffer RAM of the first multiplication module, the input end of the output termination second base 8FFT computing module of the second transformation from serial to parallel buffer RAM, the input end of the output termination first buffer RAM of the second base 8FFT computing module, an input end of output termination second multiplication module of the first buffer RAM, second twiddle factor ROM ROM connects another input end of the second multiplication module, the input end of the output termination base 2FFT computing module of the second multiplication module, the output termination second buffer RAM of base 2FFT computing module,

The input end of the output termination base 2FFT computing module of the first buffer RAM, the output termination second buffer RAM of base 2FFT computing module;

128 point data are carried out sequence of parity sequence, and odd sequence is x ₁r (), even sequence is x ₂r () is X after having carried out 64 point transformation ₁(k), X ₂(k), the latter X ₂k () is multiplied by twiddle factor being added the number drawn with the former is 64 numbers and X (k) before 128 FFT, subtracts each other rear 64 numbers and X (N/2+k) that the number drawn is 128 FFT, see following formula:

$X\left(k\right)=\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_1\left(r\right)W_N^{2rk}+W_N^k\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_2\left(r\right)W_N^{2rk}=X_1\left(k\right)+W_N^k{X}_2\left(k\right)$

According to symmetry:

$X(N/2+k)=X_1\left(k\right)+W_N^{N/2+k}{X}_2\left(k\right)=X_1\left(k\right)-W_N^k{X}_2\left(k\right)$

In above formula, represent twiddle factor, r is the sequence before FFT conversion

R=0,1 ..., N/2-1, k are the sequence k=0 after FFT conversion, 1 ..., N/2-1.

In technique scheme, configurable 128 the FFT devices of one proposed, adopt mixed base form, the effect of 128 FFT is realized by two radix-8 algorithm and base 2 unit, can close the effect that base 2 unit adjustment sequence of operation realizes 64 FFT, therefore the present invention can be set to 64 FFT simultaneously.The demand of ofdm system 64 and 128 FFT can be met like this.

It is of the present invention that to be principal feature be:

1) mixed base process 128 FFT

Adopt two radix-8 algorithm and a base 2 unit pipeline processes 128 point quick Fourier conversion, reach cascade number minimum, time delay is minimum, and can high speed processing.Wherein in realization, will through string also (and string) transit storage, first the data entered are changed into the FFT arithmetic element that 8 are exported to first base 8, after computing again serial through multiplier and rotation fac-tor, then carry out the FFT computing of second base 8, the result drawn draws again the result of final 128 FFT after the computing of base 2.

2) use of multiplier is reduced

Adopt the mode of mixed base not only can reduce the waste that cascade brings storage, and the use of multiplier can be reduced, 128 configurable FFT designs of the present invention use two complex multipliers altogether, that is to say 6 multipliers, other FFT devices relatively, greatly reduce the use number of multiplier, also improve the utilization factor of multiplier.

3) can be configured to 64 FFT

64 FFT in fact with 128 FFT gaps are few FFT unit of having carried out a base 2, in fact 128 FFT in the present invention comprise 64 FFT functions, as long as adjustment order, 64 data pass through the FFT unit of 2 bases 8, just computing can be completed, the present invention, by controlling the FFT computing of last base 2, completes the conversion to and at 128 at 64.

Compared with prior art, the beneficial effect of technical solution of the present invention is: configurable 128 the FFT devices of low hardware complexity of the present invention (can be set to 64 points).Not only meet ofdm system high rate bioreactor demand, and reach the purpose of design of system level chip of low-power consumption, low-resource occupancy.

Accompanying drawing explanation

Fig. 1 is the module map of 128 configurable FFT devices in the present invention.

Fig. 2 is base 8 structural drawing in the present invention.

Fig. 3 is base 2 structural drawing in the present invention.

Fig. 4 is the schematic diagram of the booth multiplier in the present invention.

Embodiment

Below in conjunction with drawings and Examples, technical scheme of the present invention is described further.

In order to make object of the present invention, technical scheme and advantage more clear, below in conjunction with accompanying drawing 1 ~ 4 and embodiment, configurable 128 FFT devices of the present invention are further described from principle and structure.It should be noted that following described instantiation is only for explaining summary of the invention, is not intended to limit the present invention.

For the FFT device of 128, its principle is as follows:

FFT is the fast algorithm of discrete Fourier transform (DFT), and it is the characteristic such as odd, even, empty, real according to discrete Fourier transform (DFT), carries out improving obtaining the algorithm of discrete Fourier transform (DFT), as follows according to DFT formula:

$X\left(k\right)=DFT\[x\left(n\right)\]=\underset{n=0}{\overset{N-1}{\Σ}}x\left(n\right)W_N^{nk}---\left(1\right)$

Wherein 0≤k≤N-1.

Can find out that the operand of DFT is larger, and fft algorithm is the DFT by constantly the DFT of long sequence being resolved into several short data records, and utilizes the periodicity of FFT, reducibility and conjugate symmetry to reduce the operand of DFT, as shown in the table:

Note: N representative is counted

The operand adopting different base can be demonstrated by above-mentioned table, can 4032 be reached for the complex multiplication operation amount of 64 FFT, direct DFT, adopt base 2 and base 4, base 8 be then 256,144,112.Can to think that on operand base 8 is optimum, speed up and connect as base 4, base 2, and the operand of DFT be maximum, but be necessary for the integer power of 8 and 4 due to the algorithm length of base 8 and base 4, therefore in selection flexibility ratio not as base 2.The present invention is based on configurable 128 FFT, demand fulfillment 64 FFT computings, so select employing 2 radix-8 algorithm and base 2 unit to form 128 FFT mixed base combinations in realization, the deficiency of base 8 and base 2 structure FFT can be made up, and it is minimum to reach operand;

If 128 point sequences of x (n) are as follows:

$X\left(s\right)=\underset{n=0}{\overset{N-1}{\Σ}}x\left(n\right)W_N^{ns}---\left(2\right)$

Wherein N=128, n, s ∈ 0,1 ..., N-1}, the sequence of x (n) point odd even is drawn x ₁(r)=x (2r), x ₂(r)=x (2r+1), wherein r=0,1 ..., N/2-1, if the first half that X (k) is X (s), the latter half that X (N/2+k) is X (s), as follows:

$\begin{array}{c}X\left(k\right)=\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_1\left(r\right)W_N^{2rk}+W_N^k\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_2\left(r\right)W_N^{2rk}\\ =X_1\left(k\right)+W_N^k{X}_2\left(k\right);k=0,1,...,N/2-1\end{array}---\left(3\right)$

$\begin{array}{c}X(N/2+k)=X_1(N/2+k)+W_N^{N/2+k}{X}_2(N/2+k)\\ =X_1\left(k\right)-W_N^k{X}_2\left(k\right);k=0,1,...,N/2-1\end{array}---\left(4\right)$

Above-mentioned formula is divided into two FFT, wherein X at 128 at 64 ₁(k), X ₂k () is 64 FFT, X ₁k () is that 128 middle even sequence numbers carry out 64 FFT parts, and X ₂k () is that 128 middle odd sequence numbers carry out 64 FFT parts, because both are the same, can think that their methods are the same;

64 FFT that two base 8FFT complete can be expressed as:

$X(t,s)=\underset{l=0}{\overset{7}{\Σ}}\{\[\underset{m=0}{\overset{7}{\Σ}}x(m,l)W_8^{ms}\]W_{64}^{ls}\}{W}_8^{lt}---\left(5\right)$

Wherein m, l, t, s ∈ 0,1 ..., the integer of 7}; Wherein m, l, t, s ∈ 0,1 ..., namely 7} is the matrix sequence of X, x is that 64 numbers of X, x are arranged according to 8*8, x (m, l) for carrying out the data before FFT, namely after serioparallel exchange 8 row 8 arrange data, be respectively the twiddle factor (instead of with displacement in the design) of first and second base 8 inside, it is the twiddle factor that will carry out after the computing of first base 8 being multiplied.

From formula (3), (4), carrying out 128 FFT can as follows:

First 128 point data are carried out odd even ordering, odd sequence is x ₁r (), even sequence is x ₂r () is X after having carried out 64 point transformation ₁(k), X ₂(k), the latter X ₂k () is multiplied by twiddle factor add and subtract mutually with the former, they are added front 64 numbers that the number drawn is 128 FFT, subtract each other latter 64 (corresponding (3), (4)) that the number drawn is 128 FFT.

Next be exactly that explanation 2 base 8 structural units realize 64 FFT, such as formula (5), first calculate the FFT of 8 groups 8, the result of gained and corresponding 49 non-1 twiddle factors after completing be multiplied, then divide again carry out FFT computing at 8 groups 8, complete the FFT computing of 64.In the FFT computing of wherein base 8, the inside adopts base 2 structure, and the multiplication of first, second grade only design 1 and 0, not can think and need to carry out multiplying.As seen from Figure 2, need when the third level to carry out the multiplication with twiddle factor, particularly $W_8^1=\frac{\sqrt{2}}{2}-j\frac{\sqrt{2}}{2}$ With $W_8^3=-\frac{\sqrt{2}}{2}-j\frac{\sqrt{2}}{2},$ Therefore multiplication process must be adopted.

As shown in Figure 1,128 in the present invention configurable FFT devices are mainly divided into input-buffer, intermediate buffer, export buffer memory, the FFT unit of the FFT unit of two bases 8 and a base 2, two complex multipliers and two twiddle factor ROM.The data implementation of configurable 128 FFT of the present invention is: the data that serial enters first are sorted by buffer, then 8 data export, carry out the FFT conversion of first order base 8, conversion after and twiddle factor carry out complex multiplication, be stored into internal buffer, then carry out the FFFT conversion of second level base 8.In the result of conversion 128 rear 64 carry out second time and rotation fac-tor after add and subtract mutually with first 64, obtain net result.

Below each functional module of the present invention is described in detail:

One. transformation from serial to parallel buffer RAM

The major function of transformation from serial to parallel buffer RAM is the buffer memory realizing input data, and gets out one group of 8 data next time exporting, realizes the function of transformation from serial to parallel.First this module adopts table tennis design, and hocket read-write, ensures that the high-speed and continuous of module exports.Realizing in 64 FFT situations, this module serial directly inputs, and then parallel 8 data directly export, and do not convert in way, and realizing when 128, serial input, when preservation, sequence of parity stores respectively, after 128 writes are full, the data first exporting 64 even order export 64 odd numbered sequences again, can according to formula (3), and (4) are verified.

Two. base 8FFT computing module

As shown in Figure 2, be base 8 structural drawing in the present invention, 8 data carry out 3 cascaded computation; Data are after cache module sorts, and the FFT computing module of input base 8, this module structurally adopts 3 level production line designs, and inverted order input sequence exports, and its principle of operation is stated above.Each clock of this module carries out once-through operation in addition, ensure that speedy carding process.The present invention is employing two base 8FFT computing modules, also has a complex multiplier and two buffers between them.

Three. multiplication module

Complex multiplication is made up of real addition and real multiplications, and shared by multiplier, resource is more much larger than totalizer, therefore, is reduced the number of times of multiplier, can save certain resource by certain way.Such as complex multiplication is directly launched:

(a+jb)×(c+jd)＝(ac-bd)+j(ad+bc)；

As can be seen from formula, needs 4 real multipliers and 2 real add musical instruments used in a Buddhist or Taoist mass altogether.Above-mentioned formula is converted:

(a+jb)×(c+jd)＝((c-d)a+(a-b)d)+j((a-b)d+(c+d)b)；

Can find out after simplification and only need 3 real multipliers and 5 real add musical instruments used in a Buddhist or Taoist mass, merely add 3 totalizers but reduce by a multiplier.On hardware spending, multiplier, far away higher than totalizer, can save certain resource by above-mentioned conversion.

In the present invention, one has two complex multipliers, and wherein each complex multiplier comprises 3 integer multiplier and 5 real add musical instruments used in a Buddhist or Taoist mass.The speed improving complex multiplier improves the key of FFT module speed, therefore adopts the integer multiplier of similar parallel processing to contribute to raising speed.In integer multiplier realizes, adopt the combination of booth coding and wallace add tree as shown in Figure 4,3 stages of needs realize multiplication function altogether, and first stage first multiplier is processed with multiplicand by the booth coding of base 4, draws the value that various piece is long-pending.Second stage utilizes wallace add tree to carry out additive operation by long-pending for various piece, and calculate the value of Sum and Carry, the phase III uses Prefix Adder that Sum and Carry is added and draws net result.Relative to general displacement multiplier, this multiplier, under some resource situation of sacrifice, performs similar parallel processing, increases substantially the speed of calculating, meet the requirement of FFT module arithmetic speed.

Four. the generation of twiddle factor

The present invention has needs two complex multipliers altogether, its major function is and rotation fac-tor, need when realizing 128 FFT to use two twiddle factor ROM, these two groups of twiddle factors are multiplied two complex multiplication module with corresponding data respectively.First twiddle factor ROM, is multiplied with it after completing the FFT of first base 8 in data, and twiddle factor has fixed in ROM (read-only memory) (Rom).Its formula produced is:

$W_N^k=e^{-j\frac{2\mathrm{\π}}{N}k}=cos\left(\frac{2\mathrm{\π}k}{N}\right)-j\sin \left(\frac{2\mathrm{\π}k}{N}\right);$

First group of twiddle factor ROM has needs 64 twiddle factors altogether, produces twiddle factor as follows:

I represents the sequence number of 64 data;

When i ∈ [0,7], twiddle factor is 1;

When i ∈ [9,16], twiddle factor is wherein k ∈ [0,7];

When i ∈ [17,23], twiddle factor is wherein k ∈ [0,6];

When i ∈ [25,32], twiddle factor is wherein k ∈ [0,7];

When i ∈ [33,39], twiddle factor is wherein k ∈ [0,6];

When i ∈ [41,48], twiddle factor is wherein k ∈ [0,7];

When i ∈ [49,55], twiddle factor is wherein k ∈ [0,7];

When i ∈ [57,63], twiddle factor is wherein k ∈ [0,7];

When i ∈ [8,24,40,56], twiddle factor is 1.

According to above-mentioned, the twiddle factor of generation calculated result by matlab, result is changed into binary mode respectively, get 20 bits, first is sign bit, and second is integer-bit, and remaining is decimal place, such as $W_{64}^{12}=cos\left(\frac{3\mathrm{\π}}{8}\right)-jsin\left(\frac{3\mathrm{\π}}{8}\right),$ $cos\left(\frac{3\mathrm{\π}}{8}\right)\≈0.3827$ Transfer 20 scale-of-two+0.110000111111000101 to, transferring 20 scale-of-two to is+0.1110110010000011010; Combined symbol gets complement code, and real number imaginary number is stored together and can be obtained: 00110000111111000101_1100010011011111100110; 20 is real number above, after 20 be imaginary number.The binary data drawn by this method is fixed in first twiddle factor ROM ROM;

Second twiddle factor produces quite easily comparatively speaking, can learn that the formula of second twiddle factor is with reference to formula (3), (4):

$W_{128}^k=e^{-j\frac{2\mathrm{\π}}{128}k}=\cos \left(\frac{2\mathrm{\π}k}{128}\right)-j\sin \left(\frac{2\mathrm{\π}k}{128}\right);k=\[0,1,2,...,63\]$

Here utilize matlab to calculate each twiddle factor equally, by above-mentioned conversion, can binary data be obtained, and be fixed in second twiddle factor ROM ROM.

Five. internal data buffer device

After the FFT computing of two bases 8, data start stored in internal buffer, and a clock 8 data, stored in RAM, if carry out 64 FFT, just read after just only needing wait 64 data writes at once.If 128 FFT just need storage 128 data, front 64 data are even sequences, and latter 64 is odd sequence, then simultaneously Sequential output respectively from two data of even sequence and odd sequence.

Six. the FFT processing module of base 2

As shown in Figure 3, base 2 resume module is made up of two totalizers and a complex multiplier, because complex multiplier independently becomes module, so be only left two totalizers here to realize FFT conversion, the even sequence sent here by a upper module and odd sequence carry out plus-minus and draw two results.

Seven. export data buffer

Known according to formula (3), (4), realizing 128 FFT, the result that module addition draws is front 64 data of 128, and the result that subtraction draws is rear 64 data, stored in output data buffer, waits for and reading.64 FFT then do not need to export data buffer module by upper base 2 module and this, directly export.

In sum, 128 configurable FFT counters that the embodiment of the present invention provides, complete 128 point processings by 2 base 8 arithmetic elements and base 2 arithmetic element, and module adopts pipeline system, ensure that high-speed and continuous exports.On hardware implementing, reduce being suitable for of multiplier, improve the utilization factor of multiplier, hardware resource is expended minimum.The present invention can be configured to 64 FFT enable to be applied on OFDM equipment in addition.

The corresponding same or analogous parts of same or analogous label;

Describe in accompanying drawing position relationship for only for exemplary illustration, the restriction to this patent can not be interpreted as;

Obviously, the above embodiment of the present invention is only for example of the present invention is clearly described, and is not the restriction to embodiments of the present invention.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.All any amendments done within the spirit and principles in the present invention, equivalent to replace and improvement etc., within the protection domain that all should be included in the claims in the present invention.

Claims (6)

1. configurable 128 FFT devices, it is characterized in that, comprise first and second transformation from serial to parallel buffer RAM, first and second base 8FFT computing module, first and second multiplication module, first and second group twiddle factor ROM ROM, first and second buffer RAM and base 2FFT computing module;

Data input connects the input end of the first transformation from serial to parallel buffer RAM, the input end of the output termination first base 8FFT computing module of the first transformation from serial to parallel buffer RAM, an input end of output termination first multiplication module of the first base 8FFT computing module, first twiddle factor ROM ROM connects another input end of the first multiplication module, the input end of the output termination second transformation from serial to parallel buffer RAM of the first multiplication module, the input end of the output termination second base 8FFT computing module of the second transformation from serial to parallel buffer RAM, the input end of the output termination first buffer RAM of the second base 8FFT computing module, an input end of output termination second multiplication module of the first buffer RAM, second twiddle factor ROM ROM connects another input end of the second multiplication module, the input end of the output termination base 2FFT computing module of the second multiplication module, the output termination second buffer RAM of base 2FFT computing module,

The input end of the output termination base 2FFT computing module of the first buffer RAM, the output termination second buffer RAM of base 2FFT computing module;

128 point data are carried out sequence of parity sequence, and odd sequence is x ₁r (), even sequence is x ₂r () is X after having carried out 64 point transformation ₁(k), X ₂(k), the latter X ₂k () is multiplied by twiddle factor being added the number drawn with the former is 64 numbers and X (k) before 128 FFT, subtracts each other rear 64 numbers and X (N/2+k) that the number drawn is 128 FFT, see following formula:

$X\left(k\right)=\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_1\left(r\right)W_N^{2rk}+W_N^k\underset{r=0}{\overset{N/2-1}{\Σ}}{x}_2\left(r\right)W_N^{2rk}=X_1\left(k\right)+W_N^k{X}_2\left(k\right)$

According to symmetry:

$X(N/2+k)=X_1\left(k\right)+W_N^{N/2+k}{X}_2\left(k\right)=X_1\left(k\right)-W_N^k{X}_2\left(k\right)$

In above formula, represent twiddle factor, r is the sequence r=0 before FFT conversion, 1 ..., N/2-1, k are the sequence k=0 after FFT conversion, 1 ..., N/2-1,

2. configurable 128 FFT devices according to claim 1, is characterized in that, described first and second transformation from serial to parallel buffer RAM inputs the buffer memory of data for realizing, and get out one group of 8 data next time exporting, realize data serial and turn parallel;

First and second transformation from serial to parallel buffer RAM adopts table tennis design, and hocket read-write, ensures that the high-speed and continuous of module exports;

When realizing 64 FFT devices, serial directly inputs, and then parallel 8 data directly export, and do not convert in way,

When realizing 128 FFT devices, serial input, during preservation, sequence of parity stores respectively, after 128 writes are full, first export the data of 64 even order, then exports the data of 64 odd numbered sequences.

3. configurable 128 FFT devices according to claim 1, is characterized in that, described first and second base 8FFT computing module adopts 3 level production line designs, and inverted order input sequence exports.

4. configurable 128 FFT devices according to claim 1, it is characterized in that, first and second multiplication module described comprises 6 integer multiplier and 10 real add musical instruments used in a Buddhist or Taoist mass respectively, integer multiplier realize in, employing be booth coding be combined the multiplier formed with wallace add tree.

5. configurable 128 FFT devices according to claim 4, it is characterized in that, it is described in integer multiplier realizes, what adopt is the multiplier that booth coding forms with the combination of wallace add tree, its realization needs 3 stages to realize multiplication function altogether, first stage first multiplier is processed with multiplicand by the booth coding of base 4, draws the value that various piece is long-pending; Second stage utilizes wallace add tree to carry out additive operation by long-pending for various piece, and calculate the value of Sum and Carry, the phase III uses Prefix Adder that Sum and Carry is added and draws net result.

6. configurable 128 FFT devices according to claim 5, is characterized in that, described first twiddle factor ROM ROM stores first group of twiddle factor, and described second twiddle factor ROM ROM stores second group of twiddle factor;

Its produce formula be into:

$W_N^k=e^{-j\frac{2\mathrm{\π}}{N}k}=cos\left(\frac{2\mathrm{\π}k}{N}\right)-jsin\left(\frac{2\mathrm{\π}k}{N}\right).$