CN105095152B - A kind of 128 configurable point FFT devices - Google Patents
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Abstract
The present invention discloses a kind of 128 configurable point FFT devices, including the first and second transformation from serial to parallel buffer RAM, the first and second base 8FFT computing module, the first and second multiplication module, first and second group of twiddle factor ROM ROM, the first and second buffer RAM and base 2FFT computing module, wherein data processing method: being that 128 point datas are first carried out odd even ordering according to sequence, odd-order is classified as x1(r), even-order is classified as x2It (r), is X after sequence of parity data have carried out 64 point transformation1(k)、X2(k), X2(k) multiplied by twiddle factorWith X1(k) it is added and obtains first 64 several X (k) of 128 point FFT, subtract each other latter 64 several X (N/2+k) that the number drawn is 128 point FFT.It is a kind of 128 point FFT devices (can be set at 64 points) that novel low hardware complexity is configurable.Not only meet ofdm system high rate bioreactor demand, and reached low-power consumption, low-resource occupancy system level chip purpose of design.
Description
Technical field
The present invention relates in communication code field, the especially coding of WLAN digital baseband part and decoding field
A kind of 128 configurable point FFT devices.
Background technique
Orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM) thought is 20
A kind of modulation technique put forward the sixties in century is a kind of special multi-carrier transmission scheme, can regard a kind of multiplexing skill
Art, basic thought are using the overlapping of permission sub-channel spectra and not interactional frequency division multiplexing (FDM) technology.Not only may be used in this way
Not use high speed balanced device, and the availability of frequency spectrum is relatively high, and anti-impulsive noise and anti-multipath fading ability are stronger.But
It is higher due to being applicable in the system complexity that analog filter implements, so never growing up.Nineteen sixty-five
J.W.Cooley and T.W.Tukey proposes the think of of Fast Fourier Transform (FFT) (FFT, Fast Fourier Transformation)
Think, then in the 1970s, S.B.Weinstein proposes to use discrete Fourier transform (DFT, Discrete Fourier
Transform it) realizes multi-carrier modulation, has established theoretical basis for the functionization of OFDM.
Traditional Parallel Data Transmission System is that entire signal frequency range is divided into N number of subchannel, the transmission of these subchannels
Modulated signal independent, then by N number of subchannel frequency division multiplexing, although this Frequency Division Multiplexing system can reduce frequency selection
Property decline avoid channel spectrum from being overlapped, but cannot effectively utilize frequency spectrum resource, and this system needs N number of modulator to conciliate
Device is adjusted, if when subchannel number is relatively more, it will be sufficiently complex with system for implementing hardware, and price is more expensive.
In the past 10 years, due to the hair at full speed of Digital Signal Processing (DSP, Digital Signal Processing) technology
Exhibition, can handle Fast Fourier Transform (FFT), and OFDM technology is due to its high bandwidth, the characteristic of strong antijamming capability,
OFDM is applied to WLAN, in the wireless communication systems such as LTE.Wherein the FFT device in OFDM modulation and demodulation will have a direct impact on
The quality of system performance.The implementation method of many FFT computing devices for ofdm system existing at present, but tradition is mostly used greatly
Base -2 or base -4FFT algorithm, not only the cascade series of butterfly unit is more, but also need to expend a large amount of multiplier, causes in this way
Designed FFT computing device arithmetic speed, in terms of Shortcomings in place of, with high-performance OFDM
The requirement of system still has some gaps.
Traditional FFT generally uses the algorithm of base -2FFT structure, the butterfly unit cascade that the device of 128 point FFT generates
Number is up to 7 grades, and the multiplier needed increases therewith, and this hardware implementation method is simple, but cost is hardware resource utilization
Not high and memory spent by 7 grades is more.It is general in the FFT in face of multiple spot it is not recommended that using pure -2 structure of base algorithm.
And use the algorithm of -4 structure of base that can not use the algorithm of pure -4 structure of base since 128 be not 4 integer power.Traditional
128 point FFT need the butterfly unit of 3 bases 4 and the butterfly unit of 1 base 2 using mixed base algorithm, and memory is accounted for multiplier
Resource is also quite large.
Summary of the invention
The present invention in order to overcome at least one of the drawbacks of the prior art described above (deficiency), provides a kind of novel low hardware
128 configurable point FFT devices (can be set at 64 points) of complexity.Not only meet ofdm system high rate bioreactor demand,
And reached low-power consumption, low-resource occupancy system level chip purpose of design.
In order to solve the above technical problems, technical scheme is as follows:
A kind of 128 configurable point FFT devices, including the first and second transformation from serial to parallel buffer RAM, the first and second base 8FFT
Computing module, the first and second multiplication module, the first and second twiddle factor ROM ROM, the first and second buffer RAM and base 2FFT
Computing module；
Data input the input terminal for meeting the first transformation from serial to parallel buffer RAM, and the first transformation from serial to parallel buffer RAM's is defeated
The input terminal of the first base 8FFT computing module is terminated out, output the first multiplication module of termination of the first base 8FFT computing module
One input terminal, the first twiddle factor ROM ROM connect another input terminal of the first multiplication module, the first multiplication module
The second transformation from serial to parallel buffer RAM of output termination input terminal, the output termination the of the second transformation from serial to parallel buffer RAM
The input terminal of diyl 8FFT computing module, the input terminal of the first buffer RAM of output termination of the second base 8FFT computing module, the
One input terminal of output the second multiplication module of termination of one buffer RAM, the second twiddle factor ROM ROM connect second and multiply
Another input terminal of summer block；The input terminal of the output termination base 2FFT computing module of second multiplication module, base 2FFT
The output of computing module terminates the second buffer RAM；
The input terminal of the output termination base 2FFT computing module of first buffer RAM, the output end of base 2FFT computing module
Meet the second buffer RAM；
128 point datas are subjected to sequence of parity sequence, odd-order is classified as x1(r), even-order is classified as x2(r), 64 point transformation have been carried out
It is afterwards X1(k)、X2(k), the latter X2(k) multiplied by twiddle factorFirst 64 that the number drawn is 128 point FFT are added with the former
Number is X (k), subtracts each other rear 64 i.e. X of number (N/2+k) that the number drawn is 128 point FFT, referring to following formula:
According toSymmetry:
In above formula,Indicate that twiddle factor, r are the sequence before FFT transform
R=0,1 ..., N/2-1, k are the sequence k=0,1 ..., N/2-1 after FFT transform.
In above-mentioned technical proposal, a kind of 128 configurable point FFT devices of proposition pass through two using mixed base form
Radix-8 algorithm and base Unit 2 realize the effect of 128 point FFT, while can close base Unit 2 adjustment operation order and realize 64
The effect of point FFT, therefore the present invention can be set to 64 point FFT.It can satisfy 64 points and 128 points of ofdm system in this way
The demand of FFT.
Of the invention is to be mainly characterized in that:
1) mixed base handles 128 point FFT
Using two radix-8 algorithms and 2 unit pipeline processes of base, a 128 point quick Fourier transformation, reach cascade number
Mesh is minimum, and delay is minimum, and can high speed processing.Wherein in realization, to pass through string simultaneously (and string) transit storage, first will
The data of entrance change into 8 outputs to the FFT arithmetic element of first base 8, again serially by multiplier and rotation after operation
Transposon is multiplied, and then carries out the FFT operation of second base 8, and the result obtained obtains final 128 again after the operation of base 2
The result of point FFT.
2) use of multiplier is reduced
Cascade can be not only reduced by the way of mixed base and brings the waste of storage, but also can reduce making for multiplier
With, of the invention 128 points configurable FFT designs use altogether two complex multipliers, that is to say 6 multipliers, it is opposite other
FFT device greatly reduces the use number of multiplier, also improves the utilization rate of multiplier.
3) it can be configured to 64 point FFT
64 point FFT are actually few FFT unit for having carried out a base 2 with 128 point FFT gaps, actually of the invention
In 128 point FFT include 64 point FFT functions, as long as adjustment sequence, 64 data pass through the FFT unit of 2 bases 8, energy
Complete operation, the present invention is completed by controlling the FFT operation of the last one base 2 to and 64 points of conversion at 128 points.
Compared with prior art, the beneficial effect of technical solution of the present invention is: low hardware complexity of the invention is configurable
128 point FFT devices (can be set at 64 points).Not only meet ofdm system high rate bioreactor demand, and reaches low function
The purpose of design of the system level chip of consumption, low-resource occupancy.
Detailed description of the invention
Fig. 1 is the module map of 128 points of configurable FFT devices in the present invention.
Fig. 2 is 8 structure chart of base in the present invention.
Fig. 3 is 2 structure chart of base in the present invention.
Fig. 4 is the schematic diagram of the booth multiplier in the present invention.
Specific embodiment
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
It is right below in conjunction with attached drawing 1~4 and embodiment in order to be more clear the objectives, technical solutions, and advantages of the present invention
Configurable 128 point FFT devices of the invention are further described from principle and structure.It is worth noting that, being retouched below
The specific example stated is only used for explaining summary of the invention, is not intended to limit the present invention.
By taking 128 points of FFT device as an example, the principle is as follows:
FFT is the fast algorithm of Discrete Fourier Transform, it is the spies such as odd, even, empty, real according to Discrete Fourier Transform
Property, acquisition is improved to the algorithm of Discrete Fourier Transform, as follows according to DFT formula:
Wherein 0≤k≤N-1.
It can be seen that the operand of DFT is bigger, and fft algorithm is by the way that constantly the DFT of long sequence is decomposed
At the DFT of several short sequences, and the operand of DFT is reduced using the periodicity, reducibility and conjugate symmetry of FFT, it is as follows
Shown in table:
Note: N represents points
Operand using different bases, by taking 64 point FFT as an example, the complex multiplication of direct DFT can be shown by above-mentioned table
Operand can achieve 4032, and use base 2 and base 4, base 8 then for 256,144,112.It is considered that base 8 on operand
It is optimal, it speeds up and is connected in base 4, base 2, and the operand of DFT is maximum, but since the algorithm length of base 8 and base 4 is necessary for 8 and 4
Integer power, therefore it is not so good as base 2 in selection flexibility ratio.The present invention is to need to meet 64 point FFT based on configurable 128 point FFT
Operation, so selection in realization constitutes the combination of 128 point FFT mixed bases using 2 radix-8 algorithms and base Unit 2, it can be more
The deficiency of base 8 and 2 structure FFT of base is mended, and it is minimum to reach operand；
If 128 point sequences of x (n) are as follows:
Wherein N=128, n, s ∈ { 0,1 ..., N-1 },The sequence point odd even of x (n) is obtained
X out1(r)=x (2r), x2(r)=x (2r+1), wherein r=0,1 ..., N/2-1, if X (k) is the first half of X (s), X (N/
2+k) the latter half for being X (s), as follows:
Above-mentioned formula is to be divided into two 64 point FFT for 128 points, wherein X1(k),X2It (k) is 64 point FFT, X1It (k) is 128 points
64 parts point FFT of middle even-order columns progress, and X2It (k) is that odd-order columns carries out 64 parts point FFT in 128 points, due to the two
Equally, it is believed that their methods are the same；
The 64 point FFT that two base 8FFT are completed can be indicated are as follows:
The integer of wherein m, l, t, s ∈ { 0,1 ..., 7 }；Wherein m, l, t, s ∈ { 0,1 ..., 7 } are X, the matrix sequence of x
Column are X, and 64 numbers of x are arranged according to 8*8, and x (m, l) is the data carried out before FFT, i.e., 8 rows 8 after serioparallel exchange
The data of column,Twiddle factor (in the design with displacement instead of) inside respectively first and second base 8,
For the twiddle factor that be multiplied after first 8 operation of base.
By formula (3), (4) it is found that 128 point FFT of progress can be as follows:
128 point datas are first subjected to odd even ordering, odd-order is classified as x1(r), even-order is classified as x2(r), after having carried out 64 point transformation
For X1(k)、X2(k), the latter X2(k) multiplied by twiddle factorIt is mutually added and subtracted with the former, it is 128 points that they, which are added the number drawn,
Preceding 64 numbers of FFT subtract each other latter 64 (corresponding (3), (4)) that the number drawn is 128 point FFT.
It next is exactly to illustrate that 28 structural units of base realize that 64 point FFT first calculate 8 groups 8 points of FFT such as formula (5), it is complete
At rear resulting result and corresponding 49 non-1 rotation fac-tors, then divide 8 groups of 8 points of progress FFT operations again, completes 64
The FFT operation of point.Wherein the inside uses 2 structure of base in the FFT operation of base 8, and the multiplication of first, second grade design 1 and 0 can
To think not needing to carry out multiplying.As seen from Figure 2, it needs to carry out the multiplication with twiddle factor when the third level,
EspeciallyWithTherefore multiplication process must be used.
As shown in Figure 1,128 points of configurable FFT devices in the present invention are broadly divided into input-buffer, intermediate buffer, output
Caching, the FFT unit of two bases 8 and the FFT unit of a base 2, two complex multipliers and two twiddle factor ROMs.This
The data implementation procedure of the configurable 128 point FFT of invention are as follows: the data serially entered first pass through buffer and are ranked up, and then 8
A data output, carries out the FFT transform of first order base 8, carries out complex multiplication after transformation with twiddle factor, and inner buffer is arrived in storage
Device then carries out the FFFT transformation of second level base 8.Latter 64 of 128 carry out second and twiddle factor in the result of transformation
It is mutually added and subtracted after multiplication with first 64, obtains final result.
Each functional module of the invention is described in detail below:
One, transformation from serial to parallel buffer RAM
The major function of transformation from serial to parallel buffer RAM is to realize the caching of input data, and be ready to export next time
One group of 8 data, realize the function of transformation from serial to parallel.The module is alternately read and write using table tennis design first, guarantees mould
The high speed of block continuously exports.When realizing 64 point FFT, which is serially directly inputted, and then parallel 8 data are directly defeated
Out, it is not converted on the way, and when realizing at 128, serial input, when preservation, sequence of parity stores respectively,
After 128 points of write-ins are full, the data for first exporting 64 even orders export 64 odd numbered sequences again, can be according to formula (3), (4)
Verifying.
Two, base 8FFT computing modules
As shown in Fig. 2, being 8 structure chart of base in the present invention, 8 data carry out 3 cascaded computations；Data are in cache module
After being ranked up, the FFT computing module of base 8 is inputted, which is designed in structure using 3 level production lines, inverted order input
Sequential output, principle of operation have been stated in front.In addition each clock of the module carries out once-through operation, ensure that high speed
Output.The present invention is using two base 8FFT computing modules, and there are one complex multiplier and two buffers between them.
Three, multiplication modules
Complex multiplication is made of real addition and real multiplications, and the resource as occupied by multiplier is bigger than adder very
It is more, therefore, the number of multiplier is reduced by certain way, can save certain resource.Such as complex multiplication is directly unfolded:
(a+jb) × (c+jd)=(ac-bd)+j (ad+bc)；
As can be seen that needing 4 real multipliers and 2 real add musical instruments used in a Buddhist or Taoist mass altogether from formula.Above-mentioned formula is become
It changes:
(a+jb) × (c+jd)=((c-d) a+ (a-b) d)+j ((a-b) d+ (c+d) b)；
It can be seen that only needing 3 real multipliers and 5 real add musical instruments used in a Buddhist or Taoist mass after simplification, merely add 3 adders but
Reduce by a multiplier.On hardware spending, multiplier is significantly larger than adder, and certain money can be saved by above-mentioned transformation
Source.
There are two complex multipliers altogether in the present invention, wherein each complex multiplier includes 3 integer multipliers and 5
Real add musical instruments used in a Buddhist or Taoist mass.The speed for improving complex multiplier is the key that improve FFT module speed, therefore use similar parallel processing
Integer multiplier helps to improve speed.In integer multiplier realization, using the combination of booth coding and wallace add tree
As shown in figure 4,3 stages is needed to realize multiplication functions altogether, first stage multiplier first by the booth coding of base 4 with
Multiplicand is handled, and obtains the value of various pieces product.Second stage be using wallace add tree by various pieces product into
Row add operation calculates the value of Sum and Carry, and the phase III is added Sum with Carry using Prefix Adder and obtains most
Terminate fruit.For general displacement multiplier, this multiplier executes similar parallel in the case where sacrificing some resource situations
Processing, increases substantially the speed of calculating, meets the requirement of FFT module arithmetic speed.
The generation of four, twiddle factors
The present invention needs altogether two complex multipliers, and major function is and rotation fac-tor to realize at 128 points
Need to use two twiddle factor ROMs when FFT, this two groups of twiddle factors are multiple at two with corresponding data respectively
Number multiplier module is multiplied.First twiddle factor ROM multiplies it by after the FFT that data complete first base 8, revolves
Transposon has fixed in read-only memory (Rom).Its formula generated are as follows:
First group of twiddle factor ROM needs altogether 64 twiddle factors, and it is as follows to generate twiddle factor:
I indicates the sequence number of 64 data；
When i ∈ [0,7], twiddle factor 1；
When i ∈ [9,16], twiddle factor isWherein [0,7] k ∈；
When i ∈ [17,23], twiddle factor isWherein [0,6] k ∈；
When i ∈ [25,32], twiddle factor isWherein [0,7] k ∈；
When i ∈ [33,39], twiddle factor isWherein [0,6] k ∈；
When i ∈ [41,48], twiddle factor isWherein [0,7] k ∈；
When i ∈ [49,55], twiddle factor isWherein [0,7] k ∈；
When i ∈ [57,63], twiddle factor isWherein [0,7] k ∈；
When i ∈ [8,24,40,56], twiddle factor 1.
According to above-mentioned, the twiddle factor of generation is calculated by matlab as a result, result to be changed into binary system shape respectively
Formula takes 20 bits, and first is sign bit, and second is integer-bit, and remaining is decimal place, such as Switch to 20 binary systems+0.110000111111000101, switching to 20 binary systems is+0.1110110010000011010；Combined symbol takes complement code, and real number
Imaginary number stores can obtain together: 00110000111111000101_1100010011011111100110；Front 20 is real
Number, behind 20 be imaginary number.First twiddle factor ROM ROM is fixed to by the binary data that this method obtains
In；
Comparatively second twiddle factor generates relatively easy, referring to formula (3), (4) it can be seen that second twiddle factor
Formula are as follows:
Here each twiddle factor is calculated also with matlab, by above-mentioned conversion, binary data can be obtained,
And it is fixed in second twiddle factor ROM ROM.
Five, internal data buffer devices
After the FFT operation of two bases 8, data start to be stored in internal buffer, and 8 data of a clock are stored in RAM
In, if it is 64 point FFT are carried out, just only need just to read at once after waiting 64 data write-ins.It is just needed if it is 128 point FFT
128 data are stored, preceding 64 data are even sequences, and latter 64 are odd sequences, and then Sequential output comes respectively simultaneously
From two data of even sequence and odd sequence.
The FFT processing module of six, bases 2
As shown in figure 3,2 resume module of base is made of two adders and a complex multiplier, due to complex multiplier
It is independent at module, so be left two adders only here to realize FFT transform, the even sequence and surprise sent by a upper module
Sequence carries out plus-minus and obtains two results.
Seven, output data buffers
According to formula (3), (4) it is found that realizing 128 point FFT, the result that a module addition obtains is preceding the 64 of 128 points
A data, and the result that subtraction obtains is rear 64 data, is stored in output data buffer, waits and be read out.And 64 point FFT are then not
It needs directly to export by 2 module of a upper base and this output data buffer module.
In conclusion 128 points provided in an embodiment of the present invention configurable FFT calculators, by 28 arithmetic elements of base and
One 2 arithmetic element of base completes 128 point processings, and module uses pipeline system, guarantees the continuous output of high speed.In hardware realization
On, being applicable in for multiplier is reduced, the utilization rate of multiplier is improved, expends hardware resource minimum.In addition the present invention is can to match
64 point FFT are set to enable to apply in OFDM equipment.
The same or similar label correspond to the same or similar components；
Described in attached drawing positional relationship for only for illustration, should not be understood as the limitation to this patent；
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention
Protection scope within.
Claims (5)
1. a kind of 128 configurable point FFT devices, which is characterized in that including the first and second transformation from serial to parallel buffer RAM,
One, diyl 8FFT computing module, the first and second multiplication module, the first and second twiddle factor ROM ROM, the first and second buffer
RAM and base 2FFT computing module；
Data input the input terminal for meeting the first transformation from serial to parallel buffer RAM, the output end of the first transformation from serial to parallel buffer RAM
The input terminal of the first base 8FFT computing module is connect, the output of the first base 8FFT computing module terminates one of the first multiplication module
Input terminal, the first twiddle factor ROM ROM connect another input terminal of the first multiplication module, the first multiplication module it is defeated
The input terminal of the second transformation from serial to parallel buffer RAM is terminated out, and the output of the second transformation from serial to parallel buffer RAM terminates the second base
The input terminal of 8FFT computing module, the input terminal of the first buffer RAM of output termination of the second base 8FFT computing module, first is slow
One input terminal of output the second multiplication module of termination of storage RAM, the second twiddle factor ROM ROM connect the second multiplier
Another input terminal of module；The input terminal of the output termination base 2FFT computing module of second multiplication module, base 2FFT operation
The output of module terminates the second buffer RAM；
The input terminal of the output termination base 2FFT computing module of first buffer RAM, the output termination the of base 2FFT computing module
Two buffer RAM；
First and second transformation from serial to parallel buffer RAM and gets out export next time one group for realizing the caching of input data
8 data realize that serial mode turns parallel；
First and second transformation from serial to parallel buffer RAM is alternately read and write using table tennis design, is guaranteed that the high speed of module is continuously defeated
Out；
It when realizing 64 point FFT device, serially directly inputs, then parallel 8 data directly export, and are not become on the way
It changes,
When realizing 128 point FFT device, serial input, when preservation, sequence of parity stores respectively, after 128 points of write-ins are full, first
The data of 64 even orders are exported, then export the data of 64 odd numbered sequences；
128 point datas are subjected to sequence of parity sequence, odd-order is classified as x1(r), even-order is classified as x2(r), it is after having carried out 64 point transformation
X1(k)、X2(k), the latter X2(k) multiplied by twiddle factorPreceding 64 numbers that the number that draws is 128 point FFT are added with the former i.e.
X (k) subtracts each other rear 64 i.e. X of number (N/2+k) that the number drawn is 128 point FFT, referring to following formula:
According toSymmetry:
In above formula,Indicate that twiddle factor, r are the sequence r=0,1 ..., N/2-1, k before FFT transform
For the sequence k=0,1 after FFT transform ..., N/2-1.
2. 128 configurable point FFT devices according to claim 1, which is characterized in that the first and second base 8FFT fortune
It calculates module to design using 3 level production lines, the output of inverted order input sequence.
3. 128 configurable point FFT devices according to claim 1, which is characterized in that the first and second multiplier mould
Block separately includes 3 integer multipliers and 5 real add musical instruments used in a Buddhist or Taoist mass, integer multiplier realization in, using booth coding with
Wallace add tree combines the multiplier of composition.
4. 128 configurable point FFT devices according to claim 3, which is characterized in that described to be realized in integer multiplier
In, using the multiplier of booth coding and the combination composition of wallace add tree, realization needs 3 stages to realize altogether
Multiplication function, first stage multiplier first are encoded by the booth of base 4 and are handled with multiplicand, obtain various pieces product
Value；Second stage is that various pieces product is carried out add operation using wallace add tree, calculates Sum's and Carry
Value, phase III are added Sum with Carry using Prefix Adder and obtain final result.
5. 128 configurable point FFT devices according to claim 4, which is characterized in that the first twiddle factor storage
Device ROM is stored with first group of twiddle factor, and the second twiddle factor ROM ROM is stored with second group of twiddle factor；
The formula that it is generated is equal are as follows:
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| CN111368250B (en) * | 2018-12-26 | 2023-08-15 | 北京欣奕华科技有限公司 | Data processing system, method and equipment based on Fourier transformation/inverse transformation |
| CN111562900A (en) * | 2020-07-20 | 2020-08-21 | 长沙海格北斗信息技术有限公司 | FFT (fast Fourier transform) calculation method, calculation module and chip for high-precision navigation |
| CN112835073A (en) * | 2021-02-05 | 2021-05-25 | 重庆九洲星熠导航设备有限公司 | FFT (fast Fourier transform) processor for satellite signal acquisition |
| CN116094896B (en) * | 2023-04-12 | 2023-06-30 | 高拓讯达(北京)微电子股份有限公司 | OFDM system control method, device, computer equipment and medium |
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