TW201227351A - Recursive modified discrete cosine transform and inverse discrete cosine transform system with a computing kernel of RDFT - Google Patents

Abstract

The invention provides a recursive modified discrete cosine transform and inverse modified discrete cosine transform system, whose computing kernel is a Recursive Discrete Fourier Transform (RDFT). The system is implemented with a low core area, low computation complexity and high performance recursive discrete Fourier transform. Moreover, the system can be re-usable, re-configurable, and can be easily used in any taps of discrete Fourier transform. The system can play a kernel of the MDCT/IMDCT to achieve the reusability so as to increase the utilization.

Description

201227351 VI. Description of the Invention: [Technical Field] The present invention relates to the field of digital signal processing, and more particularly to a system of modified discrete cosine positive conversion with discrete Fourier transform as the core [Prior Art] Awareness is rising, and various industries around the world are constantly advocating energy conservation and carbon reduction. For the 3C industry, the green energy design will be the future trend. In terms of mobile multimedia devices, the functionality is no longer a single nature in the past. In addition to the integration of multiple high compression ratio music formats (MP3, AC-3, ACC, etc.), it also provides instant broadcast listening and recording. The ability to incorporate such a versatile product into the main concept of green energy design—low cost, high performance, configurability, and reusability—is still a challenge. At the same time, it is not easy to integrate different systems or codecs (C 〇 d e c) on the same playback platform and effectively reduce the similarity. With the development of technology and the continuous innovation of 3C (Computer, Communication, Consumer Electronics) product technology, Fast Fourier Transform (FFT) has been widely used, especially in communication. Due to the transmission process, Orthogonal Frequency-Division Multiplexing (OFDM) technology is commonly used to perform modulation and demodulation (2012), and OFDM is required to be used internally. Fourier Transform (Fourier Transform, FFT) ° Fast Fourier Transform (Frr) Since 965, by JW 乂 丨 及 and W. Tukey, it has been paid attention to. The early research on FFT is mainly devoted to methods. The analysis of complexity, the discussion and the amount of computation required, and the introduction of more efficient algorithms. In recent years, there are still many studies that constantly seek the lower limit of FFT complexity.

Traditionally, most FFT conversions are handled by software. A large number of multiplications and additions are required during the conversion process, which undoubtedly increases the burden on the processor. For mobile multimedia devices, it is often limited by the computing power of the processor, resulting in differences in conversion speed and results. Therefore, the most common conventional techniques 硬 hardwareize this part of the operation, which has the advantage of reducing the burden on the processor, and the same day operation can increase the conversion speed due to the independent operation of the hardware. Its hard aa killing can be roughly recursive (recursive) and parallel 丨丨e丨). Parallel architecture and other implementations, common memory-based FFT, MDC (Multi-path Delay)

Commutator, MDC) FFT and SDF (Single-path Delay)

Feedbaek, SDF) FFT, etc. The advantage is that the conversion speed is fast, but the disadvantage is that (1) the specification points are poorly adjusted, and the power points generally used for the second power point 'has to be limited and difficult to be used in other aspects after the hardware is implemented; (2) ) A large number of memory components are required, which leads to an excessive wafer area and an increase in power consumption. In recent years, a new digital broadcasting technology has appeared. This technology is called the digital ball radio broadcast (D丨丨汪丨M〇dja丨e, drm), and the number of specifications used is the power of the traditional two. The points are different, respectively, 201227351 is N=288, 256, 176, 112. For a parallel architecture, this is a new challenge. In order to achieve such a design, additional hardware must be planned to mix and match existing architectures, K. Dong-Sun, et al_ in Consumer Electronics, IEEE Transactions on, vol. 54, pp. 1590-1594, 2008 This design is adopted in the paper of r Design of a mixed prime factor FFT for portable digital radio mondiale receiver. Compared with the recursive architecture, neither the power of the second power nor the power of the second power need to be redesigned, and the concept of repeated application of the green energy design can be directly achieved, but the only consideration is the operation speed. problem. Therefore, how to design an efficient recursive architecture circuit becomes a challenge. The music format MP3 (MPEG-1 Audio Layer 3, MP3), AC-3 (Dolby AC-3, AC-3) and AAC (Advanced Audio Coding, A AC) have their signal-time/frequency conversion analysis at the encoding end. It is implemented by Modified Discrete Cosine Transform (MDCT), and the decoding end is also implemented by Inverse Modified Discrete Cosine Transform (IMDCT), so subband analysis/synthesis is performed. (subband analysis/synthesis) Based on MDCT/IMDCT, it has been widely used in various audio codec standards. However, the computational complexity of MDCT/IMDCT is the same as that of FFT, which has a large number of multiplication and addition operations, and this operation has a certain proportion in the entire codec process. So there is the concept of realizing the computational independent hardware of MDCT/IMDCT to reduce the burden on the processor. A conventional technique uses FFT as the core parallel architecture to achieve this, but this architecture will have poor application flexibility in 201227351 'often limited by the power of two power specifications, a large number of memory components and so on. In order to improve the limitation of the number of points, another conventional technique adopts a parallel architecture and a recursive architecture with DCT (Discrete Cosine Transform, DCT) as the core, and is applied to the power of the non-two power. For the parallel architecture, it requires complex control methods and extremely high hardware requirements, which will be detrimental to the hardware implementation of multi-format multi-points. For the recursive architecture, C· Hwang-Cheng and L.

Jie-Cherng recursively using Sinusoidal/Cosinusoidal in the paper "Regressive implement at 丨〇. for the forward and inverse MDCT in MPEG audio coding" published by Signal Processing Letters, IEEE, vol. 3, pp. 116-118, 1996. Recursive MDCT/IMDCT (RMDCT/RIMDCT) architecture. C. Che_H〇ng et al in Circuits and Systems II: Analog and Digital Signal

Processing, IEEE Transactions on, vol. 50, pp. 38-45, 2003 published paper "Recursive architectures f〇r reaHzing modified discrete cosine transform and its inverse" and S. Lai, et al. on IEEE Transactions on Circuits And Systems II: Express Briefs, voi. 56, pp. 793-797, 2009 published "Common architecture design of novel recursive MDCT and IMDCT algorithms for application to AAC, AAC in DRM' and MP3 codecs" using Chebyshev polynomials Propose the efficient and high-output RMDCT/RIMDCT architecture and implementation. Compared with the parallel architecture, the recursive architecture has the advantages of simple architecture and control design, and can dynamically switch the specification point 201227351 without changing the hardware architecture. If the hardware resources are limited, this architecture will be good. The choice, but its shortcomings need to have more calculation cycles. Although the system of discrete cosine positive conversion and inverse conversion has been developed for many years, in order to further reduce the computational complexity, reduce the hardware cost, and improve the performance of data calculation, the system of the aforementioned discrete cosine positive conversion still needs improvement. . SUMMARY OF THE INVENTION The main object of the present invention is to provide a system for correcting discrete cosine transforming and inverse transforming with discrete Fourier transform as a core, which can realize recursive discrete with low area, low complexity and high performance. Recursive Discrete Fourier Transform (RDFT) also has an energy-saving, reusable and configurable green energy design concept that can be easily used for DFT conversion of any specification point and also acts as MDCT /IMDCT core, to achieve RDFT can be reused to increase utilization. According to a feature of the present invention, the present invention provides a system for modifying a discrete cosine transform with a discrete Fourier transform as a core, comprising a data sequential shifting unit, a data reordering unit, a first rotating unit, A discrete Fourier transform unit of N/4 points, a second rotation operation unit, and a de-interleaving (de_inteHeave) operation unit. The data sequential shifting unit receives 1^ input digit signals, and performs sequential shift programming on the N digit signals to generate N first temporary signals, wherein N is a positive integer of a multiple of 4. The data reordering unit is connected to the data sequential shifting unit, and performs a data reordering operation on the first temporary signal 201227351 to generate N/4 second temporary signals. The first rotation unit is coupled to the data reordering unit to perform a first rotation operation on the second temporary signal to generate a third temporary signal. The discrete Fourier transform single (4) of the NM points is connected to the known transfer device grass, for the N/4 flute-cylinder. The second temporary signal performs discrete Fried/ _ to generate _ a fourth temporary signal. The discrete Fourier transform unit of the N/4 points includes a first flute, a first adder, a first adder

The first-multiplier, the first _shift register, the second multiplexer, the delay, the second multiplication, the brother, the younger brother, the Xigongyi, and the third multiplication: first! Four multiplexers, a second adder', and a second delay. "7 benefits are used to receive the N/4 third temporary signals and - the first multiplication signal, and generate a cage for the rice to the first multiplex signal. The first-adder is connected to the first Xigongyi, in order to add the first-multiplex signal and a second delay number to produce a late m... fourth temporary signal. Yan Xuan-multiplication letter...adder' to the fourth temporary signal Multiplying with the - cosine function signal &, - shift register to connect the second - multiply signal. The number is shifted to produce Ϊ ^ to connect the first multiplier to JL The first-shift signal. The second multiplex shift signal, γ 'receives the first-multiplication signal and the first-multiple bit. ft number' to take a flute-炙丁〇〇 to the first a first lingering signal. The first delaying device is connected to generate a -1st fourth temporary signal for late delay-delay (1). The second multiplier is connected to the delaying device to delay the first delay Row multiplication operation to generate a first multiplication, ... string function signal to connect to the first delay method: number. The third multiplexer, ^ installed And the δ 玄 second multiplier receives the first late a 9 201227351 to output a third multiplexer delay signal and the second multiplied signal number. The third multiplier is connected to the third multi-jade (4) the third multiplexer signal is multiplied by -1 to generate a third multiplication signal. The fourth multiplexer is coupled to the second multiplexer to receive the second multiplexer signal and the a delay signal to rotate the fourth multiplexer signal. The second adder is coupled to the third multiplier and the fourth multiplexer to signal the third multiplier signal and the fourth multiplexer signal Performing an addition operation to generate a second addition signal. The second delay is coupled to the second adder to delay the "Hai first addition signal to generate the second delay apostrophe. 戎Second rotation The arithmetic unit is connected to the discrete Fourier transform unit 该 of the N/4 points to perform a second rotation operation on the N/4 fourth temporary signal and the second addition signal to generate N/4 fifth temporary a de-interleave operation unit connected to the second Rotating the arithmetic unit to perform a deinterleaving operation on the N/4 fifth temporary signals to generate N output signals. According to another feature of the present invention, the present invention provides a modified discrete cosine with discrete Fourier transform as the core The inverse conversion system includes a data reordering unit ′—a first rotation operation unit, an N/4 point discrete Fourier transform unit, a second rotation operation unit, and a deinterleave operation unit. The data reordering unit receives N/2 round digit signals to perform a data reordering operation on the n/2 input digit signals to generate N/4 sixth temporary signals, wherein N is a positive integer of a multiple of 4 The first rotation operation unit is connected to the data reordering unit to perform a first rotation operation on the N/4 sixth temporary signals to generate N/4 seventh temporary signals. The n/4 points of the discrete Fourier 201227351 leaf conversion unit are connected to the first-rotation operation unit, and (4) the n/4 temporary signal performs a discrete Fourier transform to generate an N/4 (four) number. The discrete Fourier transform unit of the NM points includes a first: a first adder, a first multiplier, a first shifter, a second multiplexer, a first delay, a second multiplier - a third multiplexer, a second multiplier, a fourth multiplexer, _ _.

And - the second delay. The first multiplexer is configured to receive the N: temporary signal and the second multiplication signal, and generate a _th multiplex signal. The first adder is coupled to the first multi-guard to add the first multi-gas number and the second delay signal to generate the eighth temporary number. The first multiplier is coupled to the first adder to multiply the eighth temporary signal and a cosine function signal to generate a first multiplication signal. The first shift register is coupled to the first multiplier to perform a shift operation on the first multiplying signal to generate a first shift signal. The second multiplexer is connected to the first multiplier to receive the first multiplication signal and the first shift signal to output a second multiplexer signal. The first delay is coupled to the first adder to delay the transport of the eighth temporary signal to generate a first delay signal. The second multiplying method is coupled to the first delay device ‘ to multiply the first delay signal and a positive chord function signal to generate the second multiplication signal. The second multiplexer is connected to the first delay device and the second multiplier receives the first delay signal and the second multiplication signal to output a third multiplexer signal. The third multiplier is coupled to the third multiplexer to multiply the second multiplexer signal and -丨 to generate a third multiplying sfl number. The fourth multiplexer is connected to the second multiplexer to receive the second 201227351 multiplexer signal and the second delay signal to output a fourth multiplexer signal. The second adder is coupled to the third multiplier and the fourth multiplexer to add the third multiplier signal and the fourth multiplexer signal to generate a second add signal. The second delay is coupled to the second adder to delay the second addition signal to generate the second delay signal. The second rotation operation unit is connected to the discrete Fourier transform unit of the N/4 points, and performs a second rotation operation on the N/4 components consisting of the eighth temporary signal and the second addition signal to generate N/4 The ninth temporary signal. The de inter leave operation unit is coupled to the second rotation operation unit to perform a deinterleave operation on the N/4 ninth temporary signals to generate N output signals. [Embodiment] Modified Discrete Cosine Transform (MDCT) uses DFT-assisted operation. It only needs to use N/4 DFT operation plus pre- and post-processing to complete MDCT operation, and the overall calculation amount is reduced a lot. The method of implementing the MDCT operation with the DFT as the core enables the use of the discrete Fourier transform unit 160 of the N/4 points for recursive DFT architecture. First, the MDCT transformation can be expressed using the following formula: n-ι / Μ 1 π\ = ^ a(n) cos Μ « + —+ 2)^) # ίί = 0·1· -·Μ~ί 11=0 V ^. Using the variable transformation η = η - Ν / 4 into the formula of the MDCT transformation: S 'V / 4-1 η = · ν / 4 Ν 12 201227351 SAf / 4-l

, 2N ^ Λ (n - y) (2n ten l) (2fc ten 1) n=.V/4 AV~l >:>"-^^ cos J^^(2n + l)(2fc + l) n=*V/4

, 2N 5.V/4-1 η=Λ. Λτ-1

〉:x^ ~ —^ cos I (2η -τ X)(2k -l· 1) η=λ*/4

, 2/V AV4-1 ~ X x(^ + 4W)C05(:^^2n"l"1^2A:+^ η=0 .V-1 ^ .r(n)cos (2η + l)( 2fe + 1) (1) n = 0 where

((η)

X ( ^ \ Ν λ· η 丁一λ' , Ο < η <--1 ν 4 / 4 κ)' < η < Λ» - 1 Let k'=Nk: -l, then the formula ( 1) The Cosine function in the equation can be expressed as: cos (2n + 1)(23⁄4 + 1)^ = cos (2η + 1)(2Λ? - 2ke - l) j cos (?r( 2n + 1) One (2ti + l)(2fc'+ 1) 13 201227351 =(5(2n + l)(2fc'+ 1) j (2) From the result of equation (2): X(2k + 1 ) = -X{N -2k-2), (3) Therefore, only the case of X(2k) will be considered. Then, using the symmetry of cos(9), based on Θ = =π, the original form can be re-formulated as . — i 欠(2A〇= I i (n)cos (2n + 1) (from + 1) n=Q ^ / i(n)c〇5{ —(2n + l)(4fc-}- 1) n =0 π

4*x(W — n — l)cos I ——(2(N — n — 1) + l)(4fc + i) V2N )1 i(n)cosl-(2n + l)(4fe + l) Σ {i(n)c〇s(^ n=0 +x(W — n — l)c〇5 ίπ(4^ +1)- (2n + l)(4A: + l) x(n)cos | —(2n + l)(4fc+ l) n=0 π —x(W — n — l)cos I — (2n + l)(4A: + l) —1 ^ {x(n) — ί (W —n — l)}c〇5 i —(2n + l)(4fc + l) n=0 \ y (4) 14 201227351 Again using the symmetry of cos(;e;), based on θ = π/2 Equation (2) can be re-table as. X(2fc) = ^{x(2n) — x{N — 2n — l)]cos (4n + l)(4/c + l) n=0

M Λ-1 n=0

COS π (2(*—2n-l)+l)(4fc + l)

2N

Λ· ^ (x(2n) — x(W — 2n — i)}cos i— (4n + l)(4fc + l)

n=G \ *J n=0 cos (4fc + (4n + l)(4fc + l)

.V 4 〆^ (x(2n) — :?·(Λ'a 2n — l)}cos (Φη + l)(4/c + 1) jn=0 , / .V •a Σ P —2n - Ό_ $ (all +2ti) j5in (巧(4n+丄)(4*+" n=0 "year-i

Re ^ |(x(2n) — x{N — 2n — 1)) + i — 2n — 1 n=0 — I XV2 7Γ + 2n) JJejcpI —i — (4n + l)(4fc + l) by exponent The characteristics of the function: Η 15 (5) 201227351 & 10 5 (eg + 1 +) + 1)) = exp t — (4n + l)^exp^—(4n + l)(4ic + l) exp (-1· (4n + 1) (4fc + 1) where xi2k+i)

Re T" ^ |—i(x(2n) — .r(W — 2n — 1)) + — 2n — 1 n=0

Im meaning (S + 2«))} exp (-i^ (4n + l)(4fc + 1)

r.V ^ |(x(2?i) — λ (Λ/ — 2n — 1)) + i — 2n — 1 n=0 ίτ-*- 2nJ \\exP\ π

2N (4n + l)(4fc + 1) (6) Define the new symbol ^(k), denoted as ΛΓ Τ' n=0 (7) where λ'η = (x(2w) _ x(^N — 2n — 1 )) + f (Especial (^· - 2τι — 1) _ ·Χ(·^· + 2w)) Equation (7) can be rewritten as: 16 (8)201227351 2ττ , N Λ = 〇·~—one 1 / 4 where xjjo

n=〇2ΤΓ, exp / 2π \ li—-nfc] \ A//4 } From equations (5) and (6), we know that /?e(;?(fc)) = A,(2Ar) , N — 4

Hn (;?(fc)) = X(2fc + $) , fc = 0, the same (9) (10) According to formula (3) and formula (1 0), k = 〇 + - X ( A/ — — 2) , k =--1 to 0 4 (11) = -X(2k+l) 可The result of the formula (u) shows that··

X(2k + 1) = -Im

X /N I--k a 1 \4

N , k = --1 4 (12) From the previous derivation process, the mdct conversion process can be easily organized into the following steps: 1. The input data is simply shifted and arranged into a complex form. 2- The pre-processing of the complex data execution coefficient by {3(_丨(271/1^)(11 + (1/8)))). The data after the pre-processing operation is NM point DFT conversion. 17 201227351 4. The data of the conversion completion is executed after the coefficient exp(_i(27l/N)(k + (1/8))) multiplication operation. 5. Finally, the data will be systematically rearranged to convert the output. The following is the DFT-based IMDCT method, which does not use dft to convert to IDFT and then implements 11^11) (: D, because such an approach cannot effectively merge with the results) to achieve the core common architecture First, the definition of an IMDCT transformation can be expressed using the following formula: Λ(«)=

Secondly, the symmetry of the output result can be considered as long as the even part is considered, so the IMDCT conversion can be expressed by the following formula:

(4n + 1 + j) (2k + l)^ can be rewritten as a formula to expand the cosine function in the IMDCT conversion formula (13):

Considering the symmetry of & considering the symmetry of A, we can derive the formula (M) and the formula (15): (2n) = ^ (-DftYW2fc)(C(n.fc)-5(n.fc)) fc =〇' (14) (15)201227351 Λ;/4-1

X (¥+2π)= ^ 〇k){-C(:nt k) - 5(η, fe)^ A*=〇+X (Prepared - - 1) (C(rU) - S(n, fc ))j where C(nf λ·) = cos '(4n + l)(4fc + 1)tt,

2N

S(nt k) = 5in r(4n + l)(4fc + 1

2/V -) Combine the formula (14) and the formula (15), and the result is the formula (16) x(2n) + ix + 2n j Λν/4-l ^ (-Ι)%βχρ(-ί λ=0 2πNji •nk >exp\

2/Γ / *一 s N (n ^ i)) (16) where = f^(2Ar) -r iX — 2k — exp(—i~^k + —j

Finally, according to the paper "A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation" published by G. Chih-Da Chien and J. Guo in 2007, the output in equation (16) can be rearranged. The multiplication method of the exemption factor w8-i's rule is: 19 201227351 x(2n) = /?e (il (〇)) x(2n + 1) = —Im WH) x(- + = Im(x( n)) \ (;+ 2« + 1)=edge ("-i - „)) r(?+2n)=irn(K€+n)) 伶+ 2n + 1) = -Re(-1 - „)) x (-^7 + 27i) = ~i?e(x(n))

X (t + 2n + 1 ί(η)= where r.v/4-ι \ Σ(-i)乂 find p(_i5nfc) hit p(-f U=0 \

o Observe the previous MDCT conversion and IMDCT conversion. The MDCT/IMDCT conversion can be the same except that the input 'output data is rearranged ^ 2 differently, including the coefficients of the pre- and post-processing, and the N/4 DFT as the core. Architecture. Therefore, the entire river raft (: D / 11 ^ 1 :) (^ ^ change system can be as shown in Figure 1) Figure 1 is a discrete Fourier transform to the core of the modified discrete cosine forward conversion system 110, and A schematic diagram of a modified discrete cosine inverse conversion system 120. The modified discrete cosine forward conversion system 〇1〇 includes a data sequential shifting unit 13〇, a data reordering unit 140, and a first rotating computing unit u〇, — N/4 points of discrete Fourier 20 201227351 Conversion unit 160' - second rotation operation unit 17〇, and a de-interleave operation unit 18〇. The data sequence shifting unit 丨3〇 receives\ Inputting a digital signal x(n), performing sequential shift programming on the N digital signals to generate 1^ first temporary signal rings „), wherein !^ is a positive integer of a multiple of 4. The data is reordered. The unit 丨4〇 is connected to the data sequence shifting arrangement unit 130, and performs data reordering on the first temporary signal 玎... to generate N/4 second temporary signals & 忒 first rotation operation Unit 1 5〇 is connected to the data The new sorting unit 140 performs a first rotation operation on the N/4 second temporary signals to generate N/4 third temporary signals. The discrete Fourier transform unit 16 of the NM points is connected to the first The rotation operation unit 15 performs discrete Fourier transform on the N/4 third temporary signals to generate N/4 fourth temporary signals. The N/4-point discrete Fourier transform unit 1 60 is a recursive dft The Hierarchy-rotation transport unit 7兀丨 is connected to the N/4 point discrete Fourier transform unit 丨60, and performs a second rotation on the N/4 fourth temporary signals and the second addition signal Calculating to generate N/4 fifth temporary signals X(k) ° " The de-interleaving operation unit 18〇 is connected to the second rotating computing unit 丨7〇' to the NM The five temporary signals are "executively interleaved to generate N output signals. It is known from the foregoing formula that the sequence shift 130 of the data is expressed by the following formula: 21 201227351

The data is reordered and slid open, 1 40 with the following cock + time.

Time signal. The first rotation operation unit 150 performs the first rotation operation on the N/4 second temporary signals by the following formula: 271 1 exp(—i—(t —)) 1 N 8 where the '/system is one by 0 To the N/4-1 indicator. The second rotation operation unit 170 performs a second rotation operation on the N/4 fourth temporary signals by the following formula: wherein, the index is an index from 0 to N/4-1. The de-interleave operation unit 180 performs deinterleaving on the NM fifth temporary signals by the following formula: X(2k) = Re(X(k)) X(2k + l) = - Im(X(-

22 201227351 Among them, the NM fifth temporary signals are the N output signals.

Figure 2 is a schematic illustration of the N/4 point discrete Fourier transform unit 16A of the present invention. The N/4 point discrete Fourier transform unit 16A includes a first multiplexer 205, a first adder 21A, a first multiplier 215, a first shift register 220, and a second The multiplexer 225, a first delay benefit 23 0, a second multiplier 23 5, a third multiplexer 24 〇, a third multiplier 245, a fourth multiplexer 25 〇, a second addition The device 255 and a second delay 260. a second multiplication signal and generating a first multiplex signal. The first adder 2丨0 is connected to the first multiplexer 2〇5 to add the first multiplex signal and a second delay signal to generate the fourth temporary signal. Bu. The first multiplication mode 2 1 5 is connected to the first adder 2 1 〇 to multiply the fourth temporary apostrophe and the cosine function signal to generate a first multiplication signal. The first shift register 22G is connected to the first multiplier 215 to perform a shift operation by the multiplication signal to generate a "first shift signal" for outputting a second multiplexer signal. The second multiplexer 225 is connected to the first multiplier 215 and the first, receiving side first multiplication apostrophe and the first shifting signal 23 201227351. The second delay 230 is connected to the first adder 21 〇 to The fourth temporary signal is delayed to generate a first delay signal. The first multiplier 235 is coupled to the first delay device 230 to multiply the first delay signal and a sinusoidal function signal to generate the second multiplication signal. The second multiplexer 240 is connected to the first delay device 23 and the second multiplier 235, and receives the first delay signal and the second multiplication signal ’ to output a third multiplexer signal. A third multiplier 245 is coupled to the third multiplexer 24A to multiply the third multiplexer signal by -1 to produce a third multiply signal. The fourth multiplexer 250 is coupled to the second multiplexer 225 to receive the second multiplexer signal and the second delay signal to rotate a fourth multiplexer signal. The second adder 255 is coupled to the third multiplier 245 and the fourth multiplexer 250 to add the third multiplier signal and the fourth multiplexer signal to generate a second add signal. The second delay 260 is coupled to the second adder 255 to delay the second addition signal to generate the second delay signal. Referring again to Figure 1, there is shown a schematic diagram of a modified discrete cosine transforming system 11 〇 and a modified discrete cosine inverse transform system 120 with discrete Fourier transform as the core. The modified discrete cosine inverse conversion system 120 includes a data reordering unit 19A, a first rotating operation unit 150, an N/4 point discrete Fourier transform unit 16A, and a second rotating transport unit! 7〇, and a deinteriave (deinterieave) arithmetic unit. 24 201227351 The data reordering unit 190 receives N/2 input digit signals, and performs data reordering operation on the N/2 input digit signals to generate N/4 sixth temporary signals a ' A positive integer of multiples of 4. 6H first red transport unit 丨5〇 connected to the data reordering single TC190, perform a first rotating nose for the N/4 sixth temporary signals to generate N/4 seventh temporary signals .

The N/4 point discrete Fourier transform unit is coupled to the first rotational operation unit το 1 5G ′ to perform discrete Fourier transform on the N/4 seventh temporary signals to generate N/4 eighth temporary signals. The second rotation operation unit 170 is connected to the N/4 points of the discrete Fourier transform unit 160, and performs a second rotation operation on the N/4 eighth temporary signals to generate NM ninth temporary signal rings. .... The deinterleaving operation unit 丨8〇 is connected to the second rotation transfer different unit, and performs a deinterleaving operation on the N/4 ninth temporary signal pairs to generate N output signals 〆^. The far data reordering unit 19 is represented by the following formula:

Xk - X(2k) + iX{N/2-2k-l), wherein X moxibustion is the N/4 sixth temporary signals, and ^ is the N/2 input digital signals. The first rotation operation unit 15 〇 performs the first rotation operation on the N/4 sixth temporary signals/moxibuses by the following formula: 25 201227351 exp(~i~(t + in , N 8 中 中 ' i An index from 〇 to N/4-1 "The second rotation operation unit 17 第二 performs the second rotation operation on the 1^[/4 eighth temporary signals by the following formula: / 1 exP(-l -7r(t'+~)) » N 8 is an index from 〇 to N/4-1. The deinterleave unit deinterleaves the ν/4 ninth temporary signals. The operation is expressed by the following formula: -v(2n) = Re + , r(2n + i)=—such as (cross (w 1 — n)) + 2n) = im (cross (η))

λ: + 2n + l) = — J?e (branch (I -1 - η)) Λ - x(^+2n)=/m^(^+n)) (y+2n + l)=-J ?e^(^-ln] τ + 2nj = -i?e(x(n)) , (^+2n+1)=/nl (ί(?-1-η), for this Ν/4 The ninth temporary signal is the N rounds of signals. Fig. 3 is a schematic diagram of a conventional improved RDFT architecture. As can be seen from Fig. 3, the conventional improved RDFT architecture requires four real multipliers and five complex numbers plus 26 201227351 But further observation, we can find that the operation of multiplying jsinx (ek) coefficient is regarded as a valid value in the last cycle, if two multipliers are used to support this in hardware implementation The operation is not only very inefficient for the multiplier, but also a waste in both wafer area and power consumption.

It can be seen from Table 1 that the number of transistors in the register and the multiplexer is negligible compared with the multiplier, so the register and the multiplexer will be added to multiply the jsin(ek) coefficient and the cos(ek) coefficient. The device is shared, but the relative cost must be an additional cycle to perform the jsin(ek) coefficient multiplication. Figure 4 is a block diagram of the improved RDFT architecture of the shared multiplier of Figure 3, and Figure 5 is the design of the shared multiplier of Figure 4. As a result, the efficiency of the multiplier is not only 100% but also greatly improved in area and power. The code for c〇eff_sei in Figure 5 is: — define cos_value= 1'bO define sin_value=l'bl if(loop_cycie=N+1 ) coeff_sel=sin_ value else coeff_sel=cos value o Table 1 Electricity for 24-Bits components Crystal Number Component 拴 Locker Adder Multiplier multiplexer Number of Transistors 240 672 18624 192 Looking further at Figure 4, you can find three complex adders surrounded by dashed lines in the graph, the efficiency of which is the efficiency of the multiplier discussed earlier. The problem is the same, 27 201227351 are in the last cycle _, the operation results are used... Once again, the modified RDFT architecture is modified. How many multiplexes are needed for this modification? ! That is, Figure 2 shows the result of the modification. After hardware improvement, comparing Figure 2 with Figure 3 for hardware evaluation, we can see that the hardware requirements are reduced from the original 5 complex adders and 4 real multipliers to 2 complex adders and 2 real multipliers. The rate is about 47.2%. The advantage of the Common Factor method is that the decomposition of N can be any number of 'decompositions. The closer the two numbers are, the more efficient the pipeline is. Vietnam's 'but its shortcomings have the problem of the rotation factor' will increase the computational complexity of multiplication. Accuracy. The advantage of the Prime Factor method is that there is no problem of the twiddle factor. The disadvantage is that the decomposition of N needs to be mutually primed. Such decomposition may lead to a decrease in the efficiency of the pipeline, and the point for the power. The number does not apply. S.-C. Lai, et al., Circuits and Systems II: Express Briefs, IEEE Transactions on, pp. 647-651, 2010. Low-Computation cycle, Power-Efficient and Reconfigurable Design of Recursive DFT for portabie In Digital Radio Mondiale Receiver, the number of specification points n=256 is directly calculated in one-dimensional form, and it is not ideal in terms of calculation cycle, complexity and SNR value. Therefore, in the hardware planning, a hybrid type will be adopted to improve the overall efficiency. As for the problem of the twiddle factor, it will be solved without adding hardware. Table 2 lists the c and m value decomposition methods for the DRM required specification points in the hybrid method. 28 201227351

Finally, based on the results of Figure 2 and the concept of pipelined, the hardware architecture with two-stage pipelines can be cut out. The first-level part is planned to be responsible for the c-point DFT operation, while the second-level part is planned to be responsible. (7) Point plus calculation.

Since the RDFT architecture has double production, two sets of two DFT hardware are arranged at the second level to handle the results of the pre-stage operation. It can be seen from Table 2 that c is even, and when k=0, c/2, the RDFT architecture will only have a single output, and for the second level, a set of hardware will be inoperable, resulting in waste of resources. In order to improve this problem, a simple accumulating circuit as shown in Fig. 6 will be added in the first stage, so that lc=0, c/2 can be simultaneously operated to generate two results for use in the next stage. Finally, in order to simplify the number of die 1/〇 pins, the RDFT hardware sf will be output sequentially using the multiplexer. The hardware architecture is shown in Figure 7. In order to effectively provide coefficients to the calculation circuit, the 'commonly common practice is to use external input'. Relatively speaking, when the accuracy of the coefficient needs to be asked, then more I/O pins are needed to increase the number of bits of the coefficient input. However, this practice will cause the PAD to be too large and the overall area will become larger. Another method is to read the memory (Read only Memory, ROM) of the built-in memory of the chip. Using the look-up table method (L〇〇k_up Table, [υτ) to know the coefficient, the table 3 knows the 'area size' along with the number of points. Increase and increase, for the recursive architecture, the advantage is that it has a small area. If the LUT is inevitably increased by 29 201227351 area and power consumption, it will contradict this characteristic. The method is self-generated by the circuit, and the simple circuit And the initial value is given, and other required coefficients are calculated by the initial value. This method is more flexible in adjusting the number of specifications in the future, and the required hardware is smaller in the realization of the wafer. The present invention is based on the low area. The concept of energy saving and multi-standard, so take the circuit self-generation method. Table 3 Comparison of 24-Bits memory element size single and double 记忆 memory large area (mm勹 delay (US) small double 埠單埠 double 256 0.186 0.082 1.33 1.24 512 0.294 0.129 1.42 1.25 1K 0.467 0.223 1.46 1.26 2K 0.816 0.354 1.49 1.28 8K 2.718 1.180 1.89 1.65 The way the coefficient is self-generated is based on the trigonometric function and the angular formula theorem. The sum and angle formulas are: (17) (18), let cos(« + /?) = _ Si.„(rt)Si7l(分). sm(a + 幻=伽(")奶〇?) + co„(a)咖(6). The coefficient variation of the RDFT architecture circuit is determined by the variable k θ = 2π/ Ν, then cos(ke) and sin(kG) can be re-formulated as: (19) (20) Equation (18) expands, cos(k0) = cos sin^kff) = sin Formula (1 9) and formula (20) According to the formula (1 7), a recursive relation can be obtained: 30 201227351 (21) (22) ,·..,Ν-ΐ 〇JS(fc0) = cos((fc - l)0)cos (0) _ (8), = 3: M((fc - l)0)cos(0) + cos((fc — . If cos(0) and sin(0) are known to be initial values' then k=1 2, the corresponding coefficient values can be generated by the formula (21) and the formula (22). RDFT architecture while taking a hybrid method c〇mmon Factor and Factor method prime, so there must be rotated

The problem caused by the factor coefficient. Continued to explore how the twiddle factor is equally generated using equations (17) and (18). Since the change of the rotation factor coefficient is controlled by the variables 屮 and ^, it can be seen that the red-turn factor needs two different coefficient values in the same time, and the order of demand is as shown in FIG. Tiangu δ °" know, coefficient,," 4 t value is incremented by the value of ηι, until the factor of - is completed, then increase or decrease the value of h! And set „|=〇, repeat execution to the east. Therefore, it is known from these actions that there are three sets of initial values, and the two groups are responsible for calculating the factor ' _ group determined by /7 & corresponding to k2 ' k' n| Responsible for calculating the factor 'factor' determined by ^ is as follows: set Θ = 2π / Ν, 2 (10) = (7) 咻 1 and coffee (10) = = coffee (a), then the rotation factor can be expressed as = cos (nikt2d ^- Jsin(n:ikt2e) (23) = cos(nief}~jsin(niet),

Wjv - cosing''2Θ) — jsin(n^k"2Θ) = <:〇«)-fine (〇〇31 (24) 201227351 Formula (23), formula (24) according to formula (17), formula (18) Expand, available: ¢ 705 (740,) = — l) 0,) i: OS (0,) - - . (25) = - l^eOcos^') + ¢05((^ - l)0f)sin(0f). (26) = 0)5((74 — l)0n)a>s(0") — — l)f)sin(0”).(27) sir^n/")=along — l)0&quot ;)cos(0M) + (28) and cos(f) · sin(f) · cos(〇.咖(0") can also be generated by formula (17) and formula (18). Get: = i: os((fc, - l)0)cos(0) — sin((fcf2 — l)0)sin(0). (29) •sinQSe) = 5ίη((Λ'2 — l) 0) c: os(0) + — l) 0) sin(0). (30) cos(fc"2ff) = ^5((^^2 + l)0}cos(—— 5in((fcM2 + 1)0)5171(-6^) =c〇5((fcn2 + l )))cos(0) + 5ίη((λΜ2 + l)0)sm(0) (3 1 ) 5m(/cM2ff) = 5111((3⁄41^ + l)e)c〇5(—+ cos( (fen2 + l)0)sm(—β) =sin((fc"2 + l)0)<ros(0) -+ l)0)sin(0). (3 2) If cos(0) 5in(0) cojs(0,) ·5ίη(0')cos(f) ·5ίη(0π) Given the initial value, all the twiddle factors can be derived by equations (25) through (32) The foregoing has explained how to calculate all the coefficient values by the given initial value, including the twiddle factor part required by the Common Factor method, but does not mention how to use the existing hardware architecture to calculate all From the formula (21) to the formula (22), it is known that each coefficient requires two multiplication operations. If the multiplier is directly used to support the calculation of this part, there are four more, which will be Great burden and not conducive to energy saving, 32 201227351

The low-area design does not have the concept of green energy design. In order to improve the efficiency of the multiplier, the multiplier problem is solved by the method shared by the multiplier. For a group of HDFT circuit architectures, there are two real multipliers, so only two extra cycles are needed to bear. Figure 5 can be modified as shown in Figure 9. Fig. 9 is a schematic diagram of the cos coefficient sharing multiplier of the present invention, wherein Fig. 9 only lists the design of the cos coefficient sharing multiplier, and the sin coefficient only needs to exchange the 1 〇 and η inputs of the 4 pairs of I multiplexers. The coeff_sel and coeff_se2 codes in Figure 9 are: define cos_value=l'bO define sin_value= l'b 1 if(loop_cycle = N+1) coeff_sel = sin_value else coeff_sel=cos_value and define nodeA_value=2'b00 define nodeB_value=2 'bO 1 define cos_value=2'b 1 0 define sin_value=2'b 1 1 if(loop_cycle=N+3) coeff_sel2=cos_value else if(loop_cycle=N + 2) coeff_sel2= sinvalue else if(loop_cycle=N+1 Coeff_sel2= nodeB_value else 201227351 coeff_sel2= nodeA—value. As for the twiddle factor, it can be completed by the design of the shared multiplier, but the twiddle factor requires two different sets of coefficient values in the same time, and the multiplication operation of eight times can be found from equations (29) to (32). If the 2d-form architecture is supported by the first-level architecture, it will take four cycles to bear. This will cause the gap between the first-level and the second-level to become larger and larger, resulting in a significant decrease in the efficiency of the pipeline. The second level of the architecture has two sets of RDFT architectures, so there will be four real multipliers, and the processing of the twiddle factor can be reduced to one cycle'. Therefore, the second level is used to deal with the twiddle factor as the best choice. Refer to Figure 9 for the design of the shared multiplier. The problem and the way of generating the coefficient can be completely solved by the proposed scheme. Finally, based on this scheme, how the architecture hardware implementation of the present invention is implemented will be explained. The hardware architecture is implemented under these conditions, and the conditions are: 1 N = cXm, c > m 0 2. e is even. 3. With the mutual value, 'take the Prime Factor method, and vice versa. 4. If the Common Factor algorithm is used, it is necessary to satisfy w 2 121 'how this condition is known' will be explained later. 5. The first stage of pipeline is responsible for c-point DFT conversion, and the second level is responsible for η»point conversion. 6. The problem of the twiddle factor for the Common Factor method is solved at the second level of the line 34 201227351. The hardware action is described as follows: After the reset, the first stage hardware will simultaneously calculate the DFT conversion of h = 〇C/2 at the beginning, which is responsible for the RDFT circuit and the accumulation circuit architecture of Figure 6, respectively. After the completion of the operation, the accumulating circuit will be disabled (Disable). At that time, only the RDFT circuit will be left, and the subsequent operations will be =1, 2, ..., with 2-1 conversion, the circuit will also produce

Fc2 = C'1, C'2...C/2 + 1 DFT coefficient, for each increment of h value, the circuit will idle two cycles to generate the next coefficient value' so a single Mi conversion for ^ level ((C+1)Xm) + 2 cycles, since there are μ conversions, 总VXc + A/ + 2c)/2 cycles are always required. The second stage contains two sets of RDF Ding circuits, one set is responsible for the front-level h = CU...c/2-1 conversion result, fc2 = C/2 cl, c- 2...c/2 + l conversion result, so this The level hardware action will have different actions and the other group will be responsible for 'by adopting the hybrid architecture. The way: 1. Take the Prime Factor method. The hardware action mode of this method is roughly the same as that of the first-level rdf circuit, so it can be based on The previous stage evaluation method knows that the single 4-value conversion requires (W + 1+2) cycles, and the total demand cycle for completing all Mi conversions is (state + 2) _/2 b 2, because the last-pen value conversion is not required. Then calculate the next coefficient, so deduct 2 cycles. ^ 2· Take the Common Factor method because the data transfer between the level and the level needs to be multiplied by the rotation factor, because the first-level completion of the single-bu value conversion needs ((e+1)x, deduct a cycle, compared to the second 35 The 201227351 level is required to complete the operation (Μι + 1+2) χ(ηι/2)_2 about twice the period, and the factor operation needs to add a period, of which 2 periods are the f-process used by the processing factor. The two cycles are the difference of the data multiplication factor used to process the transfer. It can handle the twiddle factor by this extra cycle. At this time, the value corresponds to the relation of formula (33): ((C+l) Xn〇+ 2>(ni + 1 + 2)x(m/2K2 + 4m. (1)) Assume that the pipeline is at the optimum efficiency (the worst case for inequality under this condition), ie c=m. 33) The formula can be obtained as: (c, s) = (8, 8) OT · (1,1) 0 Under this condition, the hardware action is planned to take 4m cycles to deal with the twiddle factor problem. Continued operation „, the bribe conversion, where the rdft hardware action is roughly similar to the first level, because there is no next level of consideration, so no simple accumulator circuit is used to be responsible for the m/2 The total demand cycle is 4, one...2)X((...)/2)_2, and the required period of the second level is increased by 〇n + 3) cycles, so the inequality in equation (33) needs to be modified to: (c+ 1) xm) + 2 > (m + 1 + 2) X (m/2) + i + 5n> (34) Similarly, by formulating (34), the cw value is: (c, m) ^ (11,11) or (0,0) From the results of 〇_ and , it can be seen that when the Comm〇n Fact〇r method is adopted, the specification points must meet the conditions of N 2 U1. 'It is possible to sort out the calculation weeks required to complete the conversion by using the Di 6 Factor method and the Common Factor method respectively. The 201227351 period is due to the pipelined relationship, and the time will overlap, so the resulting formula (WXc + W+2c)/ 2+(m+3)X 卜1-21-2. (35) (/VX c + A/ + 2c)/2 + (τη + 3) X (τη/2) + 5m + 1. ( 3 ό )

When the DFT conversion specification point is N, if the method is performed by G. Goertze丨 in American based simulation, ρρ· 34-35, 1958, "An algorithm for the evaluation of finite trigonometric series" For conversion, the calculation cycle demand is A/x〇V + i). The paper published by Van et al. in IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E SERIES A, vol. 90, p. 1644, 2007"VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT The method proposed in /IDFT Design" is converted. When the input data has been processed, the calculation cycle demand is f/2. For the architecture proposed by the present invention, the calculation cycle demand is as in formula (37) and formula. (38), where ruler =, and if c · m is a prime, use equation (37) to calculate the required period, otherwise use equation (38) to calculate. (/VX c -f- A/ + 2c )/2 + (m -r 3) X [rn/2l - 2〇(37) (Λ/ X c + A/ + 2c)/2 -f (m -f 3) X (rn/2) + 5m + 1. (3 8) The comparison object is in addition to the above two documents, and the literature published by Van et al. in 2004 and the literature related to this paper by Lei et al. in recent years are included in the comparison object. Comparing the data, here is mainly 37 201227351 for the DRM application required specification points to compare, because the points have two The power square points and non-two power power points are compared as shown in Table 4. Among them, [1] is the paper published by American G. Goertzel in American alvid monthly, pp. 34-35, 1958. An algorithm for the evaluation of finite trigonometric series"' [2] is a paper published by L. VAN and C. YANG in 2004, pp. 357-360 "High-speed area-efficient recursive DFT/IDFT architectures", [3] is a paper published by Van et al. in IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E SERIES A, vol. 90, p. 1644, 2007 "VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design", [4] is a paper published by L. Shin-Chi, et al in Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 56, pp. 921-925, 2009 "Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms", [5] is S.-C. Lai, et al. in Circuits and Systems II: Express B Riefs, IEEE Transactions on, pp. 1-5, 2010 Published paper "Low-Computation cycle,

Power-Efficient, and Reconfigurable Design of Recursive DFT for Portable Digital Radio Mondiale Receiver. Table 4 Period Comparison Box Size for DRM Specification Points (Frame Size, N) N 288 256 176 112 m N(N+1) 83,232 65,729 31,152 12,656 38 201227351 m Ν2 82,944 65,536 30,976 ^_12,544 PI Ν2/2 41,472 32,768 15,488 6,272 [4].. (Ν/2-1ΧΝ+1) 41,327 32,639 15,399 6,215 [5] 1 (A), (Β) 9,594 32,896 3,124 —1,960 The present invention (C), (D) 4,842 2,425 1,594 1,006 #5 Periodic improvement rate cycle improvement rate compared with other documents (Ratio for Various Frame SizeN) 288 256 176 112 [1] 17.19 27.10 19.54 12.58 — [21 17.13 27.03 19.43 12.47 m 8.57 13.51 9.72 6.23 [41 8.54 13.46 9.66 6.18 ~~ _ [51 1.98 13.57 1.96 1.95 The invention 1 1 1 1

The cycle improvement rate can be further calculated by the results of Table 4, as shown in Table 5. According to Table 5, it is apparent that the overall efficiency of the architecture proposed by the present invention is at least 1.95 times better than other literatures. Based on the above description, assume that the input frame length Ν is a multiple of 8,

Reprinted by C. Hwang-Cheng and L. Jie-Cherng in Signal Processing Letters, IEEE, ν〇1·3, ρρ· 1 16-1 18, 1996"Regressive implementations for the forward and inverse MDCT in MPEG audio coding", the calculation cycle demand is Λ'-/2. If c. Che-Hong, et al. in Circuits and Systems II: Analog and Digital Signal Processing, IEEE

50, pp. 38-45, 2003, "Recursive architectures for realizing modified discrete cosine transform and its inverse", without pre- and post-processing 39 201227351, the calculation cycle demand is W2/16. If s. F. Lei, et al. in Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. PP, pp. 1 - 5, 2010 published paper "Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms", the calculation cycle demand is 2/32, but in order to reduce the cost of hardware implementation, the concept of multiplier sharing is also used, so the number of calculation cycles is increased by w/4, total The calculation period becomes 〇V/8 + l) 〇V/4). Compared with the architecture of the present invention, if the number of conversion points W is changed by the pre- and post-processing procedures, the IMDCT conversion can be changed to The W/4 DFT is the core architecture conversion, and the core conversion required period can be modified by the formula (37), as shown in the following equation. (W'Xc' + AT+2〇/2+(w'+3) X [ni'/2l-2 , (39) where Λ/ = 4Λ/, Λ/ = X τη 〇

Similarly, [6] is a paper published by C. Hwang-Cheng and L. Jie-Cherng in Signal Processing Letters, IEEE, vol. 3, pp. 1 16-1 18, 1996 "Regressive implementations for the Forward and inverse MDCT in MPEG audio coding". [7] Department C. Che-Hong, et al. in Circuits and Systems II: Analog and Digital Signal Processing, IEEE

Transactions on vol. 50, pp. 38-45, 2003 "Recursive architectures for realizing modified discrete cosine transform and its inverse" 0 [8] is S. Lai, et al. in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, pp. 793-797, 2009"Common architecture 201227351

Design of novel recursive MDCT and IMDCT algorithms for application to AAC, AAC in DRM, and MP3 codecs'. [9] SF Lei, et al. in Circuits and Systems Π: Express Briefs, IEEE Transactions on, vol. PP, pp. 571-575, 2010 Published papers "Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms". The comparison data is mainly for DRM applications. Its application includes 1920 points and 240 points of AAC format compression. For the formula (39), the value of βίη' can be obtained from Table 5.2.1. The comparison results are shown in Table 6. Show.

^ 6 Recursive cycle comparison and improvement rate frame size (Frame Size, Ν') 1920 1920 Ratio 240 Ratio 6 Ν2/2 1,843,200 227.72 28,800 67 92 [71 [8] Wne (Ν/2+1ΧΝ/4Ί 230,400 461,280~ 28.47 3,600 8.49 56.99 7,260 17 12 -1^1_ The present invention (Ν/8+1)(Ν/4, (A) 115,680-8,094~~ 14.29 Ϊ 1,860 ~424~~ 4.39 i Table 6 comparison results, mainly for the core Partly to discuss, the reason is that in order to obtain an accurate number of cycles, the former 'post-processing part ignores the architecture proposed by the present invention, and has a lesser period of time, and the improvement rate is at least 4 39 times or more. ::= is the use of memory components to survive the previously calculated good system has ... ring - two use 'However, memory components for the wafer to achieve surface energy indicators, because (four) number of demand can be assessed by the type of hard body efficiency coefficient Can be evaluated by the transfer function of each method

41 201227351 For different transfer functions it is possible to have both Cosine and Sine coefficients or only a single factor. The evaluation results are shown in Table 7. Table 7 FFT Coefficients for DRM Specification Points Box Size (Ν) Total Number of Blocks (Total words) 288 288 256 176 112 m 2Ν 576 512 352 224 1,664 Γ21 2Ν 576 512 352 224 1,664 [31 2Ν 576 512 352 224 1,664 f41 Ν-2 286 254 174 110 824 ί51 2c+2m 82 512 54 46 694 The invention does not require the use of memory 0. In the IMDCT conversion section, the coefficient evaluation method can take the transfer function evaluation method with DFT. It can be viewed directly by viewing the block diagram of the architecture. The benefit of this approach is more intuitive and easy to find which coefficients can be shared to reduce errors in evaluation. The evaluation results are shown in Table 8. Table 8 Coefficient requirements for various IMDCT methods and Pre-and Post-processing Recursive kernel Total words Ratio (Ratio) Ν 1920 240 N 1920 240 Γ61 0 0 0 2N 3,840 480 4,080 3.78 m Ν 1920 240 3N/4 1,440 180 3,780 3.5 m 0 0 0 3N/4 1,440 180 1,620 1.5 Γ9] 3Ν/4 1440 180 N/2 960 120 2,700 2.5 Invention Ν/2 960 120 0 0 0 1,080 1 From the comparison results of Table 7 and Table 8, it can be seen that the proposed architecture of the present invention has the minimum requirement for the coefficient 42 201227351: whether it is in DFT conversion or applied to IMDCT conversion, which is indirect. This shows that this architecture can have a small area requirement in the wafer to achieve low cost benefits. In addition to the influence of the hidden components on the chip area, the hardware requirements of the architecture are also considered as one of the factors. The evaluation results further further calculate the computational complexity of the various methods. Since complexity is based on the results of hardware evaluations, hardware evaluation will be a top priority. The evaluation results are shown in Table 9. Where '[called

K. Dong-Sun, et al_ at Consumer Electronics, IEEE

Transact 丨ons on, vo 丨.54, pp 159〇丨594, 2〇〇8 published papers "Design of a mixed prime factor FFT for portable digital radio mondiale receiver" c Table 9 Hardware resources of various RDFT methods Adder multiplier Coeff.-ROM DTPT 101 30 30 un-listed un-listed Π 8 6 1,664 1 Ϊ 2 8 4 1,664 1 [31 12 6 1 1,664 1 [41 13 2 824 2 f51 8 4 694 1 invention 14 6 0 4 With the results of Table 9, the computational complexity can be further evaluated. The evaluation results are shown in Table 10 and Table 11. Table lj__^ The computational complexity analysis frame size of the RDFT architecture (Frame Size, N) N 288 256 176 1 112 Real addition (A)'(B) 26,270 19,198 11,118 6,190 Real multiplication (C)'(D)1 13,276 11,260 5,644 3,148 43 S; 201227351 Calculation of 256 points: (eight) 2#(〇+讲+ 5.5) —2 (C)A^ + m+12)—4 Others: (B) 2A/(c + 2_5) + 4(A/ + c)[?n/2l - 2 (D) N(c +3) + 2(W + c)im/2l - 4 Table 11 Computational complexity analysis (specification points) of various RDFT methods Real Addition Real Multiplication [10] Not listed 5,928 Not listed 1,000 m 4N(N+2) 334,080 2N(N+3) 167,616 2121 4N(N+1) 332,928 2N(N+1) 166,464 m 2N(2N+3) 333,504 2N(N+3) 167,616 f41 N(2N+7)-2 167,902 (N+1KN-2) 82,654 [51 4N(m+c+2) 49,536 2N(m+c+2) 24,768 The present invention (A 26,270 (B) 13,276 (A) 2iV(c + 2.5) + 4(Λ/ + c)im/2l - 2 (B) A'(c + 3) + 2 (Λ/ + c)fm/2] - 4 It can be seen from Table 1 that for the recursive architecture, the addition complexity is at least 1.89 times improvement rate, the maximum improvement rate is 12.72 times, and the multiplication complexity is at least 1.87 times improvement rate. The maximum improvement rate can reach 12. 63 times. In the IMDCT section, the method architecture of ChiangandLi in [6] consists of three real adders and two real multipliers. The method of Chen et al. in [7] contains 7 real adders and 4 real multipliers without pre- and post-processing. In [9], the method architecture of Lei et al. includes six real adders and two real multipliers without pre- and post-processing. The present invention implements IMDCT based on DFT, if not included. In the case of post-processing, the hardware requirements are 14 real adders and 6 real multipliers. The complete hardware comparison results are shown in Table 12. Table 12 Hardware resources for various IMDCT methods 44 201227351

Algorithm Adder Multipier Coeff.-ROM DTPT [61 3 2 4,080 1 Γ71 7 4 3,780 4 ί81 11 2 1,620 4 ί91 6 2 2,700 4 The present invention 14 6 1,080 4

The computational complexity of the various IMDCT methods is then evaluated by the results of Table 12, which will be evaluated in the same manner as the previous assessment. The results of the computational complexity assessment for all algorithms are shown in Table 13 and Table 14. Table 13 RDFT-based IMDCT architecture computational complexity analysis box size pre-processing, post-processing (Pre- and recursive (Frame Post-processing) kernel) Size, N) real addition real multiplication real number addition real multiplication NN 2N (A) (B) 1920 1,920 3,840 49,502 24,988 240 240 480 2,602 1,328 (A) 2W(c + 2.5) + 4(W -l- c)f«i/2l - 2 (B) W(c + 3 + 2(Λ» + c)fm/2l - 4 Table 1 4 Computational complexity analysis of various IMDCT methods (specification number _____ number) _ pre-processing, post-processing (Pre- and recursive core-processing (Recursive Post-processing) Kernel addition real multiplication real multiplication real multiplication ί61 0 0 5,529,600 1,845,120 m 960 1920 923,040 461,760 『81 0 0 4,608,000 922,560 ί91 3,358 1,440 691,200 231,360 The present invention 1,920 3,840 49,502 24,988 As can be seen from Table 14, there is at least additive complexity 13.5 1x change 45 201227351 Good rate, the maximum improvement rate can reach 107.53 times, at least 8.08 times improvement rate in multiplication complexity, the maximum improvement rate can reach 64 times. Based on the introduction, derivation, and hardware planning and improvement of the previous chapters, through this series of discussions, the RDFT architecture circuit was developed and synthesized by Synopsys' Design compiler Tool, and then completed by Cadence's SoC Encounter Tool. APR (Auto Placement and Route, APR), this RDFT architecture circuit chip is implemented, and its wafer data is shown in Table 15. Table 1 5 Chip Data Support Box Large DFT/IDFT 288/256/ 176/ 112 Small (Supporting Frame Size, MDCT/IMDCT 1920/240 _N)___ Internal Digital Number Length (Internal / Coeff. Word Length) 24 bit / 24 Bit Process Technology TSMC 0.18um 1P6M CMOS Package (Package) CQFP128 Supply Voltage 1.98v Power consumption 14.6mW @ 25MHz Core Size 0.84x0.84 mm2 Where Wafer Power Consumption The simulation result measured by Prime Power in the case where the RDFT specification point is set to w = 288 and the operating frequency is 25Mhz. Compare this data result with the results of other papers. The result is formula (40), which will be normalized by formula (40) to eliminate the process factors, and then calculated by formula (4 1) to obtain an objective performance index of 201227351. The comparison results are shown in Table 16. Show. Area Normalized Area =- Technology/0.18Hni , (40) DFTs Technology/Ο.ΐδμιη Energy Power X Execution Time X 103 o (41)

Table 1 6 wafer comparison Design Van et al. m Previous-I i41 Previous-II m Process Technology 0.13 um 0.18 um 0.18 um 0.18 um Internal Digital Length (Internal / Coeff. Word Length) 12 bit / — 24 bit / 24 bit 21 bit / 16 bit 24 bit / 24 bit Supply Voltage 1.2v 1.98v 1.98v 1.98v Timing (Clock Rate) 20 MHz 25MHz 25MHz 25MHz Support Frame Size (N) ) 212, 106 288, 256, 176, 112, 212, 165, 106 288, 256, 176, 112 480, 288, 256, 176, 112, 60 288 execution time 2.07 ms* (estimation) 1.65 ms (estimation) 384ps (estimation) 193.68ys (estimation) Power consumption 1.25 mW for DTMF 5.98 mW 8.44 mW 14.6 mW Core area 0.182 mm2 0.154 mm2 0.265 mm2 0.705 mm2 Normalized Area 0.348 mm2 0.154 mm2 0.265 mm2 0.705 mm2 Normalized DFTs/Energy 279.12 101.45 308.55 353.64 47 201227351 From the foregoing comparison, the modified discrete cosine forward rotation with discrete Fourier transform as the core of the present invention is known. The system of switching and reverse conversion can realize RDFT with low area, low complexity and high efficiency. It can be known from the previous comparison results. For the 288 point, the technology of the present invention and the latest Lai et ai, RDFT architecture [5 ] Comparison, the improvement rate is reduced by 49.5 ° / in terms of the calculation cycle. In addition, the addition operation saves 47 5% in terms of computational complexity and 48.7% in multiplication operation. In addition, it has an energy-saving, reusable and configurable green energy design concept that can be easily used for DFT conversion of any specification point, while also playing the core of MDCT7IMDCT, achieving RDFT goodness. Plus is reused to increase usage. As apparent from the above, the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It is to be noted that the various embodiments described above are intended to be illustrative only, and the scope of the invention is intended to be limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a system for modifying discrete discrete cosine transforms and inverse transforms with discrete Fourier transform as the core of the present invention. 2 is a schematic diagram of the N/4 point discrete Fourier transform unit of the present invention. FIG. 3 is a schematic diagram of a conventional modified RDFT architecture. FIG. 4 is a block diagram of the improved architecture of the shared secret device of FIG. 3. Figure 5 is a schematic diagram of the shared multiplier of Figure 4. Figure 6 is a schematic illustration of the accumulation circuit of the present invention. 48 201227351 Figure 7 is a schematic diagram of the RDFT hardware calculation results using the multiplexer of the present invention. Figure 8 is a schematic illustration of the order of demand for the twiddle factors of the present invention to have two different coefficients at the same time. Figure 9 is a schematic illustration of the (10) coefficient sharing multiplier of the present invention. [Main component symbol description]

Modified Discrete Cosine Positive Conversion System 11〇G Positive Discrete Cosine Inverse Conversion System 1 2 0 Data Sequence Shift Scheduling Single ^ i 3Q Data Reorder Unit (10) First Rotary Operation Unit 15〇N'4 Points Discrete Fourier Conversion unit 160

First-rotation operation unit 170 first-multiplexer 205 first multiplier 2 1 5 second multiplexer 225 second multiplier 235 third multiplier 245 second adder 255 de-interleave operation unit 180 first adder 2 1 0 first shift register 220 first-delay 230 third multiplexer 240 fourth multiplexer 250 second delay 260 49

Claims (1)

201227351 VII Patent Application Scope A modified discrete cosine forward conversion system with discrete Fourier transform as the core, comprising: a continuation shifting sequence shifting arrangement unit, which receives N input digits and a gas number 'for the N digits The signal execution sequence shifting arrangement, the first temporary signal, ", is a positive integer of a multiple of 4; a ... data reordering unit, connected to the (four) sequential shifting arrangement early 'execution data for the first temporary signal Reordering the operation to generate N/4 second temporary signals; a truncation operation unit connected to the data reordering unit 执行 performing a first rotation operation on the N/4 second temporary signals to generate Ν/4 a third temporary signal; — a 傅/4 point discrete Fourier transform unit connected to the first rotating operation unit, performing discrete Fourier transform on the Ν/4 third temporary signals to generate Ν/4 fourth temporary The signal, the discrete Fourier transform unit of the point includes: a first multiplexer for receiving the Ν/4 third temporary signals and a second multiplication signal, and generating a first multi a first adder connected to the first multiplexer to add a difference between the first multiplex signal and the second delay signal to generate the fourth temporary signal; the first multiplier is connected Up to the first adder, multiplying the fourth temporary signal by a cosine function signal to generate a first multiplication signal; 50 201227351 - the first shift register is connected to the first multiplier Performing a shift operation on the first multiplication signal to generate a first shift signal; a second multiplexer connected to the first multiplier and the first shift register to receive the first a multiplication signal and the first-shift signal' to output a second multiplexer signal; a delayer connected to the first adder to "Hai fourth temporary signal to perform a delay operation to generate a first delay signal; a second multiplier connected to the first delay device for multiplying the first delay signal and a sinusoidal function signal' The second multiplication signal is generated, and the first delay device and the first multiplication signal are received, and the first delay signal and the second multiplication signal are received to output a third multiplexer Signal a second multiplier 'connected to the third multiplexer to multiply the S-second second multiplexer signal and _丨 to generate a third multiply signal; a fourth multiplexer connected to the first a second multiplexer receiving the second multiplexer signal and the second delay signal to be a fourth multiplexer signal; a second adder connected to the third multiplier and the fourth multiplexer to Adding the third multiplication signal and the fourth multi-two signal to generate a second addition signal; ^ and 5! 201227351 a second delayer 'connected to the second adder to the second The addition signal performs a delay operation to generate the second delay signal; the second rotation operation unit is connected to the discrete Fourier transform unit of the N/4 points, and the N/4 is the fourth temporary signal and the second The addition signal is configured to perform a second rotation operation to generate N/4 fifth temporary signals; and a de-interleave operation unit connected to the second rotation, the operation unit 'the fifth temporary for the NM Signal execution _ deinterlace operation 'to generate N Output signal.修正 范围 范围 范围 第 第 范围 范围 其中 η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η η (η+ιή fn-^) XN 71 ^--1 4 NJ ~ 1 ping is the N first temporary, x (n) is the N input digital signal signal. 3. As in the system of the modified discrete cosine transform which is based on the second part of the patent application, the Fourier transform new sorting unit is represented by the following formula: , wherein the data is χ η — (^(2n) — ;v(/V — 2n — ι)\ :(n \ ))+!H "2 calls, in the field signal, for the N/4 second temporary signals, the temporary signal number; for the N 52 201227351 4. The system of modified discrete cosine forward conversion with discrete Fourier transform as the core according to claim 3, wherein the first rotating operation unit is Ν/4 second temporary signals; ^ The first rotation performed is expressed by the following formula: exp(—i .2π Ν (4)), where ' ί is an indicator from 〇 to Ν /4-1. 5. The system of modified discrete cosine forward conversion with discrete Fourier transform as a core according to claim 4, wherein the second rotation operation unit performs a second rotation on the fourth/four fourth temporary signals. The operation is expressed by the following formula: exp —1ύ0Ί is an indicator from ο to ν/4-1. 6. The system of modified discrete cosine forward conversion with discrete Fourier transform as a core according to claim 5, wherein the de-mter 丨 eave unit performs the fifth temporary signal The deinterleaving performed is expressed by the following formula: X( 2k) = Re( X(k)) X(2k + l) = -lm (again (A - h", k = 〇 4 4 , plus) The NM fifth temporary signal, the state is the N rounds of signals. 7. A modified discrete cosine inverse transform system with discrete Fourier transform as the core, which includes: ' 53 201227351 Yes, its (4) 2 Transmitting a digit signal, performing a data reordering operation on the N/2 input digit signals to generate a positive integer of a multiple of the sixth temporary signal 'deleted'; a red transport different unit, connected to the data to reorder Single _ a sixth temporary signal to perform a --rotation operation to generate N / 4 seventh temporary signals; (d) 离散 to transfer two or four points of discrete Fourier transform unit, connected to the first-rotation = transport 4 1 Perform discrete Fourier transform on the N/4 "temporary signals" N/4 eighth 轫h±% ports are temporarily occupied, and the Ν/4 points discrete Fourier transform unit includes: a first multiplexer for receiving the seventh temporary signal and: a second multiplication signal and generating a first multiplex signal; ^ a first-adder coupled to the first multiplexer to add a first multiplex signal and a second delay signal to generate the An eighth temporary signal; a first multiplier coupled to the first adder for multiplying the first temporary signal and the cosine function signal to generate a first multiplication signal; a first shift a register connected to the first multiplier to perform a shift operation on the first multiplying signal to generate a first shift signal; a second multiplexer connected to the first multiplier and the first - shifting the register, receiving the first multiplying signal and the first shifting signal ' to output a second multiplexer signal; 54 201227351 a first delay, connected to the first adder to The eighth temporary signal is delayed, no 'earth-di a delay signal; a second multiplier coupled to the first delay device to multiply the first delay signal and a sinusoidal function signal to generate the second multiplication signal; a second multiplexer connected to the first delay device and the second multiplier, receiving the first delay signal and the second multiplication signal to output a third multiplexer signal; a third multiplication And connecting to the third multiplexer to multiply the third multiplexer signal and _丨 to generate a third multiplication signal; a fourth multiplexer connected to the second multiplexer Receiving the second multiplexer signal and the second delay signal to output a fourth multiplexer signal; a second adder connected to the third multiplier and the fourth multiplexer to The third multiplication signal is added to the fourth multiplexer signal to generate a second addition signal; and a second delay is connected to the second adder to delay the second addition signal to Generating the second delay signal; a second rotation operation unit connected to the N/4 points of the discrete Fourier transform unit 7L, and the N/4 is composed of the eighth temporary signal and the second addition signal 55 201227351 - Second rotation operation to generate _ ninth The temporary signal; and the μ deinterleave operation unit are connected to the second rotation operation unit, and perform a deinterleaving operation on the N/4 ninth temporary signals to generate N output signals. 8. A system for modifying a discrete cosine inverse transform having a discrete Fourier transform as a core, as recited in claim 7, wherein the data reordering unit is represented by the following formula: Xw=X{2k) + iX{N/2-2k-l), in the standby, X is the N/4 sixth temporary signal, and the N/2 input digital signals are illusory. 9. The system of modified discrete cosine inverse conversion with discrete Fourier transform as a core according to claim 8, wherein the first rotating operation unit performs the first for the N/4 sixth temporary signals. The rotation operation is represented by the following formula: ..2π . 1 .. exp(-ι——(t + —)) ' y N 8 Where / is an indicator from 0 to N/4-1. 1 . The system of modified discrete cosine inverse conversion with discrete Fourier transform as a core according to claim 9 , wherein the first rotating operation unit performs the N/4 eighth temporary signals The second rotation operation is expressed by the following formula: Where (- and (1, + ^)) ', among them, an indicator from 0 to N/4-1. 56 201227351 11. The system of modified discrete cosine inverse conversion with discrete Fourier transform as core according to claim 10, wherein the deinterleave operation unit is opposite to the NM ninth temporary signals The deinterleaving performed is expressed by the following formula: · x(2n) = (i (g + «)) ; c(2n + 1) = —·ίηι (ί (^ _ 1 — η)) X λ· (7 + 2η + 1) = ("-1 - η))X(h2n)^Im(i{^ + n))伶+2^1) = -/?+(备—1-„) ) 2η^ = —J?e(r(n)} η = 〇* Λ1 * —— 8 ·γ (τ+2η +1)= ΐΊη (τ _ 1 ~η)) where '玎 is the first Nine temporary signals, w Α ~ Ma should have an output signal. Eight, schema (see next page): 57