CN101277283B - Fast Fourier Transform Butterfly Device - Google Patents

Abstract

The invention belongs to the technical field of communication, and particularly relates to an efficient implementation method for a fast Fourier transform butterfly unit. The operation of one branch of the butterfly unit is completed by adopting two real number multipliers and three/five real number adders in two periods through the known rotation factor in the butterfly unit and the design idea of a pipeline structure. The method comprises the following steps: 1) a real number adder unit 701 that completes addition of input data; 2) a real multiplier unit 702 that multiplies the addition result by the twiddle factor; 3) and a real number adder and delay control unit 703 for performing addition, delay and control operations on the data obtained by the unit 702. The method can be widely applied to the realization of fast Fourier transform.

Description

The fast Flourier transformation butterfly type device

Technical field

The invention belongs to communication technical field, particularly a kind of fast Flourier transformation butterfly type device.

Background technology

Fast fourier transform is a kind of way of realization rapidly and efficiently of Fourier transform, and is widely used in the various systems, as OFDM (OFDM) system, radar system, input and estimating system etc.This technology has made full use of the periodicity and the symmetry of Fourier transform twiddle factor, thereby has significantly reduced the computation complexity of Fourier transform and realized cost, therefore gets more and more people's extensive concerning.

For a long time, people have carried out extensive and deep research to fast fourier transform, mainly concentrate on algorithm and the architecture design.Butterfly type unit, as the engine of fast fourier transform, its design is the resource and the speed of decision fast Fourier transform unit directly, this shows it is considerable.Therefore how how the realization butterfly type unit of high-efficiency compact improves calculation process speed under the prerequisite of utilizing resource less, then becomes a very significant thing.

Summary of the invention

The object of the present invention is to provide a kind of butterfly type unit of fast fourier transform.Fast Fourier transform unit provided by the invention can be widely used in various needs and carry out in the system of Fourier transform.

For achieving the above object, fast Flourier transformation butterfly type device provided by the invention, it comprises:

A) real number adder unit is used for the data addition with input, and the number of basic 2 o'clock adders is one, and the number of basic 4 o'clock adders is three, and addition result is given to the real multipliers unit;

B) real multipliers unit, the result and the twiddle factor that are used for the real number adder unit is sent here multiply each other, and the result is delivered to real add musical instruments used in a Buddhist or Taoist mass and delay control unit;

C) real add musical instruments used in a Buddhist or Taoist mass and delay control unit are used for the result that the real multipliers unit obtains is postponed addition, obtain operation result; Wherein:

The real number adder unit will be sent into the data of butterfly type unit and divide the order addition respectively of real imaginary part, G _r, G _iData are real in order to import, the result of imaginary part addition, and N is the number of input data, I _Nr, I _NiReal, imaginary part for the input data;

$G_r=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{nr}}$ Formula 1

$G_i=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{ni}}$ Formula 2

The result that the real number adder unit is delivered in the real multipliers unit respectively with real, the imaginary part R of twiddle factor _r, R _iMultiply each other and obtain H _Rr, H _Ri, H _IrAnd H _Ii

H _Rr=G _rR _rFormula 3

H _Ri=G _rR _iFormula 4

H _Ir=G _iR _rFormula 5

H _Ii=G _iR _iFormula 6

Real add musical instruments used in a Buddhist or Taoist mass and delay control unit are finished the delay control addition of the real multipliers unit being delivered to data, the RB as a result that obtains expecting in two cycles _r, RB _i:

RB _r=H _Rr-H _IiFormula 7

RB _i=H _Ri+ H _IrFormula 8

RB=RB _r+ jRB _iFormula 9

Wherein, RB is branch's result of calculation,

Whole process needs 2 cycles to finish altogether, owing to adopted the mode of 4 grades of flowing water, therefore needs the delay in 4 cycles.

Described fast Flourier transformation butterfly type device, wherein, the real number adder unit will deliver to butterfly type unit data real part or imaginary part is carried out addition.

The inventive method can be in two cycles, only need under the prerequisite of two real multipliers and three/five real add musical instruments used in a Buddhist or Taoist mass, finish branch's computing of base 2 or basic 4 fast Flourier transformation butterfly type devices, owing to adopted the The pipeline design structure thought, therefore the hardware of designing has the sequential compactness, the resource utilization height, advantage such as speed is fast, and have application scenario widely.

Description of drawings

For further specifying technical characterictic of the present invention, below in conjunction with embodiment and accompanying drawing the present invention is done a detailed description, wherein:

Fig. 1 is the frame structure schematic diagram of fast Fourier transform unit.

Fig. 2 is the structural representation of frequency domain base 4 fast Flourier transformation butterfly type devices.

Fig. 3 is the hardware implementation structure schematic diagram of frequency domain base 4 butterfly type units one branch.

Embodiment

The efficient implementation method that is used for the fast Flourier transformation butterfly type device of the present invention can utilized under the prerequisite of resource as far as possible less, realizes the high usage of resource and the speed of raising system by streamline.The total plurality of units once of this implementation method, comprising:

Make full use of the design philosophy of the known and pipeline organization of twiddle factor, proposed a kind of efficient, the hardware implementation method of simple fast Flourier transformation butterfly type device, method feature comprises:

1) the real number adder unit 701, are used for the data addition with input, and the number of basic 2 o'clock adders is one, and the number of basic 4 o'clock adders is three, and the result gives 702;

2) the real multipliers unit 702, and the result and the twiddle factor that are used for Unit 701 are sent here multiply each other, and the result is delivered to 703;

3) real add musical instruments used in a Buddhist or Taoist mass and delay control unit 703 are used for the result that Unit 702 obtain is postponed addition, obtain operation result;

See also Fig. 1, the frame structure schematic diagram of fast Fourier transform unit, comprising:

1) memory cell 101,102,103,104, are used for input, temporary and dateout.

2) get conjugate unit 201,202, complex data is got conjugation, finish the switching between FFT and IFFT.

3) MUX301,302 is used to cooperate and gets conjugate unit and finish switching between FFT and IFFT.

4) address-generation unit 400, are used to produce the needed address date of memory cell and twiddle factor unit.

5) the twiddle factor unit 500, are used to export the required twiddle factor of computing.

6) main control unit 600, are used to control the co-ordination of each unit, with memory cell, get conjugate unit, MUX, address-generation unit and butterfly type unit and all be related.

7) butterfly type unit 700, are used for finishing the work of treatment of each grade of fast fourier transform butterfly type unit.

See also Fig. 2, the structural representation of frequency domain base 4 fast Flourier transformation butterfly type devices, this figure is an example with the fast Flourier transformation butterfly type device that frequency domain base 4 extracts, provide butterfly type unit and form a basic schematic diagram of structure, owing to be that therefore base 4 comprises 4 branches in this unit, each bar branch is similarly except that the addition part is slightly had any different basically, and therefore the mode that all can adopt Fig. 3 to provide is realized.

See also Fig. 3, the hardware implementation structure schematic diagram of frequency domain base 4 butterfly type units one branch.Comprising:

1) the real number adder unit 701, divide the order addition respectively of real imaginary part, G with the data of sending into butterfly type unit _r, G _iData are real in order to import, the result of imaginary part addition, and N is the number of input data, I _Nr, I _NiReal, imaginary part for the input data;

$G_r=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{nr}}---\left(1\right)$

$G_i=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{ni}}---\left(2\right)$

2) the real multipliers unit 702, be used for result that Unit 701 are delivered to respectively with real, the imaginary part R of twiddle factor _r, R _iMultiply each other and obtain H _Rr, H _Ri, H _IrAnd H _Ii

H _rr＝G _r·R _r (3)

H _ri＝G _r·R _i (4)

H _ir＝G _i·R _r (5)

H _ii＝G _i·R _i (6)

3) real add musical instruments used in a Buddhist or Taoist mass and delay control unit 703 its role is to finish the delay control addition of Unit 702 being delivered to data, the RB as a result that obtains expecting in two cycles _r, RB _i:

RB _r＝H _rr-H _ii (7)

RB _i＝H _ri+H _ir (8)

$\mathrm{RB}=R{B}_r+\mathrm{jR}{B}_r,(j=\sqrt{-1})---\left(9\right)$

Wherein, RB is branch's result of calculation.Whole process needs 2 cycles to finish altogether, owing to adopted the mode of 4 grades of flowing water, therefore needs the delay in 4 cycles.

Claims (2)

1. fast Flourier transformation butterfly type device, it comprises:

A) real number adder unit is used for the data addition with input, and the number of basic 2 o'clock adders is one, and the number of basic 4 o'clock adders is three, and addition result is given to the real multipliers unit;

B) real multipliers unit, the result and the twiddle factor that are used for the real number adder unit is sent here multiply each other, and the result is delivered to real add musical instruments used in a Buddhist or Taoist mass and delay control unit; And

C) real add musical instruments used in a Buddhist or Taoist mass and delay control unit are used for the result that the real multipliers unit obtains is postponed addition, obtain operation result; Wherein:

The real number adder unit will be sent into the data of butterfly type unit and divide the order addition respectively of real imaginary part, G _r, G _iData are real in order to import, the result of imaginary part addition, and N is the number of input data, I _Nr, I _NiReal, imaginary part for the input data;

$G_r=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{nr}}$ Formula 1

$G_i=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{I}_{\mathrm{ni}}$ Formula 2

The result that the real number adder unit is delivered in the real multipliers unit respectively with real, the imaginary part R of twiddle factor _r, R _iMultiply each other and obtain H _Rr, H _Ri, H _IrAnd H _Ii

H _Rr=G _rR _rFormula 3

H _Ri=G _rR _iFormula 4

H _Ir=G _iR _rFormula 5

H _Ii=G _iR _iFormula 6

Real add musical instruments used in a Buddhist or Taoist mass and delay control unit are finished the delay control addition of the real multipliers unit being delivered to data, the RB as a result that obtains expecting in two cycles _r, RB _i:

RB _r=H _Rr-H _IiFormula 7

RB _i=H _Ri+ H _IrFormula 8

RB=RB _r+ jRB _iFormula 9

Wherein, RB is branch's result of calculation,

Whole process needs 2 cycles to finish altogether, owing to adopted the mode of 4 grades of flowing water, therefore needs the delay in 4 cycles.

2. fast Flourier transformation butterfly type device according to claim 1, wherein, the real number adder unit will deliver to butterfly type unit data real part or imaginary part is carried out addition.

Images