CN1335642A - Chip connecting method for chip assembly - Google Patents

Chip connecting method for chip assembly Download PDF

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Publication number
CN1335642A
CN1335642A CN00121465A CN00121465A CN1335642A CN 1335642 A CN1335642 A CN 1335642A CN 00121465 A CN00121465 A CN 00121465A CN 00121465 A CN00121465 A CN 00121465A CN 1335642 A CN1335642 A CN 1335642A
Authority
CN
China
Prior art keywords
wafer
substrate
chip
sub
female bearing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN00121465A
Other languages
Chinese (zh)
Inventor
谢文乐
庄永成
黄宁
陈慧萍
蒋华文
张衷铭
涂丰昌
黄富裕
张轩睿
胡嘉杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Semiconductor Electronics Ltd
Original Assignee
Orient Semiconductor Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orient Semiconductor Electronics Ltd filed Critical Orient Semiconductor Electronics Ltd
Priority to CN00121465A priority Critical patent/CN1335642A/en
Publication of CN1335642A publication Critical patent/CN1335642A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Packaging Frangible Articles (AREA)

Abstract

The chip connecting method for stacking two chips with the same size onto one identical substrate includes hot pressing of the lugs in the mother bearing chip with the substrate with metal solder lugs in the corresponding positions, adhering the other chip on the mother chip, connecting the other chip to substrate through metal wires, and packing the whole assembly comprising the substrate, mother bearing chip and the other chip.

Description

The chip connection method of crystal covered package
The application mode of semiconductor wafer is very diversified, modular trend is then arranged in recent years, the design of some wafer needs and another wafer operates do hand-in-glove, if its long mistake of payment to a porter distance each other far then can have influence on its operational effectiveness, then the mode that can select to pile up (stack) with two plates this moment encapsulates, and makes the distance energy of its pin interdigit close; And traditional unidimensional wafer stacking practice is that a parent crystal sheet is attached to earlier in the substrate (Substrate) and with metal wire routing mode and substrate conducting at present, heap sticks a sub-wafer on parent crystal sheet end face again, and also connect substrate in metal wire routing mode, at last with the rubber polymer overall package.
Conventional practice according to this, because this two wafer all adopts and pastes wafer and the routing mode engages substrate, oneself occupies one section no small areal extent the shared metal molding position of its parent crystal sheet, area shared when the wafer of adding the second layer is connected with substrate needs broader (need avoid the metal wire of parent crystal sheet), and the area that causes overall package to get up greatly expands.
Wafer owing to two routings piles up each other in addition, when sub-wafer is attached on the parent crystal sheet, the conventional package mode needs to make whole package thickness also greatly increase, so can't be used on the equipment of paying attention to its thickness size can be attached on the parent crystal sheet after the height of line on its parent crystal sheet of elargol bed hedgehopping.
The objective of the invention is to propose a kind of wafer joint of crystal covered package, can be with the first female bearing wafer of fitting of the Flip Chip of this female case in substrate, engaging the sub-wafer that is attached on the parent crystal sheet in the routing mode again makes with substrate and is electrically connected, this structure dress mode does not need routing because of female bearing wafer, can fit tightly with sub-wafer, and can make that the metal wire institute cloth area of sub-wafer is dwindled, help the volume that dwindles overall package.
The object of the present invention is achieved like this: a kind of chip connection method of crystal covered package, it mainly is at the wafer that piles up two same sizes during in same substrate, earlier projection on female bearing wafer and the substrate that is manufactured with the brazing metal projection in advance at the relative position place are added hot pressing, sticker one sub-wafer above female bearing wafer then, this sub-wafer adopts routing mode with sub-wafer of metal wire conducting and substrate, and the whole group of encapsulation is by substrate, module that female bearing wafer and sub-wafer constituted.
Use the chip connection method of crystal covered package provided by the invention, its packaged type can effectively dwindle overall package thickness, and can save the used routing processing procedure of female bearing wafer in the prior art, promotes to make usefulness.
Further describe the present invention below in conjunction with accompanying drawing:
Fig. 1 is a stacked structure cutaway view of commonly using skill.
Fig. 2 a to Fig. 2 e is a stacked structure processing procedure cross-sectional schematic of the present invention.
See also shown in Figure 1, at present traditional unidimensional wafer stacking practice is to be attached to a parent crystal sheet 11 in the substrate (Substrate) 12 earlier and with metal wire 14 routing modes and substrate 12 conductings, heap sticks a sub-wafer 13 on parent crystal sheet 11 end faces again, and also connect substrate 12 in metal wire 15 routing modes, at last with rubber polymer 16 overall package.
See also shown in Fig. 2 a to 2e figure, be stacked structure processing flow cutaway view of the present invention.
The present invention is that a kind of wafer of crystal covered package engages, and mainly is provided with the parent crystal sheet 21 of engagement protrusion, glutinous brilliant glue 28, is formed with unidimensional sub-wafer 23, metal wire 24 and the rubber polymer 26 of parent crystal sheet 21 by substrate 22, filler 27, surface:
A, at first female bearing wafer 21 is engaged with the Flip Chip of substrate 22 with female case;
A1: go up filler (underfill) 27 in substrate 22 (can be brazing metal projection 221) earlier, shown in Fig. 2 a.
A2: with female bearing wafer 21 upsets, make this engagement protrusion (bump) 211 and substrate 22 heat phase pressings again, finish being electrically connected, shown in Fig. 2 b.
B, adopt the surface mount mode to paste sub-wafer 23 again:
B: the glutinous brilliant glue 28 of coating above female bearing wafer 22, with glue unifier wafer 23, shown in Fig. 2 c.
C, with sub-wafer 23 routings:
C: the nail pin that sub-wafer 23 is reserved with the aluminium pad and the substrate 22 of the sub-wafer 23 of metal wire 24 conductings is electrically connected it, shown in Fig. 2 d.
D, will put in order group member encapsulation:
D: with the whole module that is constituted by substrate 22, female bearing wafer 21 and sub-wafer 23 of organizing of rubber polymer 26 encapsulation, shown in Fig. 2 e.
Implement according to the invention described above mode, can commonly use the routing processing procedure that method for packing is save one parent crystal sheet, and can reduce encapsulation required area and volume significantly, can reduce signal delay again.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; can do various conversion and modification, so protection scope of the present invention should define simultaneously with reference to the content in claims.

Claims (1)

1, a kind of chip connection method of crystal covered package, it mainly is at the wafer that piles up two same sizes during in same substrate, earlier projection on female bearing wafer and the substrate that is manufactured with the brazing metal projection in advance at the relative position place are added hot pressing, sticker one sub-wafer above female bearing wafer then, this sub-wafer adopts routing mode with sub-wafer of metal wire conducting and substrate, and the whole group of encapsulation is by substrate, module that female bearing wafer and sub-wafer constituted.
CN00121465A 2000-07-24 2000-07-24 Chip connecting method for chip assembly Pending CN1335642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN00121465A CN1335642A (en) 2000-07-24 2000-07-24 Chip connecting method for chip assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN00121465A CN1335642A (en) 2000-07-24 2000-07-24 Chip connecting method for chip assembly

Publications (1)

Publication Number Publication Date
CN1335642A true CN1335642A (en) 2002-02-13

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Application Number Title Priority Date Filing Date
CN00121465A Pending CN1335642A (en) 2000-07-24 2000-07-24 Chip connecting method for chip assembly

Country Status (1)

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CN (1) CN1335642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477955B (en) * 2008-01-04 2013-04-10 南茂科技股份有限公司 Encapsulation structure and method for tablet reconfiguration
CN105374776A (en) * 2014-08-13 2016-03-02 三星电子株式会社 Semiconductor chip, semiconductor device, and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477955B (en) * 2008-01-04 2013-04-10 南茂科技股份有限公司 Encapsulation structure and method for tablet reconfiguration
CN105374776A (en) * 2014-08-13 2016-03-02 三星电子株式会社 Semiconductor chip, semiconductor device, and method of manufacturing the same
US10249604B2 (en) 2014-08-13 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN112071764A (en) * 2014-08-13 2020-12-11 三星电子株式会社 Semiconductor chip, semiconductor device and method for manufacturing the same

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