CN1333450C - Electric connection end structure of embedded chip and its producing method - Google Patents
Electric connection end structure of embedded chip and its producing method Download PDFInfo
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- CN1333450C CN1333450C CNB2004100338616A CN200410033861A CN1333450C CN 1333450 C CN1333450 C CN 1333450C CN B2004100338616 A CNB2004100338616 A CN B2004100338616A CN 200410033861 A CN200410033861 A CN 200410033861A CN 1333450 C CN1333450 C CN 1333450C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to an electric connection end structure of an embedded chip and a manufacturing method of the electric connection end structure. The structure comprises an electrical connection pad, a metallic layer deposited on the electrical connection pad, conducting layers deposited on the metallic layer, and plated metal layers deposited on the conducting layers in an electroplating mode, and is characterized in that an insulating layer is formed on a circuit board structure embedded with the chip; then, the insulating layer forms a plurality of openings, wherein at least one opening corresponds to the position of the electrical connection pad of the chip; the electrical connection pad is exposed out; the metallic layer is formed on the electrical connection pad of the chip; the conducting layers are formed on the surfaces of the metallic layer, the insulating layer and the openings of the insulating layer; subsequently, a pattern obstacle layer which is provided with a plurality of openings is formed on the conducting layer; the pattern obstacle layer is exposed, and then, the conducting layers on the metallic layer are deposited on the pattern obstacle layer; afterwards, an electroplating procedure is carries out, the plated metal layer is formed on the conducting layers exposed on the pattern obstacle layer. The present invention has the advantages of short process flow and time, few processes and low cost.
Description
Technical field
The invention relates to a kind of electricity connection terminal construction and method for making thereof of embedded chip, particularly about a kind of electricity connection terminal construction and manufacture method thereof that is incorporated into semiconductor chip in the circuit board.
Background technology
Development along with semiconductor packaging, semiconductor device (Semiconductor device) has been developed different encapsulation kenels, spherical grid array type (Ball grid array wherein, BGA) semiconductor package part is a kind of advanced person's a semiconductor packaging, its characteristics are to adopt substrate to settle semiconductor chip, and utilize automatic contraposition (Self-alignment) technology, plant the tin ball (Solder ball) of putting a plurality of one-tenth grid arrays arrangements at this substrate back, make on the semiconductor chip carriers of same units area and can hold more I/O link (I/O connection), satisfy the requirement of highly integrated (Integration) semiconductor chip, and borrow these tin balls whole encapsulation unit to be welded and is electrically connected to outside printed circuit board (PCB).
The operation of general semiconductor device, at first produce the chip carrier that is applicable to this semiconductor device by the chip carrier producer, as substrate or lead frame, afterwards, these chip carriers being given semiconductor packages person puts crystalline substance, mold pressing and plants operations such as ball again, at last, just can finish the semiconductor device of the needed electric function of client.Relate to different operation industries (comprising chip carrier manufacturing and semiconductor packages industry) therebetween, therefore not only step is loaded down with trivial details in the actual manufacture process and the interface is difficult for integrating, moreover, when if client will change the function design, the change meeting of its concordant bedding is complicated more, can not satisfy the demand and the economic benefit of change flexibility.
In addition, operation for general flip-chip type semiconductor device, mainly be after finishing wafer integrated circuit operation, in this wafer, form one deck welding block bottom metalization (Under bump metallurgy on the electric connection pad of chip, UBM) structure sheaf is for the bearing metal projection, cut single job again so that this wafer cutting is formed a plurality of chips, afterwards this flip-chip type semiconductor chip is connect and put and be electrically connected on the substrate.Wherein the operation of this UBM structure sheaf and metal coupling at first forms insulating protective layer (Passivation layer) at this semiconductor wafer surface, and expose the electric connection pad position, then on this electric connection pad, utilize sputter and electroplate to form the UBM structure sheaf that includes multiple layer metal; To refuse layer afterwards and be arranged on this insulating protective layer, and this refuses layer and be preset with a plurality of openings, expose this UBM structure sheaf; Carry out the scolder painting process then, for example with the scolder of leypewter (Sn/Pb), refuse the opening of layer by this, utilize the technology of screen painting to be applied to this UBM structure sheaf, carry out reflow (Reflow) operation again scolder is soldered on this UBM structure sheaf, afterwards this being refused layer removes, and carry out reflow second time program with this scolder ballization, on semiconductor crystal wafer, form metal coupling, borrow this metal coupling that being electrically conducted between semiconductor chip and substrate is provided, and then carry out semi-conductive packaging process.
Above-mentioned operation is not only loaded down with trivial details and the interface is difficult integrates, therefore, be the manufacturing of integral chip carrier and the operation of semiconductor packages, but applicant of the present invention develops a kind of board structure of circuit of integrating semiconductor chip, it mainly is to finish wafer integrated circuit operation, and after in this wafer, forming conductive structure on the electric connection pad of chip, cut single job again, this wafer cutting is formed a plurality of chip units, this chip unit is embedded in the default opening of circuit board, on this conductive structure, form the plated metal structure afterwards, and be electrically conducted this chip and this circuit board, finish the board structure of circuit that is integrated with semiconductor chip.
Figure 1A to Fig. 1 I is the operation that forms conductive structure and plated metal structure on the electric connection pad of wafer.Shown in Figure 1A, wafer 10 is provided, this wafer 10 comprises a plurality of chips 100, wherein, this wafer 10 has been finished the integrated circuit operation, and is formed with patterning protective layer 11 on these wafer 10 surfaces, exposes outside the electric connection pad 12 of chip in this wafer.Shown in Figure 1B, on this electric connection pad 12, form zinc impregnation layer 13 (as Catalytic Layer) and electroless-plating nickel dam 14, this nickel dam 14 effectively is attached on this electric connection pad 12, utilizes this nickel dam 14 to make this electric connection pad 12 effectively isolated simultaneously with the copper metal of follow-up formation.Shown in Fig. 1 C, on this nickel dam 14, form deposited gold layer 15, so as to protecting this nickel dam 14, the copper metal of subsequent deposition is effectively adhered on it.Shown in Fig. 1 D, on this gold layer 15, form electroless-plating thick copper layer 16, and this wafer 10 is cut, to form a plurality of chips 100, this chip 100 can be embedded in the prodefined opening 102 of circuit board 101 thereafter.Shown in Fig. 1 E, be embedded with at this and form insulating barrier 17, for example ABF (Japanese trader's aginomoto company produces for Ajinomoto Build-up Film, trade name) on circuit board 101 surfaces of chip 100.Shown in Fig. 1 F, utilize the laser drill technology, remove the partial insulative layer 17 and part thick copper layer 16 of correspondence in electric connection pad 12 positions of this chip, so as to formation opening 170, and with the knitting layer of thick copper layer 16 residual in this opening 170 as the subsequent deposition metal.Can to this opening 170 places carry out de-smear (De-smear) operation thereafter.Shown in Fig. 1 G, form conductive layer 18 at this insulating barrier and this open surfaces, this conductive layer can utilize the electroless-plating mode to form the copper layer earlier via after plating palladium layer (as Catalytic Layer) again.Shown in Fig. 1 H, on this conductive layer 18, form patterning resistance layer 19, and on this resistance layer 19, form a plurality of openings 190, expose outside conductive layer 18 that should chip electric connection pad place.Shown in Fig. 1 I, carry out electroplating work procedure in the opening 190 of this patterning resistance layer 19, to form plated metal structure 191, copper metal for example is for the conductive path of follow-up chip and circuit board.
In the above-mentioned operation, in the conductive structure that forms this chip power connection gasket, must successively form this nickel dam and thick copper layer, but this nickel dam and thick copper layer are to adopt the electroless-plating mode to form, it must spend many activity times and process cost, cause process efficiency obviously to descend, the first deposited gold layer of still needing before forming this thick copper layer simultaneously also causes the increase of process flow and the raising of cost.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of electricity connection terminal construction and method for making thereof of embedded chip, can effectively shorten process flow and time.
Another object of the present invention is to provide a kind of electricity connection terminal construction and method for making thereof of embedded chip, can effectively save process cost.
For reaching above-mentioned and other purpose, the method for making of the electricity connection terminal construction of embedded chip of the present invention, mainly be after finishing wafer integrated circuit operation and a plurality of chip units of cutting formation, this chip unit is embedded in the structure of circuit board, on being integrated with the board structure of circuit of chip, this forms insulating barrier then, and make this insulating barrier form a plurality of openings, wherein, at least one opening is to electric connection pad position that should chip, to expose outside the electric connection pad of this chip, also on the electric connection pad of this chip, form metal level, and at this metal level and this insulating barrier and open surfaces formation conductive layer thereof, then on this conductive layer, form the patterning resistance layer, make this patterning resistance layer form a plurality of openings to expose outside the conductive layer part of this follow-up depositing metal layers thereon, wherein, at least one resistance layer opening corresponds to the electric connection pad position of this chip, can carry out electroplating work procedure afterwards, to form electroplated metal layer on the conductive layer that is revealed in this patterning resistance layer at this, copper metal layer for example.
By above-mentioned operation, the present invention also provides a kind of electricity connection terminal construction of embedded chip, and it mainly comprises: electric connection pad; Be deposited on the metal level on this electric connection pad; Be deposited on the conductive layer on this metal level; And be deposited on electroplated metal layer on this conductive layer with plating mode by this conductive layer.
Therefore, the electricity connection terminal construction of embedded chip of the present invention and method for making thereof, mainly be after wafer integrated circuit operation is finished, the wafer cutting is formed a plurality of chip units, and this chip unit is embedded in the board structure of circuit, directly be integrated with in the board structure of circuit of chip at this, only at the deposition of the enterprising row metal layer of the electric connection pad of chip (for example nickel dam), then can utilize plating mode on this metal level, to form electroplated metal layer simultaneously and formation build-up circuit structure on circuit board earlier.Just, can utilize plating mode to carry out the conductive structure operation of the electricity connection end of chip, carry out layer operation that increase of circuit board conductive wire simultaneously by the present invention.The operation of the electricity connection end of the embedded chip that the applicant invented in the past, be after wafer integrated circuit operation is finished, must on electric connection pad, form earlier conductive structure, again this wafer cutting is formed a plurality of chip units so that be embedded in the board structure of circuit, electrically integrate loaded down with trivial details operations such as this chip and circuit board afterwards again, therefore on the high activity time and funds of the required cost of electroless-plating copper layer that forms this conductive structure, the present invention really can obviously reduce process flow and cost.
Description of drawings
Figure 1A to Fig. 1 I is the electricity connection terminal construction of existing embedded chip and the generalized section of method for making thereof; And
Fig. 2 A to Fig. 2 H is the electricity connection terminal construction of embedded chip of the present invention and the generalized section of method for making thereof.
Embodiment
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.
Fig. 2 A to Fig. 2 H is the electricity connection terminal construction of embedded chip of the present invention and the generalized section of method for making thereof.
Shown in Fig. 2 A, after finishing product circle integrated circuit operation and a plurality of chips 200 of cutting formation, this chip 200 is embedded in the structure of circuit board 201.Wherein these chip 200 surfaces are formed with protective layer (Passivation layer) 21; this protective layer 21 is dielectric layer (Dielectriclayer); in general operation, adopt polyimide layer (Polyimide layer), silicon dioxide layer (Silicon dioxide layer), silicon nitride layer (Siliconnitride layer) etc.; be used to cover this chip 200 surfaces; protect it to avoid external environmental and destruction, and this protective layer 21 have the electric connection pad 22 of a plurality of openings to expose this chip 200.Because the structure of the electric connection pad 22 of this chip 200 is all roughly the same, therefore in order to simplify accompanying drawing and explanation, the present embodiment China National Instruments Import ﹠ Export Corporation shows that single electric connection pad illustrates as example in addition.
Shown in Fig. 2 B, be integrated with at this and form insulating barrier 23 on circuit board 201 of chip 200, the resin type material that this insulating barrier 23 can be non-fiber, for example ABF is that the circuit board that Japanese aginomoto company produces increases layer material (Ajinomoto Build-up Film), or fiber impregnation resin material, bismaleimide-triazine resin (BT, Bismaleimide triazine) for example, BCB is benzocyclobutene (benzo cyclo buthene), LCP is liquid crystal polymer (liquid crystalpolymer), PI is pi (polyimide), PTFE is polytetrafluoroethylene (poly tetrafluoro ethylene), epoxy resin and glass fibre (FR4, FR5) wherein a kind of.
Shown in Fig. 2 C, for example utilize technology such as laser opening to remove partial insulative layer 23, make this insulating barrier 23 form a plurality of openings 230, wherein, at least one opening 230 is corresponding to electric connection pad 22 positions of this chip 200, with the electric connection pad 22 that exposes outside this chip 200.But when utilizing the laser drill technology, also need carry out de-smear (De-smear) operation and remain in glue slag in this opening 230 to remove because of boring.Certainly, when adopting photoinduction insulating material, then can utilize modes such as exposure, development to form a plurality of openings 230, also need remove dregs (De-scum) operation thereafter and remain in the interior dregs of this opening 230 to remove because of development as this insulating barrier 23.
Shown in Fig. 2 D, on the electric connection pad 22 of this chip 200, form layer of metal layer 24 at least, can be used as resistance barrier metal level, wherein, this metal level 24 is nickel metal layer preferably, and it utilizes the electroless-plating depositional mode to form.In addition, in order to make this nickel metal layer 24, can on this electric connection pad 22, deposit layer of metal processing layer 240 (for example zinc impregnation processing layers) earlier effectively attached on this electric connection pad 22.
Shown in Fig. 2 E, form conductive layer 25 on this metal level 24 and this insulating barrier 23 and opening 230 surfaces thereof, this conductive layer 25 is mainly as the required current conduction path of aftermentioned electroplating work procedure, it can be by metal, alloy or precipitation number layer metal level constitute, as by copper, tin, nickel, chromium, titanium, copper-evanohm or tin-lead alloy constitute any composition in the group, by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless-plating or chemical precipitation, for example sputter (Sputtering), evaporation (Evaporation), electric arc steam deposition (Arc vapor deposition), ion beam sputter (Ion beam sputtering), the chemical vapour deposition (CVD) mode that molten diffusing deposition of laser (Laser ablationdeposition) or electricity slurry promote forms.According to the experience of practical operation, this conductive layer 25 preferably is made of the electroless-plating copper particle.
Shown in Fig. 2 F, on this conductive layer 25, be formed with patterning resistance layer 26, this patterning resistance layer 26 is as electroplating resistance layer, make this patterning resistance layer 26 form a plurality of openings 260, with conductive layer 25 parts that expose outside this follow-up depositing metal layers thereon, wherein, at least one resistance layer opening 260 corresponds to electric connection pad 22 positions of this chip 200.
Shown in Fig. 2 G, can carry out electroplating work procedure afterwards, on the conductive layer 25 that is emerging in this patterning resistance layer 26, to form electroplated metal layer 27, for example copper metal layer.Certainly, in the electroplated metal layer 27 on electroplating the electric connection pad 22 that forms this chip 200, also can be integrated with to electroplate on the circuit board 201 of chip 200 and form line layer (figure is mark) at this, with layer operation that increase of the conductive structure operation of the electric connection pad of while integral chip and circuit board conductive wire, so as to step and the cost of simplifying working process.
Shown in Fig. 2 H, after forming this electroplated metal layer 27 removable this resistance layer 26 and the conductive layer 25 that covered by this resistance layer 26.
By above-mentioned operation, the invention provides a kind of electricity connection terminal construction of embedded chip, shown in Fig. 2 G figure, it mainly comprises: electric connection pad 22; Be deposited on the metal level 24 on this electric connection pad 22; Be deposited on the conductive layer 25 on this metal level 24; And be deposited on electroplated metal layer 27 on this conductive layer 25 with plating mode by this conductive layer 25.
Therefore, the electricity connection terminal construction of embedded chip of the present invention and method for making thereof mainly are after wafer integrated circuit operation is finished, the wafer cutting is formed a plurality of chip units, and this chip unit is embedded in the board structure of circuit, directly be integrated with in the board structure of circuit of chip at this, only at the deposition of carrying out nickel dam on the electric connection pad of chip, then can utilize plating mode on this nickel dam, to form the copper layer simultaneously and formation build-up circuit structure on circuit board earlier.Just, can utilize plating mode to carry out the conductive structure operation of the electricity connection end of chip, carry out layer operation that increase of circuit board conductive wire simultaneously by the present invention.The operation of the electricity connection end of the embedded chip that the applicant invented in the past, be after wafer integrated circuit operation is finished, must on electric connection pad, form earlier conductive structure, again this wafer cutting is formed a plurality of chip units so that be embedded in the board structure of circuit, electrically integrate loaded down with trivial details operations such as this chip and circuit board afterwards again, and aspect the high activity time and funds of the required cost of electroless-plating copper layer that forms this conductive structure, the present invention really can obviously reduce process flow and cost.
Claims (30)
1. the method for making of the electricity connection terminal construction of an embedded chip is characterized in that, this method for making comprises:
The circuit board that is embedded with chip is provided, and this chip surface has a plurality of electric connection pads;
Be embedded with at this and form an insulating barrier on circuit board of chip, and make this insulating barrier form a plurality of openings, wherein at least one opening is corresponding to the electric connection pad position of this chip;
On the electric connection pad of this chip, form metal level;
At this metal level and this insulating barrier and open surfaces formation conductive layer thereof;
Form the patterning resistance layer on this conductive layer, make this patterning resistance layer form a plurality of openings, to expose outside the conductive layer part of follow-up depositing metal layers thereon, wherein at least one opening corresponds to the electric connection pad position of this chip; And
Carry out electroplating work procedure on the conductive layer that is revealed in this patterning resistance layer, to form electroplated metal layer.
2. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this method for making after forming this electroplated metal layer, the conductive layer that promptly removes this resistance layer and covered by this resistance layer.
3. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this chip is after finishing wafer integrated circuit operation and a plurality of chip units of cutting formation, and is embedded to circuit board.
4. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, the electroplated metal layer on the electric connection pad of this chip is a copper metal layer.
5. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this metal level is a nickel metal layer.
6. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, effectively is attached on this electric connection pad for making this metal level, earlier plated metal processing layer on this electric connection pad.
7. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 6 is characterized in that, this metalized layer is the zinc impregnation processing layer.
8. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this conductive layer is the copper layer.
9. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, the metal level on the electric connection pad of chip forms in the electroless-plating mode.
10. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this insulating barrier is a kind of in the resin type material of non-fiber and the fiber impregnation resin material.
11. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 10, it is characterized in that this insulating barrier is that circuit board that Japanese aginomoto company produces increases a kind of in layer material, bismaleimide-triazine resin, benzocyclobutene, liquid crystal polymer, pi, polytetrafluoroethylene, epoxy resin and the glass fibre.
12. the method for making as the electricity connection terminal construction of claim 1 or 10 described embedded chips is characterized in that, this insulating barrier is to utilize the laser drill technology to form opening.
13. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 12 is characterized in that, this method for making comprises that also carrying out the de-smear operation residues in glue slag in this opening to remove because of boring.
14. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1 is characterized in that, this insulating barrier is the photoinduction insulating material.
15. the method for making as the electricity connection terminal construction of claim 1 or 14 described embedded chips is characterized in that, this insulating barrier is to utilize exposure and developing technique to form opening.
16. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 15, its special type be, this method for making comprises that also removing the dregs operation residues in dregs in this opening to remove because of development.
17. the method for making of the electricity connection terminal construction of embedded chip as claimed in claim 1, it is characterized in that, this conductive layer is by physical vapour deposition (PVD), chemical vapour deposition (CVD), electroless-plating or chemical precipitation, is to be selected from sputter, evaporation, electric arc steam deposition, ion beam sputter, the molten diffusing deposition of laser and electric a kind of mode of starching in the chemical vapour deposition (CVD) that promotes to form.
18. the electricity connection terminal construction of an embedded chip is characterized in that, this structure comprises:
Electric connection pad;
Be deposited on the metal level on this electric connection pad;
Be deposited on the conductive layer on this metal level; And
Be deposited on electroplated metal layer on this conductive layer by this conductive layer with plating mode.
19. the electricity connection terminal construction of embedded chip as claimed in claim 18 is characterized in that, this chip is after finishing wafer integrated circuit operation and a plurality of chip units of cutting formation, and is embedded to circuit board.
20. the electricity connection terminal construction of embedded chip as claimed in claim 18 is characterized in that, the electroplated metal layer on the electric connection pad of this chip is a copper metal layer.
21. the electricity connection terminal construction of embedded chip as claimed in claim 18 is characterized in that, this conductive layer is the copper layer.
22. the electricity connection terminal construction of embedded chip as claimed in claim 18 is characterized in that, this metal level is a nickel metal layer.
23. the electricity connection terminal construction of embedded chip as claimed in claim 18 is characterized in that, this structure also comprises the metalized layer, and it is formed between this metal level and this electric connection pad.
24. the electricity connection terminal construction of embedded chip as claimed in claim 23 is characterized in that, this metalized layer is the zinc impregnation processing layer.
25. the electricity connection terminal construction of embedded chip as claimed in claim 19 is characterized in that, is formed with insulating barrier on this circuit board, and this insulating barrier has the opening corresponding to the electric connection pad position of this chip.
26. the electricity connection terminal construction of embedded chip as claimed in claim 25 is characterized in that, this insulating barrier is a kind of in the resin type material of non-fiber and the fiber impregnation resin material.
27. the electricity connection terminal construction of embedded chip as claimed in claim 26, it is characterized in that this insulating barrier is that circuit board that Japanese aginomoto company produces increases a kind of in layer material, bismaleimide-triazine resin, benzocyclobutene, liquid crystal polymer, pi, polytetrafluoroethylene, epoxy resin and the glass fibre.
28. the electricity connection terminal construction as claim 25 or 26 described embedded chips is characterized in that, this insulating barrier is to utilize the laser drill technology to form opening.
29. the electricity connection terminal construction of embedded chip as claimed in claim 25 is characterized in that, this insulating barrier is the photoinduction insulating material.
30. the electricity connection terminal construction as claim 25 or 29 described embedded chips is characterized in that, this insulating barrier is to utilize exposure and developing technique to form opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100338616A CN1333450C (en) | 2004-04-15 | 2004-04-15 | Electric connection end structure of embedded chip and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100338616A CN1333450C (en) | 2004-04-15 | 2004-04-15 | Electric connection end structure of embedded chip and its producing method |
Publications (2)
| Publication Number | Publication Date |
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| CN1684239A CN1684239A (en) | 2005-10-19 |
| CN1333450C true CN1333450C (en) | 2007-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100338616A Expired - Fee Related CN1333450C (en) | 2004-04-15 | 2004-04-15 | Electric connection end structure of embedded chip and its producing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101359639B (en) * | 2007-07-31 | 2012-05-16 | 欣兴电子股份有限公司 | Circuit board construction embedded with semi-conductor chip and preparation thereof |
| TWI532424B (en) * | 2014-01-29 | 2016-05-01 | 旭德科技股份有限公司 | Cover structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362090B1 (en) * | 1999-11-06 | 2002-03-26 | Korea Advanced Institute Of Science And Technology | Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method |
| US6417089B1 (en) * | 2000-01-03 | 2002-07-09 | Samsung Electronics, Co., Ltd. | Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM) |
| US6452270B1 (en) * | 2000-10-13 | 2002-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrode |
| US6664128B2 (en) * | 2002-03-01 | 2003-12-16 | Advanced Semiconductor Engineering, Inc. | Bump fabrication process |
-
2004
- 2004-04-15 CN CNB2004100338616A patent/CN1333450C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362090B1 (en) * | 1999-11-06 | 2002-03-26 | Korea Advanced Institute Of Science And Technology | Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method |
| US6417089B1 (en) * | 2000-01-03 | 2002-07-09 | Samsung Electronics, Co., Ltd. | Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM) |
| US6452270B1 (en) * | 2000-10-13 | 2002-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrode |
| US6664128B2 (en) * | 2002-03-01 | 2003-12-16 | Advanced Semiconductor Engineering, Inc. | Bump fabrication process |
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| CN1684239A (en) | 2005-10-19 |
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