CN102420203B - Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body - Google Patents
Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body Download PDFInfo
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- CN102420203B CN102420203B CN201110362534.5A CN201110362534A CN102420203B CN 102420203 B CN102420203 B CN 102420203B CN 201110362534 A CN201110362534 A CN 201110362534A CN 102420203 B CN102420203 B CN 102420203B
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- metal layer
- solder bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- Parts Printed On Printed Circuit Boards (AREA)
Abstract
The invention relates to a micro-interconnection technology in the field of microelectronic package, in particular to a solder bump/metallization (transitional) layer connecting structure body with favorable solderability in the microelectronic package and application of the solder bump/metallization (transitional) layer connecting structure body. The solder bump/metallization (transitional) layer connecting structure body and the application of the solder bump/metallization (transitional) layer connecting structure body are applied to the technical field of manufacturing of bonding pads of substrates and printed circuit boards in general microelectronic connection as well as metallization transitional layers below solder bumps in the flip-chip bonding interconnection. The connecting structure body is formed by connecting the solder bumps with the metallization layer; the metallization layer is an alloy layer formed by co-depositing 59-69 percent by weight of a ferrum element, 31-41 percent by weight of a nickel element and the balance of a cobalt element; and the solder is a tin-silver or tin-silver-copper series lead-free solder alloy with a relatively-high melting point. According to the method, a ferrum-nickel-cobalt alloy layer is plated on a copper (or nickel) layer by adopting an electroplating method. Relative to a ferrum-nickel coating, a small amount of cobalt is added so as to allow the proportion of the contents of the ferrum and the nickel to be maintained at a lower expansion coefficient in a wider range and maintained constant in a wider temperature range.
Description
Technical field
The present invention relates to micro-interconnection technique in microelectronics Packaging field, specifically solder bump/metallization (transition) layer syndeton body and application thereof in a kind of microelectronics Packaging of good weldability, be applicable to general microelectronics connect in substrate and printed circuit board pads, and the manufacture technology field of metallization transition zone under the interconnected middle solder bump of flip-chip.
Background technology
Semiconductor integrated circuit element is called as " rice of industry ".But what in the ordinary course of things, people used is to be with chlamydate packaging body.Electronic Packaging has the several functions such as mechanical support, electrical connection, outer field shield, stress mitigation, heat radiation protection against the tide.Now, electronic equipment rapidly light, thin, short, miniaturization promote the fast development of Electronic Packaging industry.Particularly improving constantly of chip performance, proposes higher requirement to Electronic Packaging density.This is mainly manifested in: the number of pins of encapsulation is more and more; Cloth string pitch is more and more less; Package thickness is more and more thinner; Packaging body area occupied ratio is increasing etc.
In four large basic technologies of Electronic Packaging engineering, in thin and thick membrane technology, micro-interconnection technique, substrate technology, sealing-in and encapsulation technology, micro-interconnection technique plays a part to present and opens down.No matter chip load is to carrier, or packaging body actual load is to substrate, all will use micro-interconnection technique.Flip chip bonding micro-interconnected (FCB) technology be at whole chip surface by grating array arrangements I/O terminal, chip is directly installed on wiring plate in back-off mode, realizes electrical connection by corresponding electrode pad on grating array I/O terminal and wiring plate.Like this, can, in limited area, arrange more terminal, thereby meet the requirement of pin narrow pitch in high-density packages.Key technology in the micro-connection of flip chip bonding is to form salient point in former chip Al wiring electrode district, and wherein solder bump is the most general.There is good adhesion for reaching salient point and Al and passivation layer, prevent again the Elements Diffusion between salient point metal and Al, general multilevel metallization layer, the i.e. UBM (under bump metallization) of first preparing under salient point.Typical adhesiving metal has Ti, Cr, TiN etc., and they must form enough strong adhesion with the chip power utmost point.Typical barrier metal has W, Mo, Ni, Cu etc., as barrier layer, can effectively stop and generate frangible compounds because of Elements Diffusion.Typically layer has Au, Cu, Pd etc., the solderability that they should be good with solder alloy in succession.Equally, when solder bump connects with metal line pad on substrate, also need the metallization of substrate pads, i.e. TSM (topside metallization).In general BGA (ball grid array) encapsulation, chip packing-body actual load, to printed circuit board (PCB), also need to be prepared to the metal layer being connected with solder ball on printed circuit board (PCB).
In microelectronics connection procedure, the general eutectic tin-lead solder that uses of past, wherein 37% is plumbous.The whole world approximately has the lead of 20,000 tons to use as scolder every year.If after these leaded electronic products go out of use and bury, lead in alloy can, gradually by the aqueous corrosion in natural environment, dissolving, diffusion and enrichment, finally cause expendable environmental pollution to natural environment, soil, natural water body and animals and plants biological chain thereof.People start to find the substitute of tin-lead solder thus, mainly concentrate at present on Xi Yin, tin copper and SAC, and the fusing point of these several scolders all more traditional tin-lead solder exceeds 30-40 DEG C.If these lead-free solders are as convex point material, when under they and salient point or when pad metal layer liquid reaction, need higher reflux temperature.In reflux technique process under this high-temperature condition, can make metal layer and solder reaction speed accelerate, when liquid solder and metal layer react, easily make metal layer be consumed fast, make it lose due function.
In addition, in solid-state diffusion process, the ramp of interface compound layer, the Ke Kendaer hole of thick frangible compounds and generation all will have a strong impact on the reliability of connector.In addition, in the use procedure of packaging body, because device does not mate with the heat of circuit board material, will make connector in thermal cycling stresses field, thereby cause connector generation fatigue failure.
Summary of the invention
In view of the actual conditions of above-mentioned prior art, the object of the present invention is to provide solder bump/metallization (transition) layer syndeton body and application thereof in a kind of microelectronics Packaging of good weldability, when the lead-free solder existing in solution prior art is connected with metal layer, easily make metal layer be consumed fast, make it lose due function, and the problem such as connector generation fatigue failure.
To achieve these goals, technical scheme of the present invention is as follows:
Solder bump/metal layer syndeton body in a kind of microelectronics Packaging, this syndeton body is that solder bump and metal layer are formed by connecting, metal layer is the alloy-layer of iron, nickel, cobalt element codeposition, iron weight percentage ranges is 59-69%, nickel weight percentage ranges is 31-41%, and all the other are cobalt; Scolder is Xi-Yin or the tin-silver-copper series lead-free solder alloy that fusing point is relatively high.
Solder bump/metal layer syndeton body in described microelectronics Packaging, in metal layer, iron percentage by weight preferable range is 60-65%, nickel percentage by weight preferable range is 32-35%, weight of cobalt percentage preferable range 3-8%.
Solder bump/metal layer syndeton body in described microelectronics Packaging, in solder component, silver-colored weight percentage ranges is 1-4%, and weight of copper percentage range is 0-3%, and all the other are tin.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, on conducting base surface, or electroplate or chemical plating one deck teleoseal the nonconductive matrix surface covering at conductive film; Scolder, by locating by soldering paste mould printing mode or Place mode, then forms structure after refluxing.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, in the micro-device packaging of teleoseal coating as ball grid array (BGA) encapsulation, flip-chip (flip chip), laminated chips encapsulation or MEMS (micro electro mechanical system) (MEMS), metal layer or substrate pads metal layer under solder bump.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, teleoseal coating forms syndeton body as outermost layer and solder bump.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, teleoseal coating is other deposited gold, platinum, palladium, tin or its alloy layer on surface, then forms syndeton body with solder bump.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, in the micro-device packaging of this structure as ball grid array (BGA) encapsulation, flip-chip (flip chip), laminated chips encapsulation or MEMS (micro electro mechanical system) (MEMS), being connected between micro element and substrate or printed circuit board (PCB).
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, the coefficient of expansion of teleoseal coating regulates by the content of iron in coating, is applicable to the different matrixes that require; Sn-Ag-Cu scolder is adjusted the content of silver and copper according to process conditions and product type.
The application of solder bump/metal layer syndeton body in described microelectronics Packaging, teleoseal coating is at common copper or nickel metal layer substrates; Or teleoseal coating is at the transition metal layer substrates of other types.
Tool of the present invention has the following advantages:
1, the present invention utilizes iron nickel cobalt coating and Xi-Yin or tin-silver-copper lead-free solder to form syndeton body, Xi-Yin or tin-silver-copper scolder are at good wettability and the antioxygenic property of this metal layer surface performance, can be used as outer surface layer, this syndeton can directly be reacted and form with the outer surface layer of metal layer by scolder.
2, between iron nickel cobalt coating of the present invention (metal layer) and Xi-Yin or tin-silver-copper scolder, wettability is good, very slow with the liquid reaction speed of solder interface, generate extremely thin (submicron order thickness) and smooth iron tin compound layer, meet the higher needs of reflux temperature in pb-free solder technique; Within the scope of electrical equipment normal working temperature and in solid-state timeliness, compound growth speed is extremely slow.And the linkage interface forming with scolder has good reliability energy, be applicable to very much the needs of lead-free connect technology in microelectronics Packaging.
3, iron nickel cobalt coating/Xi-Yin of the present invention or tin-silver-copper solder-connected structure body have good mechanics unfailing performance, after hot environment timeliness, and the shear strength that this connector maintenance and copper/Xi-Yin or tin-silver-copper solder structure are suitable.Fracture mainly occurs near in the scolder of compound layer, illustrates that interface reliability is good and stable.
4, in coating of the present invention, the content of iron can be adjusted within the specific limits, is approached the thermal coefficient of expansion of other layers most; In scolder, the scolder of silver and copper can need to be adjusted according to technique, does not affect interface compound growth speed and connector reliability after adjustment.
5, the manufacture craft of iron nickel cobalt coating/Xi-Yin of the present invention or tin-silver-copper solder-connected structure body is relatively simple, and applicability is strong.
6, the present invention can be at conducting base as the surface of copper or nickel, or realize the nonconductive matrix surface covering at conductive film; Can be used as being connected on micro element and substrate or between printed circuit board (PCB), and the manufacture craft of chip bump is used.
7, in the present invention, can, at other coating such as iron nickel cobalt coating coating outside deposition gold, platinum, palladium, tin and alloys thereof, improve anti-oxidant and wettability, then form connector with SAC solder reaction.
8, the interface between metal layer of the present invention and scolder is in backflow and solid-state ag(e)ing process, and compound growth is slow, can play the effect of diffusion impervious layer.
9, the linkage interface of metal layer of the present invention and scolder has good mechanics unfailing performance.After hot environment timeliness, linkage interface keeps higher shear strength.Fracture mainly occurs near in the scolder of compound layer, illustrates that interface reliability is good and stable.
10, the present invention, by the adjusting of cobalt content, makes iron, nickel percentage change at relative broad range, and metal layer has lower hot thermal coefficient of expansion, reduces the damage that in use cyclic thermal stres causes, and improves useful life and the security reliability of device.So iron nickel cobalt coating can be realized low thermal coefficient of expansion in relatively wide composition proportion, and keeps constant in wider temperature range.
11, iron of the present invention, nickel percentage by weight approach invar alloy composition (Fe64Ni36), with respect to invar alloy (Fe64Ni36) metal layer with utmost point low thermal coefficient of expansion, can allow iron, nickel composition ratio to float within the specific limits, this metal layer still can keep low thermal coefficient of expansion, therefore its technique is easily controlled, and applicability is strong.
12, the present invention using teleoseal coating as microelectronics interconnection technique in solder convex point connected metal layer, can be widely used in microelectronics Packaging industry, be particularly suitable for the micro-interconnection technique of high density of the form such as ball grid array, flip-chip.
Brief description of the drawings
Fig. 1 is the applicable flip-chip interconnection technique schematic diagram of coating of the present invention.Wherein, 4 chips; 5 times iron nickel cobalt metal layers; 6 SAC solder bumps; 7 pad iron nickel cobalt metal layers; 8 printed circuit board (PCB)s.
Fig. 2 is the spherical salient point connector of iron nickel cobalt coating/SAC macroscopic cross figure.
Fig. 3 is iron nickel cobalt coating/SAC interface microstructure.
Fig. 4 is copper/SAC interface microstructure.
Fig. 5 is solder reflow process curve.
Fig. 6 is the change curve of iron nickel cobalt coating/SAC interface compound thickness with timeliness number of days.
Fig. 7 is the post-rift fracture surface pattern of iron nickel cobalt coating/SAC connector.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in more detail:
Embodiment 1
At conducting base, as the surface of copper or nickel, or the nonconductive matrix surface covering at conductive film electroplates one deck teleoseal, and its composition and electrodeposited coating thickness all can regulate according to actual requirement.As shown in Figure 1, the coating that the present invention realizes can be used as on substrate and printed circuit board (PCB) 8 on pad iron nickel cobalt metal layer 7, and chip 4 flip chip bondings connect in the lower iron nickel cobalt metal layer 5 of SAC solder bump 6 use.As shown in Figure 2, the spherical salient point connector of iron nickel cobalt coating/SAC macroscopic cross figure.
Adopt electro-plating method on copper matrix, to plate thin layer iron nickel cobalt layer, its composition is: iron 60%, nickel 35%, cobalt 5% (weight percentage).Utilize acetone reagent to clean to coating surface, utilize aperture to print soldering paste salient point for 0.75mm mask plate at coating surface, then centering is placed SAC soldered ball thereon.The composition percentage of soldering paste and soldered ball is: tin 95.8%, silver 3.5%, copper 0.7%.In the BGA & CSP reclamation work station equipment that solder reflow process is produced in ok company of the U.S., carry out, its reflux technique curve used as shown in Figure 5.Sample sealing after reflow soldering in epoxy resin, grind along cross section, polishing and corrosion, utilize its institutional framework of scanning electron microscopic observation.As shown in Figure 3, the microstructure at interface as shown in Figure 4 for the macroscopic cross figure of syndeton body.Number in the figure 1 represents SAC scolder; 2 represent iron nickel cobalt coating; Arrow indication part is generated compound layer 3, and its thickness is about 0.2 μ m.In contrast, the interface of copper/SAC scolder has generated very irregular copper tin compound layer (as shown in Figure 5), and its peak thickness reaches 10 μ m.As can be seen here, the reaction speed of iron nickel cobalt coating and scolder is very slow.The thermal coefficient of expansion of the present embodiment coating is about 4-10 × 10
-6/ DEG C, (be about 5-7 × 10 with the thermal coefficient of expansion of ceramic substrate
-6/ DEG C) match.
As above prepared iron nickel cobalt/SAC scolder connector, carries out different number of days timeliness under 125 DEG C of environment, then its linkage interface compound thickness is measured.Fig. 6 has shown the change curve of two kinds of interface compound thickness with timeliness number of days, and in figure, SnAgCu/Cu is copper/SAC scolder connector, and SnAgCu/Cu (FeNiCo) is iron nickel cobalt/SAC scolder connector.Can find out, in solid-state ag(e)ing process iron nickel cobalt/SAC scolder connector interface compound growth speed far below copper/SAC connector interface, the interface compound grown in thickness of iron nickel cobalt/scolder connector and slowly.Scraping and cutting after test at solder ball, Fig. 7 has shown the break surface pattern of the rear toughness of this syndeton body fracture.These interfaces that all illustrated that this coating and scolder form have good mechanics reliability.
As can be seen here, iron nickel cobalt coating/SAC syndeton body of the present invention not only has lower compound generation and growth rate but also has more reliable mechanical property.Iron content in the present invention in coating can regulate according to different connecting materials, so that articulamentum has good thermal matching energy, in scolder, the content of silver and copper also can need to be adjusted according to technique.So, the present invention be highly suitable between micro element and substrate or printed circuit board (PCB), being connected in microelectronics Packaging and flip-chip technology in the technical field such as stud bump making.
Embodiment 2
Difference from Example 1 is:
The composition of iron nickel dam is: iron 59%, nickel 35%, cobalt 6%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Embodiment 3
Difference from Example 1 is:
The composition of iron nickel dam is: iron 63%, nickel 33%, cobalt 4%;
Solder component: tin 98.5%, silver 1%, copper 0.5%.
Embodiment 4
Difference from Example 1 is:
The composition of iron nickel dam is: iron 67%, nickel 31%, cobalt 2%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Embodiment 5
Difference from Example 1 is:
The composition of iron nickel dam is: iron 65%, nickel 32%, cobalt 3%;
Solder component: tin 98.5%, silver 1%, copper 0.5%.
Embodiment 6
Difference from Example 1 is:
The composition of iron nickel dam is: iron 61%, nickel 34%, cobalt 5%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Embodiment 7
Difference from Example 1 is:
The composition of iron nickel dam is: iron 69%, nickel 31%;
Solder component: tin 98%, silver 2%.
Experimental result shows, in the scope of technical solution of the present invention, iron nickel cobalt coating/SAC syndeton body has lower compound generation and growth rate and good connection reliability energy, teleoseal coating has good wettability and antioxygenic property, lower interface compound growth speed and preferably mechanics reliability.Composition in the present invention in iron nickel cobalt coating can regulate within the specific limits, and its iron percentage by weight is 59-69%; For teleoseal coating, the composition that only has iron and nickel is approaching in the very low range of invar alloy composition, and material just can obtain zero or negative thermal expansion coefficient.Add by a small amount of cobalt element, can allow iron and nickel composition ratio to float within the specific limits, this alloy layer still can keep extremely low or zero thermal expansion coefficient, and therefore its technique applicability is stronger.In SAC scolder, the composition of silver and copper also can be adjusted, and its silver-colored weight percentage ranges is 1-4%, and weight of copper percentage range is 0-3%.The present invention can be on conducting base surface, or realize the nonconductive matrix surface covering at conductive film.Iron nickel cobalt coating/SAC syndeton body can be used as the syndeton between micro element and substrate or printed circuit board (PCB) in BGA packing forms, also can be used as the stud bump making technique of flip-chip in interconnected.
Therefore, this alloy layer can be used as solder convex point connected metal layer use in microelectronics interconnection technique.Teleoseal coating can also directly be connected with solder bump as outermost layer; Also can be on surface other deposited gold, platinum, palladium, tin or its alloy layer, be then connected with solder bump.Teleoseal coating can be in common copper or nickel metal layer electro-deposition; Or, at the transition metal layer substrates of other types.
Claims (7)
1. solder bump/metal layer syndeton body in a microelectronics Packaging, it is characterized in that: this syndeton body is that solder bump and metal layer are formed by connecting, metal layer is the alloy-layer of iron, nickel, cobalt element codeposition, and scolder is Xi-Yin or the tin-silver-copper series lead-free solder alloy that fusing point is relatively high;
In metal layer, by weight percentage, the composition of iron nickel dam is: iron 59%, nickel 35%, cobalt 6%; Accordingly, by weight percentage, in solder component, tin 95.8%, silver 3.5%, copper 0.7%;
Or in metal layer, by weight percentage, the composition of iron nickel dam is: iron 63%, nickel 33%, cobalt 4%; Accordingly, by weight percentage, in solder component, tin 98.5%, silver 1%, copper 0.5%;
Or in metal layer, by weight percentage, the composition of iron nickel dam is: iron 67%, nickel 31%, cobalt 2%; Accordingly, by weight percentage, in solder component, tin 95.8%, silver 3.5%, copper 0.7%;
Or in metal layer, by weight percentage, the composition of iron nickel dam is: iron 65%, nickel 32%, cobalt 3%; Accordingly, by weight percentage, in solder component, tin 98.5%, silver 1%, copper 0.5%;
Or in metal layer, by weight percentage, the composition of iron nickel dam is: iron 61%, nickel 34%, cobalt 5%; Accordingly, by weight percentage, in solder component, tin 95.8%, silver 3.5%, copper 0.7%;
On conducting base surface, or electroplate or chemical plating one deck teleoseal the nonconductive matrix surface covering at conductive film; Scolder, by locating by soldering paste mould printing mode or Place mode, then forms structure after refluxing.
2. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: in the micro-device packaging of teleoseal coating as BGA Package, flip-chip, laminated chips encapsulation or MEMS (micro electro mechanical system), metal layer or substrate pads metal layer under solder bump.
3. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: teleoseal coating forms syndeton body as outermost layer and solder bump.
4. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: teleoseal coating is other deposited gold, platinum, palladium, tin or its alloy layer on surface, then form syndeton body with solder bump.
5. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: in the micro-device packaging of this structure as BGA Package, flip-chip, laminated chips encapsulation or MEMS (micro electro mechanical system), being connected between micro element and substrate or printed circuit board (PCB).
6. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: the coefficient of expansion of teleoseal coating regulates by the content of iron in coating, be applicable to the different matrixes that require; Sn-Ag-Cu scolder is adjusted the content of silver and copper according to process conditions and product type.
7. according to the application of solder bump/metal layer syndeton body in microelectronics Packaging claimed in claim 1, it is characterized in that: teleoseal coating is at common copper or nickel metal layer substrates; Or teleoseal coating is at the transition metal layer substrates of other types.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110362534.5A CN102420203B (en) | 2011-11-16 | 2011-11-16 | Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110362534.5A CN102420203B (en) | 2011-11-16 | 2011-11-16 | Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body |
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| Publication Number | Publication Date |
|---|---|
| CN102420203A CN102420203A (en) | 2012-04-18 |
| CN102420203B true CN102420203B (en) | 2014-07-30 |
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|---|---|---|---|
| CN201110362534.5A Active CN102420203B (en) | 2011-11-16 | 2011-11-16 | Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body |
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| JP7197933B2 (en) * | 2021-05-27 | 2022-12-28 | 石原ケミカル株式会社 | Structure including underbarrier metal and solder layer |
| CN114361041B (en) * | 2021-12-21 | 2023-03-14 | 广东气派科技有限公司 | Manufacturing method for improving Flip chip bump bridging |
| CN116884923A (en) * | 2023-09-07 | 2023-10-13 | 广州先艺电子科技有限公司 | Cover plate packaging structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1200409A (en) * | 1997-05-23 | 1998-12-02 | 陕西钢铁研究所 | Low cobalt enamel sealed iron-nickel-cobalt alloy |
| CN1239863A (en) * | 1998-06-09 | 1999-12-29 | 日东电工株式会社 | Low-expansion circuit board and multilayer circuit board |
| CN101271126A (en) * | 2007-03-19 | 2008-09-24 | 美高Tn株式会社 | Probe needle |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2365730A1 (en) * | 2010-03-02 | 2011-09-14 | Saint-Gobain Glass France | Pane with electric connection element |
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2011
- 2011-11-16 CN CN201110362534.5A patent/CN102420203B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1200409A (en) * | 1997-05-23 | 1998-12-02 | 陕西钢铁研究所 | Low cobalt enamel sealed iron-nickel-cobalt alloy |
| CN1239863A (en) * | 1998-06-09 | 1999-12-29 | 日东电工株式会社 | Low-expansion circuit board and multilayer circuit board |
| CN101271126A (en) * | 2007-03-19 | 2008-09-24 | 美高Tn株式会社 | Probe needle |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
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| CN102420203A (en) | 2012-04-18 |
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