CN102420203A - Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body - Google Patents
Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body Download PDFInfo
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- CN102420203A CN102420203A CN2011103625345A CN201110362534A CN102420203A CN 102420203 A CN102420203 A CN 102420203A CN 2011103625345 A CN2011103625345 A CN 2011103625345A CN 201110362534 A CN201110362534 A CN 201110362534A CN 102420203 A CN102420203 A CN 102420203A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- Parts Printed On Printed Circuit Boards (AREA)
Abstract
The invention relates to a micro-interconnection technology in the field of microelectronic package, in particular to a solder bump/metallization (transitional) layer connecting structure body with favorable solderability in the microelectronic package and application of the solder bump/metallization (transitional) layer connecting structure body. The solder bump/metallization (transitional) layer connecting structure body and the application of the solder bump/metallization (transitional) layer connecting structure body are applied to the technical field of manufacturing of bonding pads of substrates and printed circuit boards in general microelectronic connection as well as metallization transitional layers below solder bumps in the flip-chip bonding interconnection. The connecting structure body is formed by connecting the solder bumps with the metallization layer; the metallization layer is an alloy layer formed by co-depositing 59-69 percent by weight of a ferrum element, 31-41 percent by weight of a nickel element and the balance of a cobalt element; and the solder is a tin-silver or tin-silver-copper series lead-free solder alloy with a relatively-high melting point. According to the method, a ferrum-nickel-cobalt alloy layer is plated on a copper (or nickel) layer by adopting an electroplating method. Relative to a ferrum-nickel coating, a small amount of cobalt is added so as to allow the proportion of the contents of the ferrum and the nickel to be maintained at a lower expansion coefficient in a wider range and maintained constant in a wider temperature range.
Description
Technical field
The present invention relates to little interconnection technique in microelectronics Packaging field; Solder bump/metallization (transition) layer syndeton body and application thereof in a kind of microelectronics Packaging of good weldability specifically; Be applicable to general microelectronics connect on substrate and the printed circuit board pads, and the manufacture technology field of the metallization transition zone under the interconnected middle solder bump of flip-chip.
Background technology
The semiconductor integrated circuit element is called as " rice of industry ".But in the ordinary course of things, people are employed is the packaging body that has shell.Multiple functions such as Electronic Packaging has mechanical support, is electrically connected, outer field shield, stress relax, heat radiation protection against the tide.Now, the fast development that electronic equipment is light rapidly, thin, short, miniaturization promotes the Electronic Packaging industry.Particularly improving constantly of chip performance proposes higher requirement to Electronic Packaging density.This mainly shows: the number of pins of encapsulation is more and more; The cloth string pitch is more and more littler; Package thickness is more and more thinner; Packaging body area occupied ratio is increasing etc.
In four big basic technologies of Electronic Packaging engineering, promptly in thin and thick membrane technology, little interconnection technique, substrate technology, sealing-in and the encapsulation technology, little interconnection technique plays a part to present and opens down.No matter the chip load is to carrier, or packaging body is real to install on the substrate, all will use little interconnection technique.Flip chip bonding little interconnected (FCB) technology be on the entire chip surface by grating array arrangements I/O terminal, chip directly is installed on the wiring plate with the back-off mode, realizes being electrically connected through corresponding electrode pad on grating array I/O terminal and the wiring plate.Like this, can in limited area, arrange more terminal, thereby satisfy the requirement of pin narrow pitchization in the high-density packages.Key technology in the little connection of flip chip bonding is to form salient point at former chip Al wiring electrode district, and wherein solder bump is the most general.For reaching salient point and Al and passivation layer good adhesion is arranged, prevent the Elements Diffusion between salient point metal and the Al again, general preparation multilevel metallization layer, i.e. UBM (under bump metallization) under salient point earlier.Typical adhesiving metal has Ti, Cr, TiN etc., and they must form enough strong adhesion with the chip power utmost point.Typical barrier metal has W, Mo, Ni, Cu etc., as the barrier layer, can effectively stop because of Elements Diffusion to generate frangible compounds.Typically layer has Au, Cu, Pd etc., the solderability that they should be good with solder alloy in succession.Equally, when solder bump connects with metal line pad on the substrate, also need the metallization of substrate pads, i.e. TSM (topside metallization).In general BGA (ball grid array) encapsulation, chip packing-body is installed on the printed circuit board (PCB) in fact, also need on printed circuit board (PCB), prepare the metal layer that is connected with solder ball.
In the microelectronics connection procedure, the general eutectic tin-lead solder of using of past, wherein 37% is plumbous.The whole world has 20,000 tons lead to use as scolder every year approximately.After if these leaded electronic products go out of use and bury; Lead in the alloy can finally cause expendable environmental pollution to natural environment, soil, natural water body and animals and plants biological chain thereof gradually by the aqueous corrosion in the natural environment, dissolving, diffusion and enrichment.People begin to seek the substitute of tin-lead solder thus, mainly concentrate at present on Xi Yin, tin copper and the SAC, and all more traditional tin-lead solder of the fusing point of these several kinds of scolders exceeds 30-40 ℃.If these lead-free solders are as convex point material, when they and salient point down or during the pad metal layer liquid reaction, reflux temperature that then need be higher.In the reflux technique process under this high-temperature condition, then can make metal layer and solder reaction faster, when liquid solder and metal layer react, metal layer consumed fast, make it lose due function.
In addition, in the solid-state diffusion process, the ramp of interface compound layer, the Ke Kendaer hole of thick frangible compounds and generation all will have a strong impact on the reliability of connector.In addition, in the use of packaging body,, will make connector be in the thermal cycling stresses field, thereby cause connector generation fatigue failure because the heat of device and circuit board material does not match.
Summary of the invention
Actual conditions in view of above-mentioned prior art; The object of the present invention is to provide solder bump/metallization (transition) layer syndeton body and application thereof in a kind of microelectronics Packaging of good weldability; When the lead-free solder that exists in the solution prior art is connected with metal layer; Metal layer is consumed fast, make it lose due function, and problem such as connector generation fatigue failure.
To achieve these goals, technical scheme of the present invention is following:
Solder bump in a kind of microelectronics Packaging/metal layer syndeton body; This syndeton body is that solder bump and metal layer are formed by connecting; Metal layer is the alloy-layer of iron, nickel, cobalt element codeposition; The iron weight percentage ranges is 59-69%, and the nickel weight percentage ranges is 31-41%, and all the other are cobalt; Scolder is higher relatively Xi-Yin of fusing point or tin-silver-copper series lead-free solder alloy.
Solder bump in the described microelectronics Packaging/metal layer syndeton body, in the metal layer, iron percentage by weight preferable range is 60-65%, nickel percentage by weight preferable range is 32-35%, weight of cobalt percentage preferable range 3-8%.
Solder bump in the described microelectronics Packaging/metal layer syndeton body, in the solder component, silver-colored weight percentage ranges is 1-4%, and the weight of copper percentage range is 0-3%, and all the other are tin.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body on the conducting base surface, is perhaps electroplated or chemical plating one deck teleoseal in the nonconductive matrix surface that conductive film covers; Scolder forms structure then through locating with soldering paste mould printing mode or Place mode after refluxing.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body; In the micro element encapsulation of teleoseal coating as BGA (BGA) encapsulation, flip-chip (flip chip), laminated chips encapsulation or MEMS (MEMS), metal layer or substrate pads metal layer under the solder bump.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body, teleoseal coating forms the syndeton body as outermost layer and solder bump.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body, teleoseal coating is other deposited gold, platinum, palladium, tin or its alloy layer on the surface, forms the syndeton body with solder bump then.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body; In the micro element encapsulation of this structure as BGA (BGA) encapsulation, flip-chip (flip chip), laminated chips encapsulation or MEMS (MEMS), being connected between micro element and substrate or the printed circuit board (PCB).
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body, the coefficient of expansion of teleoseal coating is regulated through the content of iron in the coating, is applicable to the matrix of demands of different; The Sn-Ag-Cu scolder is according to the content of process conditions and product type adjustment silver and copper.
The application of solder bump in the described microelectronics Packaging/metal layer syndeton body, the electro-deposition on common copper or nickel metal layer of teleoseal coating; Perhaps, teleoseal coating electro-deposition on the transition metal layer of other types.
The present invention has following advantage:
1, the present invention utilizes iron nickel cobalt coating and Xi-Yin or tin-silver-copper lead-free solder to form the syndeton body; Xi-Yin or tin-silver-copper scolder are at good wettability and the antioxygenic property of this metal layer surface performance; Can be used as outer surface layer, this syndeton can directly be reacted through the outer surface layer of scolder and metal layer and formed.
2, wettability is good between iron nickel cobalt coating of the present invention (metal layer) and Xi-Yin or tin-silver-copper scolder; Very slow with the liquid reaction speed of solder interface; Generate extremely thin (submicron order thickness) and smooth iron tin compound layer, satisfy the higher needs of reflux temperature in the pb-free solder technology; In electrical equipment normal working temperature scope and in the solid-state timeliness, compound growth speed is extremely slow.And have the good reliability ability with the linkage interface that scolder forms, be fit to very much the needs of unleaded interconnection technique in the microelectronics Packaging.
3, iron nickel cobalt coating/Xi of the present invention-Yin or tin-silver-copper solder-connected structure body have the good mechanical unfailing performance, and after the hot environment timeliness, this connector keeps and copper/Xi-Yin or the suitable shear strength of tin-silver-copper solder structure.Fracture mainly occurs in the scolder near compound layer, explains that the interface reliability is good and stable.
4, the content of iron can be adjusted within the specific limits in the coating of the present invention, obtains the thermal coefficient of expansion near other layers; The scolder of silver and copper can be adjusted according to arts demand in the scolder, does not influence interface compound growth speed and connector reliability after the adjustment.
5, the manufacture craft of iron nickel cobalt coating/Xi of the present invention-Yin or tin-silver-copper solder-connected structure body is simple relatively, and applicability is strong.
6, the present invention can perhaps realize in the nonconductive matrix surface that conductive film covers on the surface of conducting base such as copper or nickel; Can be used as on micro element and the substrate or being connected between the printed circuit board (PCB), and the manufacture craft of chip bump is used.
7, can improve anti-oxidant and wettability at other coating such as iron nickel cobalt coating coating outside deposition gold, platinum, palladium, tin and alloys thereof among the present invention, form connector with the SAC solder reaction then.
8, the interface between metal layer of the present invention and scolder is in backflow and solid-state ag(e)ing process, and compound growth is slow, can play the effect of diffusion impervious layer.
9, the linkage interface of metal layer of the present invention and scolder has the good mechanical unfailing performance.After the hot environment timeliness, linkage interface keeps higher shear strength.Fracture mainly occurs in the scolder near compound layer, explains that the interface reliability is good and stable.
10, the present invention makes iron, nickel percentage change at relative broad range through the adjusting of cobalt content, and metal layer has lower hot thermal coefficient of expansion, reduces the damage that cyclic thermal stres in use causes, and improves the useful life and the security reliability of device.So iron nickel cobalt coating can be realized low thermal coefficient of expansion in the composition proportion of relative broad, and in wider temperature range, keeps constant.
11, iron of the present invention, nickel percentage by weight are near invar alloy composition (Fe64Ni36); With respect to the invar alloy with utmost point low thermal coefficient of expansion (Fe64Ni36) metal layer; Can allow iron, nickel composition ratio to float within the specific limits; This metal layer still can keep low thermal coefficient of expansion, so its technology controls easily, and applicability is strong.
12, the present invention as solder convex point connected metal layer in the microelectronics interconnection technique, can be widely used in the microelectronics Packaging industry with teleoseal coating, is particularly suitable for the little interconnection technique of high density of forms such as BGA, flip-chip.
Description of drawings
The flip-chip interconnection technique sketch map that Fig. 1 is suitable for for coating of the present invention.Wherein, 4 chips; 5 times iron nickel cobalt metal layers; 6 SAC solder bumps; 7 pad iron nickel cobalt metal layers; 8 printed circuit board (PCB)s.
Fig. 2 is the spherical salient point connector of iron nickel cobalt coating/SAC macroscopic cross figure.
Fig. 3 is iron nickel cobalt coating/SAC interface microstructure.
Fig. 4 is copper/SAC interface microstructure.
Fig. 5 is the solder reflow process curve.
Fig. 6 is the change curve of iron nickel cobalt coating/SAC interface compound thickness with the timeliness fate.
Fig. 7 is iron nickel cobalt coating/post-rift fracture surface pattern of SAC connector.
Embodiment
Below in conjunction with accompanying drawing to further explain of the present invention:
Embodiment 1
On the surface of conducting base such as copper or nickel, perhaps electroplate one deck teleoseal in the nonconductive matrix surface that conductive film covers, its composition and electrodeposited coating thickness all can require to regulate according to reality.As shown in Figure 1, the coating that the present invention realized can be used as on the substrate with printed circuit board (PCB) 8 on pad iron nickel cobalt metal layer 7, and chip 4 flip chip bondings connect in the following iron nickel cobalt metal layer 5 of SAC solder bump 6 use.As shown in Figure 2, the spherical salient point connector of iron nickel cobalt coating/SAC macroscopic cross figure.
Adopt electro-plating method on the copper matrix, to plate thin layer iron nickel cobalt layer, its composition is: iron 60%, nickel 35%, cobalt 5% (weight percentage).Utilize acetone reagent to clean to coating surface, utilize the aperture to print the soldering paste salient point for the 0.75mm mask plate at coating surface, centering is placed the SAC soldered ball above that then.The composition percentage of soldering paste and soldered ball is: tin 95.8%, silver 3.5%, copper 0.7%.Solder reflow process is carried out in the BGA&CSP reclamation work station equipment that U.S. ok company produces, and its used reflux technique curve is as shown in Figure 5.Admittedly be enclosed in sample after the reflow soldering in the epoxy resin, grind, polish and corrode, utilize its institutional framework of scanning electron microscopic observation along the cross section.The macroscopic cross figure of syndeton body is as shown in Figure 3, and the microstructure at interface is as shown in Figure 4.Label 1 is represented the SAC scolder among the figure; 2 represent iron nickel cobalt coating; The arrow indication partly is the compound layer 3 that is generated, and its thickness is about 0.2 μ m.Compare with it, the interface of copper/SAC scolder has generated very irregular copper tin compound layer (as shown in Figure 5), and its peak thickness reaches 10 μ m.This shows that the reaction speed of iron nickel cobalt coating and scolder is very slow.The thermal coefficient of expansion of present embodiment coating is about 4-10 * 10
-6/ ℃, (be about 5-7 * 10 with the thermal coefficient of expansion of ceramic substrate
-6/ ℃) be complementary.
As above prepared iron nickel cobalt/SAC scolder connector carries out different number of days timeliness under 125 ℃ of environment, then its linkage interface compound thickness is measured.Fig. 6 has shown the change curve of two kinds of interface compound thickness with the timeliness fate, and SnAgCu/Cu is copper/SAC scolder connector among the figure, and SnAgCu/Cu (FeNiCo) is iron nickel cobalt/SAC scolder connector.Can find out that iron nickel cobalt in solid-state ag(e)ing process/SAC scolder connector interface compound growth speed is far below copper/SAC connector interface, the interface compound grown in thickness of iron nickel cobalt/scolder connector and slowly.Solder ball scraping cut test after, Fig. 7 has shown the break surface pattern of this syndeton body fracture back toughness.These interfaces of having explained that all this coating and scolder form have mechanics reliability preferably.
This shows that iron nickel cobalt coating of the present invention/SAC syndeton body not only has lower compound generation and growth rate but also has mechanical property reliably.Iron content among the present invention in the coating can connect material according to difference to be regulated, so that articulamentum has hot preferably matching performance, the content of silver and copper also can be adjusted according to arts demand in the scolder.So, the present invention be highly suitable for being connected between the micro element and substrate or printed circuit board (PCB) in the microelectronics Packaging and flip-chip technology in technical fields such as stud bump making.
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 59%, nickel 35%, cobalt 6%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Embodiment 3
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 63%, nickel 33%, cobalt 4%;
Solder component: tin 98.5%, silver 1%, copper 0.5%.
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 67%, nickel 31%, cobalt 2%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 65%, nickel 32%, cobalt 3%;
Solder component: tin 98.5%, silver 1%, copper 0.5%.
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 61%, nickel 34%, cobalt 5%;
Solder component: tin 95.8%, silver 3.5%, copper 0.7%.
Embodiment 7
Be with embodiment 1 difference:
The composition of iron nickel dam is: iron 69%, nickel 31%;
Solder component: tin 98%, silver 2%.
Experimental result shows; In the scope of technical scheme of the present invention; Iron nickel cobalt coating/SAC syndeton body has lower compound generation and growth rate and connection reliability can preferably; Teleoseal coating have excellent wetting capacity can and antioxygenic property, lower interface compound growth speed and mechanics reliability preferably.Composition among the present invention in the iron nickel cobalt coating can be regulated within the specific limits, and its iron percentage by weight is 59-69%; For teleoseal coating, the composition that has only iron and nickel is in the very low range near the invar alloy composition, and material just can obtain zero or negative thermal expansion coefficient.Add through the little cobalt element, can allow iron and nickel composition ratio to float within the specific limits, this alloy layer still can keep extremely low or zero thermal expansion coefficient, so its technology applicability is stronger.The composition of silver and copper also can be adjusted in the SAC scolder, and its silver-colored weight percentage ranges is 1-4%, and the weight of copper percentage range is 0-3%.The present invention can perhaps realize in the nonconductive matrix surface that conductive film covers on the conducting base surface.Iron nickel cobalt coating/SAC syndeton body can be used as the syndeton between the micro element and substrate or printed circuit board (PCB) in the BGA packing forms, also can be used as the stud bump making technology of flip-chip in interconnected.
Therefore, this alloy layer can be used as solder convex point connected metal layer use in the microelectronics interconnection technique.Teleoseal coating can also directly be connected with solder bump as outermost layer; Also can be on the surface other deposited gold, platinum, palladium, tin or its alloy layer, be connected with solder bump then.Teleoseal coating can be in common copper or nickel metal layer electro-deposition; Perhaps, electro-deposition on the transition metal layer of other types.
Claims (10)
1. solder bump/metal layer syndeton body in the microelectronics Packaging; It is characterized in that: this syndeton body is that solder bump and metal layer are formed by connecting; Metal layer is the alloy-layer of iron, nickel, cobalt element codeposition; The iron weight percentage ranges is 59-69%, and the nickel weight percentage ranges is 31-41%, and all the other are cobalt; Scolder is higher relatively Xi-Yin of fusing point or tin-silver-copper series lead-free solder alloy.
2. according to solder bump in the described microelectronics Packaging of claim 1/metal layer syndeton body; It is characterized in that: in the metal layer; Iron percentage by weight preferable range is 60-65%, and nickel percentage by weight preferable range is 32-35%, weight of cobalt percentage preferable range 3-8%.
3. according to solder bump in the described microelectronics Packaging of claim 1/metal layer syndeton body, it is characterized in that: in the solder component, silver-colored weight percentage ranges is 1-4%, and the weight of copper percentage range is 0-3%, and all the other are tin.
4. according to the application of solder bump in the described microelectronics Packaging of claim 1/metal layer syndeton body, it is characterized in that:, perhaps electroplate or chemical plating one deck teleoseal in the nonconductive matrix surface that conductive film covers on the conducting base surface; Scolder forms structure then through locating with soldering paste mould printing mode or Place mode after refluxing.
5. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body; It is characterized in that: in the micro element encapsulation of teleoseal coating as BGA Package, flip-chip, laminated chips encapsulation or MEMS, metal layer or substrate pads metal layer under the solder bump.
6. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body, it is characterized in that: teleoseal coating forms the syndeton body as outermost layer and solder bump.
7. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body; It is characterized in that: teleoseal coating is other deposited gold, platinum, palladium, tin or its alloy layer on the surface, forms the syndeton body with solder bump then.
8. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body; It is characterized in that: in the micro element encapsulation of this structure as BGA Package, flip-chip, laminated chips encapsulation or MEMS, being connected between micro element and substrate or the printed circuit board (PCB).
9. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body, it is characterized in that: the coefficient of expansion of teleoseal coating is regulated through the content of iron in the coating, is applicable to the matrix of demands of different; The Sn-Ag-Cu scolder is according to the content of process conditions and product type adjustment silver and copper.
10. according to the application of solder bump in the described microelectronics Packaging of claim 4/metal layer syndeton body, it is characterized in that: the electro-deposition on common copper or nickel metal layer of teleoseal coating; Perhaps, teleoseal coating electro-deposition on the transition metal layer of other types.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110362534.5A CN102420203B (en) | 2011-11-16 | 2011-11-16 | Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110362534.5A CN102420203B (en) | 2011-11-16 | 2011-11-16 | Solder bump/metallization layer connecting structure body in microelectronic package and application of solder bump/metallization layer connecting structure body |
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|---|---|
| CN102420203A true CN102420203A (en) | 2012-04-18 |
| CN102420203B CN102420203B (en) | 2014-07-30 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114361041A (en) * | 2021-12-21 | 2022-04-15 | 广东气派科技有限公司 | Manufacturing method for improving Flip chip bump bridging |
| JP2022182186A (en) * | 2021-05-27 | 2022-12-08 | 石原ケミカル株式会社 | Structure including under-barrier metal and solder layer |
| CN116884923A (en) * | 2023-09-07 | 2023-10-13 | 广州先艺电子科技有限公司 | Cover plate packaging structure and preparation method thereof |
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| CN1200409A (en) * | 1997-05-23 | 1998-12-02 | 陕西钢铁研究所 | Low cobalt enamel sealed iron-nickel-cobalt alloy |
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| CN101271126A (en) * | 2007-03-19 | 2008-09-24 | 美高Tn株式会社 | Probe needle |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
| WO2011107342A1 (en) * | 2010-03-02 | 2011-09-09 | Saint-Gobain Glass France | Disk with an electrical connection element |
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| CN1200409A (en) * | 1997-05-23 | 1998-12-02 | 陕西钢铁研究所 | Low cobalt enamel sealed iron-nickel-cobalt alloy |
| CN1239863A (en) * | 1998-06-09 | 1999-12-29 | 日东电工株式会社 | Low-expansion circuit board and multilayer circuit board |
| CN101271126A (en) * | 2007-03-19 | 2008-09-24 | 美高Tn株式会社 | Probe needle |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
| WO2011107342A1 (en) * | 2010-03-02 | 2011-09-09 | Saint-Gobain Glass France | Disk with an electrical connection element |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022182186A (en) * | 2021-05-27 | 2022-12-08 | 石原ケミカル株式会社 | Structure including under-barrier metal and solder layer |
| JP7197933B2 (en) | 2021-05-27 | 2022-12-28 | 石原ケミカル株式会社 | Structure including underbarrier metal and solder layer |
| CN114361041A (en) * | 2021-12-21 | 2022-04-15 | 广东气派科技有限公司 | Manufacturing method for improving Flip chip bump bridging |
| CN114361041B (en) * | 2021-12-21 | 2023-03-14 | 广东气派科技有限公司 | Manufacturing method for improving Flip chip bump bridging |
| CN116884923A (en) * | 2023-09-07 | 2023-10-13 | 广州先艺电子科技有限公司 | Cover plate packaging structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102420203B (en) | 2014-07-30 |
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