CN1327503C

CN1327503C - Improvement for shallow slot separated structure height homogeneity

Info

Publication number: CN1327503C
Application number: CNB2004100543771A
Authority: CN
Inventors: 孔蔚然
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2004-09-08
Filing date: 2004-09-08
Publication date: 2007-07-18
Anticipated expiration: 2024-09-08
Also published as: CN1747146A

Abstract

The present invention provides a method for improving shallow slot separated structure height homogeneity. When an oxide layer positioned outside a shallow slot is removed, a plurality of oxide columns or oxide holes arranged in an array are formed on the oxide layer on an active region in order to obtain the optimal polishing speed balance points when a semiconductor substrate with a large active region and high density obtains flattening process treatment. As a result, a shallow slot separated structure with favorable height homogeneity can be obtained.

Description

Promote the method for shallow groove isolation structure high homogeneity

Technical field

The present invention relates to a kind of manufacture method of shallow groove isolation structure, particularly a kind of method of promoting the shallow groove isolation structure high homogeneity.

Background technology

Integrated circuit industry is through after the development of recent decades, and people can have only on the chip of 2 ~ 3 square centimeters of sizes at area, puts the transistor of counting in necessarily into.But on the chip of small size like this, place so huge IC element of number, how to be isolated the interference that prevents to each other between the element, it then is a big technology emphasis, the more important thing is, component size develops towards deep-submicron now, become an inevitable trend, so the importance of isolation technology, just remarkable more day by day.

The mode that isolation technology is used on integrated circuit has two kinds, a kind of is localized oxidation of silicon method (Local oxidation ofSilicon), another kind is shallow grooved-isolation technique (Shallow trench isolation process), but after below the component size convergence 0.25 μ m, the localized oxidation of silicon method again is difficult to deal with the demand on the integrated circuit volume production, and turns to based on shallow grooved-isolation technique.

But, see also shallow groove isolation structure shown in Figure 1, often easily because groove 10 depth-to-width ratios become oxide 12 density unevennesses that cause greatly inserting in the groove 10, therefore dummy active region (dummy active area) (not showing in the drawings) need be set in groove, and when 14 areas of the active region on the Semiconductor substrate when big or active region density is higher, can obtain a polishing speed uniformly for making when the follow-up oxide that removes outside the groove 10, need utilize an anti-phase mask on the oxide layer 12 that has on the larger area active region 14, to form a groove 16, can obtain consistent polishing velocity when making global planarization, but on large tracts of land or highdensity active region 14, form groove 16, often cause oxide layer 12 density of this active region 14 to reduce easily, and cause phenomenons such as polishing speed is not good.

Summary of the invention

The present invention is a kind of method of promoting the shallow groove isolation structure high homogeneity, its step is for providing a Semiconductor substrate earlier, on Semiconductor substrate, form a pad oxide more in regular turn, and nitride layer, then on Semiconductor substrate, form one first patterning photoresist layer, with the first patterning photoresist layer is mask, to pad oxide, nitride layer and Semiconductor substrate are carried out etching, define the position of active region and form a plurality of shallow slot structures, remove the first patterning photoresist layer then, oxide layer of filling up this shallow slot structure of deposition on Semiconductor substrate, on Semiconductor substrate, form one second patterning photoresist layer again, then, with the second patterning photoresist layer is mask, oxide layer is carried out etching, to form the oxide pillars of a plurality of arrayed, the oxide hole, remove the second patterning photoresist layer then, oxide skin(coating) to Semiconductor substrate carries out CMP (Chemical Mechanical Polishing) process one time, oxide pillars and the oxide hole that painstakingly form this moment will remedy the oxidate layer height, the polishing speed that density unevenness caused is inconsistent, thereby obtains a shallow groove isolation structure highly uniformly.

Adopt this method, can adjust the oxide skin(coating) that is filled in the groove effectively because active region area increases or density increases, the inconsistent shortcoming of planarization glossing speed that is caused, and then obtain highly consistent shallow slot structure, and the generation of reduction dish concave elephant effectively.

Description of drawings

Fig. 1 for known be to revise the oxidate density unevenness forms groove at active region schematic diagram.

Fig. 2 to Fig. 9 is a processing step schematic diagram of the present invention.

Label declaration:

10 grooves, 26 photoresist layers, 36 second patterning photoresist layers

12 oxides, 28 first patterning photoresist layers, 37 pattern area

14 active regions, 30 grooves, 38 oxide pillars

16 grooves, 31 active regions, 40 oxide holes

20 Semiconductor substrate, 32 substrate oxide layers, 42 shallow groove isolation structures

22 pad oxide skin(coating)s, 34 oxide skin(coating)s

The anti-phase mask of 24 nitride layers, 35 active areas

Embodiment

The present invention relates to a kind of method of promoting the shallow groove isolation structure high homogeneity, it can be widely applied to the isolation technology in the semiconductor technology under the deep-submicron, makes interelement obtain best isolation effect.See also Fig. 2; a Semiconductor substrate 20 at first is provided; then Semiconductor substrate 20 is cleaned; to send in the boiler tube of vertical type or horizontal type through the Semiconductor substrate 20 after cleaning then; in oxygen containing environment; on Semiconductor substrate 20, form the pad oxide 22 that material is a silicon dioxide (SiO2); a nitride layer 24 that utilizes the prepared material of Low Pressure Chemical Vapor Deposition for silicon nitride (Si3N4); with a photoresist layer 26; with active area (Active Area) mask (not showing in the drawings) design transfer that includes source region and groove is arrived photoresist then; to form one first patterning photoresist layer 28; as shown in Figure 3; again with anisotropic etching (Anisotropic Etch); the nitride layer 24 of no photoetching glue-line protection is removed with pad oxide skin(coating) 22; then carry out the dry etching of silicon trench (Si trench), in order on Semiconductor substrate 20, to form a plurality of groove 30 structures, to define active region 31.

Then, as shown in Figure 4, after finishing groove 30 making, earlier Semiconductor substrate 20 is sent in the hot boiler tube, mode with high-temperature oxydation, form one on silicon irrigation canals and ditches 30 surface and be used for repairing the silicon trench surface because of damage (Damage) that dry etching caused, and substrate oxide layer (Liner Oxide) 32 with silicon corner sphering (Corner rounding), utilize chemical vapour deposition technique to carry out material then and fill out ditch for the oxide layer 34 of silicon dioxide, till oxide layer 34 is filled up groove 30, form structure as shown in Figure 5.

Then, on Semiconductor substrate 20, form a photoresist layer, be mask with a reverse mask of active area as shown in Figure 6 (ACT-reverse Mask) 35 again, photoresist layer is carried out design transfer, to form as shown in Figure 7 second a patterning photoresist layer 36, wherein have a plurality of oxide pillars arranged into an array or the pattern area 37 in oxidation hole on the anti-phase mask 35 of active area, be mask then with the second patterning photoresist layer 36, oxide skin(coating) 34 is carried out etching, to form oxide pillars that is positioned at a plurality of arrayed on the active region 31 38 or oxide hole 40 as shown in Figure 8, remove the second patterning photoresist layer 36 then.In addition, before forming photoresist layer, more can carry out The high temperature anneal one time, to improve the quality and the density of oxide skin(coating) to oxide skin(coating) 34.

As shown in Figure 9, be the face planarization of demanding perfection, Semiconductor substrate 20 is carried out CMP (Chemical Mechanical Polishing) process one time, this moment will be because of the correction of oxide pillars 38 with oxide hole 40, make the density variation that is deposited on groove 30 and the active region 31 oxide skin(coating) 34 reduce to minimum, make the polishing speed when carrying out chemico-mechanical polishing can access best consistency, and then obtain the shallow groove isolation structure 42 of high homogeneity.

Wherein about arranging density, the arrangement mode of oxide pillars 38 with oxide hole 40, can derive by experiment, utilize and earlier an oxide that does not form oxide pillars and oxide hole is carried out chemico-mechanical polishing, to observe the polishing speed of zones of different, carry out the suitable correction in oxide pillars 38 and oxide hole 40 again, for example the very fast easily recessed part of generation dish of polishing speed can increase a plurality of oxide pillars 38, revises polishing speed.

In sum, the present invention is a kind of method of promoting the shallow groove isolation structure high homogeneity, it utilizes a reverse mask of active area, make the oxide layer surface that is positioned on the active area form the oxide pillars and the oxide hole of a plurality of arrayed, remedy the disappearance that prior art only makes at big active region groove of formation that the oxide skin(coating) density of active region reduces, when thereby correction is polished oxide skin(coating), cause is positioned at the caused polishing speed inequality of oxide layer density variation of shallow groove isolation structure and active region, and then obtains shallow groove isolation structure highly uniformly.

Above-described embodiment is only in order to illustrate technological thought of the present invention and characteristics; its purpose makes those of ordinary skill in the art can understand content of the present invention and is implementing according to this; the scope of this patent also not only is confined to above-mentioned specific embodiment; be all equal variation or modifications of doing according to disclosed spirit, still be encompassed in protection scope of the present invention.

Claims

1. method of promoting the shallow groove isolation structure high homogeneity, its step includes:

A Semiconductor substrate is provided;

On this Semiconductor substrate, form a pad oxide in regular turn, and a nitride layer;

On this Semiconductor substrate, form one first patterning photoresist layer, with this first patterning photoresist layer is mask, this pad oxide, this nitride layer and this Semiconductor substrate are carried out etching, to define active region, remove this first patterning photoresist layer then to form a plurality of shallow slot structures;

Oxide skin(coating) of deposition on this Semiconductor substrate is to fill up this shallow slot structure;

On this Semiconductor substrate, form one second patterning photoresist layer, with this second patterning photoresist layer is mask, this oxide skin(coating) is carried out etching, on the oxide skin(coating) of active region, to form oxide pillars, the oxide hole of a plurality of arrayed, remove this second patterning photoresist layer then; And

Utilize chemical mechanical polishing method that this oxide skin(coating) that is positioned on this Semiconductor substrate is carried out flatening process.

2. the method for enhancement shallow groove isolation structure high homogeneity according to claim 1 is characterized in that: the material of this pad oxide is a silicon dioxide.

3. the method for enhancement shallow groove isolation structure high homogeneity according to claim 1 is characterized in that: the material of this nitride layer is a silicon nitride.

4. the method for enhancement shallow groove isolation structure high homogeneity according to claim 3 is characterized in that: this nitride layer is to utilize Low Pressure Chemical Vapor Deposition formed.

5. the method for enhancement shallow groove isolation structure high homogeneity according to claim 1, it is characterized in that: before this oxide skin(coating) of deposition, earlier this Semiconductor substrate is sent in the hot boiler tube,, in this shallow slot structure, formed one deck substrate oxide layer in the mode of high-temperature oxydation.

6. the method for enhancement shallow groove isolation structure high homogeneity according to claim 1 is characterized in that: this oxide skin(coating) is to utilize chemical vapour deposition technique formed.

7. the method for enhancement shallow groove isolation structure high homogeneity according to claim 1 is characterized in that: after finishing this oxide deposition this oxide skin(coating) is carried out The high temperature anneal one time.