CN1319127C - Method for semultaneous forming silicide and shallow junction - Google Patents
Method for semultaneous forming silicide and shallow junction Download PDFInfo
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- CN1319127C CN1319127C CNB02112146XA CN02112146A CN1319127C CN 1319127 C CN1319127 C CN 1319127C CN B02112146X A CNB02112146X A CN B02112146XA CN 02112146 A CN02112146 A CN 02112146A CN 1319127 C CN1319127 C CN 1319127C
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- silicide
- metal
- impurity
- present
- shallow junction
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a method for forming silicide and source leakage shallow junction simultaneously. At present, a silicide preparation process is started after source and drain implantation and anneal activation and junction, has the problem of reliability and influences the final performance of transistors simultaneously. The present invention forms required metal for forming silicide is deposited on a silicon substrate; impurities are filled below the metal, and then the silicide and shallow junction are formed simultaneously through anneal. The present invention avoids some problems caused by the silicide a diffusion source and the impurities are filled below the metal. The present invention has the characteristics of deep junction, easy control, high impurity density and good repeatability and reduces at least two process steps, such as oxides as an injection mask, high-temperature anneal, etc. The present invention has the advantages of process simplification, short process and low cost.
Description
Technical field
The invention belongs to field of IC technique, be specifically related to a kind of method that forms silicide and shallow junction simultaneously.
Background technology
Along with the continuous development of integrated circuit, transistorized minimum feature is constantly dwindled, and the length that present main flow technology 0.18 μ m technology is exactly a finger grid is 0.18 micron.When live width was constantly dwindled, in order to improve transistorized performance, the degree of depth of source/drain junction was also constantly reducing, and the degree of depth of tying under 0.18 μ m technology has only tens nanometer.
At present the technology of main flow all is after definition finishes, finish just that the high dose that finishes injects and annealing after, PVD (physical vapor deposition) depositing metal forms silicide by rapid thermal treatment again.Because the growth of silicide itself can consume a part of silicon, so if silicide process is bad, the interface out-of-flatness of silicide and silicon, perhaps junction depth control bad (shallow excessively), when the source-drain electrode making alive, be easy to cause the generation of electric leakage at the position of interface projection, cause the inefficacy of device.As shown in Figure 1.In this external silicide forming process, the problem that also has impurity to distribute again need be considered silicide process to final Impurity Distribution, just the influence of transistor performance.
It is after silicide forms that method is also arranged, and injects by ion impurity (for example As, B) is injected into silicide, by heating, allows impurity diffuse out from silicide again, and shallow junction is leaked in the formation source.Help solution to cause the irregular problem in interface because of silicide process is bad like this, but here silicide itself is used as a diffuse source, on to the control of Impurity Distribution and process repeatability, all have certain problem, and diffusion technology itself is eliminated in advanced person's manufacturing process.
Summary of the invention
The objective of the invention is to propose a kind of weakness that becomes knot technology before the silicide of both can having eliminated, form the method for silicide and shallow junction when can avoid impurity to inject diffusing into behind the silicide the existing problem of knot technology again.Has the advantage that knot is shallow, concentration is high, be easy to control.
When proposing, the present invention forms the method for silicide and shallow junction, be after PVD deposit on the silicon substrate forms the required metal level of silicide, when ion implanted impurity, do not allow impurity rest in the metal, and to allow the peak depth of impurities concentration distribution just in time be positioned at the degree of depth of the following 3nm-10nm of metal (surface of silicon just), as shown in Figure 2; And in thermal process subsequently,, also finish the activation and the formation of shallow junction simultaneously in the formation of finishing silicide by two step quick thermal treatment process.
The concrete steps of the inventive method are as follows:
1, forms the required metal of silicide by the PVD method in the deposit of surface of silicon full wafer, as Co/Ti;
2, be to inject mask with the metal level, finish source/drain junction and grid dosage ion and inject that the peak value that makes impurity concentration is just in time at the following 3-10nm of surface of silicon;
3, adopt the method for rapid thermal annealing,, form high-resistance silicide, as CoSi lower temperature such as 500-600 ℃;
4,,, eroded as Co or Ti etc. with unwanted and unreacted metal;
5, the rapid thermal annealing by higher temperature such as 950-1000 ℃ forms low-resistance silicide, as CoSi
2, and finish impurity activation and shallow junction formation simultaneously.
In the inventive method, because when silicide formed, impurity can be pushed downwards diffusion, simultaneously since Impurity Distribution below metal, under certain thermodynamic condition, this method can guarantee all the time that the lower surface of shallow junction and the lower surface of silicide have certain distance.In heat activation subsequently, can ignore the influence of silicide self so to a great extent down.Avoid occurring defective shown in Figure 1.Because the ion that injects has had certain degree of depth, in heat treatment subsequently, downward diffusion just needn't consider that emphasis is the activation of impurity too much for impurity, so both can improve the concentration of doping, can guarantee the degree of depth of tying again in addition.And in the former technology, be annealing after injecting, take into account the requirement of the concentration and the degree of depth.And impurity has activated and has distributed in traditional technology, in silicide process subsequently, the one, the impurity that is heated once again can spread again, and the 2nd, it is different that the distribution in silicon is followed in the distribution of impurity in silicide, thereby the problem that distributes again of the impurity that also will consider to eject from silicide.And in this method, because shallow junction not formation as yet, so though the problem that needs consideration impurity to eject from silicide is much smaller with respect to conventional method for the influence of junction depth and CONCENTRATION DISTRIBUTION.Another advantage of this method is to have saved oxide as injecting this procedure of mask, directly does mask with the PVD metal; Saved a high annealing (referring to be annealed into knot) in addition.Simplify operation greatly, the flow process time of shortening, reduced cost.
Among the present invention, should can use up-to-date rapid thermal annealing (RTP) mode at present more than 950 degree in the short annealing temperature after the injection, as SPIKE annealing and IMPULSE annealing, these annealing way can both guarantee that the electricity of impurity activates and distributed depth.Simultaneously, not only can form silicide but also can not destroy the quality of silicide because the time is very short.Among the present invention, the P type injects can use B (boron) or BF
2(boron difluoride), dosage are 1 * 10
15-5 * 10
15/ cm
2, energy is at 30-50keV; The N type injects then will use As (arsenic) or P (phosphorus), and dosage is 1 * 10
15-5 * 10
15/ cm
2, energy is at 50-100keV.
The present invention owing to taked will form the reliability that method that silicide and formation source leakage shallow junction finish has together guaranteed shallow junction, and it is easy to control to have junction depth, knot doping content height, characteristics such as the distribution of impurity concentration is more stable, the quality of silicide also is guaranteed simultaneously.This method also has the characteristics of good reproducibility owing to use the method for injecting with respect to the mode of diffusion impurity from silicide.Relative in addition traditional handicraft has also reduced the oxidation step thing and has done the operation of injecting mask, and the operation of a step high annealing, has simplified technology, and the flow process of shortening has reduced cost.
Description of drawings
Fig. 1 is that unsmooth interface that silicide forms can cause the diagram of leaking electricity.
Fig. 2 is after intermediate ion of the present invention injects, and the peak value of impurity concentration is in the following diagram of surface of silicon.
Number in the figure: 1 is silicon substrate, and 2 is silicide, and 3 is shallow junction, and 4 is foreign atom, and 5 is metal level.
Embodiment
Implementation step of the present invention is as follows:
1, with the hydrofluoric acid cleaning silicon wafer surface of dilution, the method by PVD forms the required metal of silicide in the deposit of silicon chip surface full wafer, as Co (cobalt)/Ti (titanium).
2, serve as to inject mask with metal level such as Co/Ti, finish the injection of source/drain junction and grid dosage, the peak value that makes impurity concentration is just in time below surface of silicon, as 5nm.
3, adopt the method for rapid thermal annealing,,, form high-resistance silicide, as CoSi as 550 ℃ at lower temperature.
4,,, eroded as Co or Ti metal with unwanted and unreacted metal.
5, (use SPIKE annealing (the supper-fast thermal annealing of spike formula) or IMPULSE annealing modes such as (the supper-fast thermal annealings of assisted)) forms low-resistance silicide by the rapid thermal annealing of higher temperature (950-1000 ℃), as CoSi
2, and finish the formation of impurity activation and knot simultaneously.
Claims (2)
1, a kind of method that forms silicide and shallow junction simultaneously, it is characterized in that after the surface of silicon physical vapor deposition forms the required metal level of silicide, inject by ion impurity is injected into below the metal, make impurities concentration distribution peak value 3～10nm below metal, and in heat treatment process subsequently, go on foot quick thermal treatment process by two, when finishing silicide formation, also finish the activation of impurity and the formation of shallow junction.
2, method according to claim 1 is characterized in that concrete steps are as follows:
(1) forms the required metal of silicide by the physical vapor deposition method in the deposit of surface of silicon full wafer;
(2) be to inject mask with the metal level, finish source/drain junction and grid dosage ion and inject that the peak value that makes impurities concentration distribution is just in time at the following 3-10nm of surface of silicon;
(3) method of employing rapid thermal annealing under lower temperature 500-600 ℃, forms high-resistance silicide;
(4) unwanted and unreacted metal are eroded;
(5) rapid thermal annealing by 950-1000 ℃ of high temperature forms low-resistance silicide, and finishes impurity activation and shallow junction formation simultaneously;
Wherein, implanted dopant adopts As or P, and dosage is 1 * 10
15-5 * 10
15/ cm
2, energy is 50-100keV, perhaps implanted dopant adopts B or BF
2, dosage is 1 * 10
15-5 * 10
15/ cm
2, energy is 30-50keV;
Described high-temperature quick thermal annealing adopts supper-fast thermal annealing of spike formula or the supper-fast thermal annealing of assisted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02112146XA CN1319127C (en) | 2002-06-20 | 2002-06-20 | Method for semultaneous forming silicide and shallow junction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02112146XA CN1319127C (en) | 2002-06-20 | 2002-06-20 | Method for semultaneous forming silicide and shallow junction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1385879A CN1385879A (en) | 2002-12-18 |
| CN1319127C true CN1319127C (en) | 2007-05-30 |
Family
ID=4741908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02112146XA Expired - Fee Related CN1319127C (en) | 2002-06-20 | 2002-06-20 | Method for semultaneous forming silicide and shallow junction |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928324A (en) * | 2014-03-24 | 2014-07-16 | 中国电子科技集团公司第五十五研究所 | AlGaN/GaN HEMT manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5536684A (en) * | 1994-06-30 | 1996-07-16 | Intel Corporation | Process for formation of epitaxial cobalt silicide and shallow junction of silicon |
| US6258682B1 (en) * | 2000-10-17 | 2001-07-10 | Vanguard International Semiconductor Corporation | Method of making ultra shallow junction MOSFET |
| US6274511B1 (en) * | 1999-02-24 | 2001-08-14 | Advanced Micro Devices, Inc. | Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer |
| US6316319B1 (en) * | 1999-07-20 | 2001-11-13 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having shallow junctions |
| US6383901B1 (en) * | 2001-01-25 | 2002-05-07 | Macronix International Co., Ltd. | Method for forming the ultra-shallow junction by using the arsenic plasma |
-
2002
- 2002-06-20 CN CNB02112146XA patent/CN1319127C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5536684A (en) * | 1994-06-30 | 1996-07-16 | Intel Corporation | Process for formation of epitaxial cobalt silicide and shallow junction of silicon |
| US6274511B1 (en) * | 1999-02-24 | 2001-08-14 | Advanced Micro Devices, Inc. | Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer |
| US6316319B1 (en) * | 1999-07-20 | 2001-11-13 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having shallow junctions |
| US6258682B1 (en) * | 2000-10-17 | 2001-07-10 | Vanguard International Semiconductor Corporation | Method of making ultra shallow junction MOSFET |
| US6383901B1 (en) * | 2001-01-25 | 2002-05-07 | Macronix International Co., Ltd. | Method for forming the ultra-shallow junction by using the arsenic plasma |
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| Publication number | Publication date |
|---|---|
| CN1385879A (en) | 2002-12-18 |
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Effective date of registration: 20060901 Address after: 201203 No. 177 blue wave road, Zhangjiang hi tech park, Shanghai, Pudong New Area Applicant after: Shanghai Huahong (Group) Co., Ltd. Co-applicant after: Shanghai integrated circuit research and Development Center Co., Ltd. Address before: 18, Huaihai Road, Shanghai, No. 200020, building 918 Applicant before: Shanghai Huahong (Group) Co., Ltd. |
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