CN1385879A

CN1385879A - Method for semultaneous forming silicide and shallow junction

Info

Publication number: CN1385879A
Application number: CN 02112146
Authority: CN
Inventors: 胡恒升
Original assignee: Shanghai Huahong Group Co Ltd
Current assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date: 2002-06-20
Filing date: 2002-06-20
Publication date: 2002-12-18
Anticipated expiration: 2022-06-20
Also published as: CN1319127C

Abstract

At present, a silicide is prepared by filling in source and drain and anneal activate which exists the shortcoming of reliability and influences the final performance to transistors. This invention is to form a metal necessary to silicons by depositing on the substrate, then injecting in impurities below the metal to form silicide and shallow junction after anneal to avoid problems brough the silicide the diffusion source. Advantages are junction depth is easy to be controlled, high concentration of impurities and good repeatability and reducing two procedures of taking oxides as injection mask and high temperature anneal.

Description

A kind of method that forms silicide and shallow junction simultaneously

Technical field

The invention belongs to field of IC technique, be specifically related to a kind of method that forms silicide and shallow junction simultaneously.

Background technology

Along with the continuous development of integrated circuit, transistorized minimum feature is constantly dwindled, and the length that present main flow technology 0.18 μ m technology is exactly a finger grid is 0.18 micron.When live width was constantly dwindled, in order to improve transistorized performance, the degree of depth of source/drain junction was also constantly reducing, and the degree of depth of tying under 0.18 μ m technology has only tens nanometer.

At present the technology of main flow all is after definition finishes, finish just that the high dose that finishes injects and annealing after, PVD (physical vapor deposition) depositing metal forms silicide by rapid thermal treatment again.Because the growth of silicide itself can consume a part of silicon, so if silicide process is bad, the interface out-of-flatness of silicide and silicon, perhaps junction depth control bad (shallow excessively), when the source-drain electrode making alive, be easy to cause the generation of electric leakage at the position of interface projection, cause the inefficacy of device.As shown in Figure 1.In this external silicide forming process, the problem that also has impurity to distribute again need be considered silicide process to final Impurity Distribution, just the influence of transistor performance.

It is after silicide forms that method is also arranged, and injects by ion impurity (for example As, B) is injected into silicide, by heating, allows impurity diffuse out from silicide again, and shallow junction is leaked in the formation source.Help solution to cause the irregular problem in interface because of silicide process is bad like this, but here silicide itself is used as a diffuse source, on to the control of Impurity Distribution and process repeatability, all have certain problem, and diffusion technology itself is eliminated in advanced person's manufacturing process.

Summary of the invention

The objective of the invention is to propose a kind of weakness that becomes knot technology before the silicide of both can having eliminated, form the method for silicide and shallow junction when can avoid impurity to inject diffusing into behind the silicide the existing problem of knot technology again.Has the advantage that knot is shallow, concentration is high, be easy to control.

When proposing, the present invention forms the method for silicide and shallow junction, be after PVD deposit on the silicon substrate forms the required metal level of silicide, when ion implanted impurity, do not allow impurity rest in the metal, and to allow the peak depth of impurities concentration distribution just in time be positioned at the degree of depth of the following 3nm-10nm of metal (surface of silicon just), as shown in Figure 2; And in thermal process subsequently,, also finish the activation and the formation of shallow junction simultaneously in the formation of finishing silicide by two step quick thermal treatment process.

The concrete steps of the inventive method are as follows:

1, forms the required metal of silicide by the PVD method in the deposit of surface of silicon full wafer, as Co/Ti;

2, be to inject mask with the metal level, finish source/drain junction and grid dosage ion and inject that the peak value that makes impurity concentration is just in time at the following 3-10nm of surface of silicon;

3, adopt the method for rapid thermal annealing,, form high-resistance silicide, as CoSi lower temperature such as 500-600 ℃;

4,,, eroded as Co or Ti etc. with unwanted and unreacted metal;

5, the rapid thermal annealing by higher temperature such as 950-1000 ℃ forms low-resistance silicide, as CoSi ₂, and finish impurity activation and shallow junction formation simultaneously.

In the inventive method, because when silicide formed, impurity can be pushed downwards diffusion, simultaneously since Impurity Distribution below metal, under certain thermodynamic condition, this method can guarantee all the time that the lower surface of shallow junction and the lower surface of silicide have certain distance.In heat activation subsequently, can ignore the influence of silicide self so to a great extent down.Avoid occurring defective shown in Figure 1.Because the ion that injects has had certain degree of depth, in heat treatment subsequently, downward diffusion just needn't consider that emphasis is the activation of impurity too much for impurity, so both can improve the concentration of doping, can guarantee the degree of depth of tying again in addition.And in the former technology, be annealing after injecting, take into account the requirement of the concentration and the degree of depth.And impurity has activated and has distributed in traditional technology, in silicide process subsequently, the one, the impurity that is heated once again can spread again, and the 2nd, it is different that the distribution in silicon is followed in the distribution of impurity in silicide, thereby the problem that distributes again of the impurity that also will consider to eject from silicide.And in this method, because shallow junction not formation as yet, so though the problem that needs consideration impurity to eject from silicide is much smaller with respect to conventional method for the influence of junction depth and CONCENTRATION DISTRIBUTION.Another advantage of this method is to have saved oxide as injecting this procedure of mask, directly does mask with the PVD metal; Saved a high annealing (referring to be annealed into knot) in addition.Simplify operation greatly, the flow process time of shortening, reduced cost.

Among the present invention, should can use up-to-date rapid thermal annealing (RTP) mode at present more than 950 degree in the short annealing temperature after the injection, as SPIKE annealing and IMPULSE annealing, these annealing way can both guarantee that the electricity of impurity activates and distributed depth.Simultaneously, not only can form silicide but also can not destroy the quality of silicide because the time is very short.Among the present invention, the P type injects can use B (boron) or BF ₂(boron difluoride), dosage are 1-5 * 10 ¹⁵/ cm ², energy is at 30-50keV; The N type injects then will use As (arsenic) or P (phosphorus), and dosage is 1-5 * 10 ¹⁵/ cm ², energy is at 50-100keV.

The present invention owing to taked will form the reliability that method that silicide and formation source leakage shallow junction finish has together guaranteed shallow junction, and it is easy to control to have junction depth, knot doping content height, characteristics such as the distribution of impurity concentration is more stable, the quality of silicide also is guaranteed simultaneously.This method also has the characteristics of good reproducibility owing to use the method for injecting with respect to the mode of diffusion impurity from silicide.Relative in addition traditional handicraft has also reduced the oxidation step thing and has done the operation of injecting mask, and the operation of a step high annealing, has simplified technology, and the flow process of shortening has reduced cost.

Description of drawings

Fig. 1 is that unsmooth interface that silicide forms can cause the diagram of leaking electricity.

Fig. 2 is after intermediate ion of the present invention injects, and the peak value of impurity concentration is in the following diagram of surface of silicon.

Number in the figure: 1 is silicon substrate, and 2 is silicide, and 3 is shallow junction, and 4 is foreign atom, and 5 is metal level.

Embodiment

Implementation step of the present invention is as follows:

1, with the hydrofluoric acid cleaning silicon wafer surface of dilution, the method by PVD forms the required metal of silicide in the deposit of silicon chip surface full wafer, as Co (cobalt)/Ti (titanium).

2, serve as to inject mask with metal level such as Co/Ti, finish the injection of source/drain junction and grid dosage, the peak value that makes impurity concentration is just in time below surface of silicon, as 5nm.

3, adopt the method for rapid thermal annealing,,, form high-resistance silicide, as CoSi as 550 ℃ at lower temperature.

4,,, eroded as Co or Ti metal with unwanted and unreacted metal.

5, (modes such as use SPIKE annealing or IMPULSE annealing) form low-resistance silicide by the rapid thermal annealing of higher temperature (950-1000C), as CoSi ₂, and finish the formation of impurity activation and knot simultaneously.

Claims

1, a kind of method that forms silicide and shallow junction simultaneously, it is characterized in that after surface of silicon PVD deposit forms the required metal level of silicide, inject by ion impurity is injected into below the metal, make impurities concentration distribution peak value 3～10nm below metal, and in heat treatment process subsequently, go on foot quick thermal treatment process by two, finish activation and the formation of also finishing shallow junction when silicide forms.

2, method according to claim 1 is characterized in that concrete steps are as follows:

(1) forms the required metal of silicide by the PVD method in the deposit of surface of silicon full wafer;

(2) be to inject mask with the metal level, finish source/drain junction and grid dosage ion and inject that the peak value that makes impurities concentration distribution is just in time at the following 3-10nm of surface of silicon;

(3) method of employing rapid thermal annealing under lower temperature 500-600 ℃, forms high-resistance silicide;

(4) unwanted and unreacted metal are eroded;

(5) rapid thermal annealing by higher temperature such as 950-1000 ℃ forms low-resistance silicide, and finishes impurity activation simultaneously and shallow junction forms.

3, method according to claim 2 is characterized in that described implanted dopant can be with As or P, and dosage is 1-5 * 10 ¹⁵/ cm ², energy is 50-100keV.

4, method according to claim 1 is characterized in that described implanted dopant can be with B or BF ₂, dosage is 1-5 * 10 ¹⁵/ cm ², energy is 30-50keV.

5, method according to claim 2 is characterized in that high-temperature quick thermal annealing adopts SPIKE annealing or IMPULSE annealing.