CN1190825C - Method for forming shallow junction - Google Patents
Method for forming shallow junction Download PDFInfo
- Publication number
- CN1190825C CN1190825C CN 02112148 CN02112148A CN1190825C CN 1190825 C CN1190825 C CN 1190825C CN 02112148 CN02112148 CN 02112148 CN 02112148 A CN02112148 A CN 02112148A CN 1190825 C CN1190825 C CN 1190825C
- Authority
- CN
- China
- Prior art keywords
- silicide
- shallow junction
- impurity
- annealing
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 43
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 230000004913 activation Effects 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- 238000000137 annealing Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000009826 distribution Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000002360 preparation method Methods 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910019001 CoSi Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007865 diluting Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a method for forming shallow junctions in an integrated circuit manufacturing process. At present, a silicide preparation process which is started after source/drain implantation and anneal activation to form junctions can bring on the problem of no reliability, particularly electrical leakage and influence on the final performance of transistors simultaneously. Silicide is formed first, and then injected with impurities and annealed to junctions in the present invention. The distributed peak value of the injected impurities lies under the silicide to avoid some problems caused by the silicide as a diffusion source. The impurities are injected under the silicide, so the present invention has the characteristics of deep junctions, easy control, high impurity concentration and good repeatability; in addition, a process step that oxide is used as an injection mask is reduced, and the process is simplified.
Description
Technical field
The invention belongs to field of IC technique, be specifically related to a kind of method that forms the drain-source shallow junction.
Background technology
Along with the continuous development of integrated circuit, transistorized minimum feature is constantly dwindled, and the length that present main flow technology 0.18um technology is exactly a finger grid is 0.18 micron.When live width was constantly dwindled, in order to improve transistorized performance, the degree of depth of source/drain junction was also constantly reducing, and the degree of depth of tying under 0.18 μ m technology has only tens nanometer.
The technology of main flow all is after having defined source transistor/drain junction at present, just finishes the high dose injection and the annealing back regrowth silicide that finish.Because the growth of silicide itself can consume a part of silicon, so if silicide process is bad, the interface out-of-flatness of silicide and silicon, perhaps junction depth control bad (shallow excessively), when the source-drain electrode making alive, be easy to cause the generation of electric leakage at the position of interface projection, cause the inefficacy of device.As shown in Figure 1.In this external silicide forming process, the problem that also has impurity to distribute again need be considered silicide process to final Impurity Distribution, just the influence of transistor performance.
It is after silicide forms that method is also arranged, and injects by ion impurity (for example As (arsenic), B (boron)) is injected into silicide, by heating, allows impurity diffuse out from silicide again, and shallow junction is leaked in the formation source.Help solution to cause the irregular problem in interface because of silicide process is bad like this.But here silicide itself is used as a diffuse source, on to the control of Impurity Distribution and process repeatability, all have certain problem, and diffusion technology itself is eliminated in advanced person's manufacturing process.
Summary of the invention
The objective of the invention is to propose a kind of weakness that before the preparation silicide, becomes knot technology of both can having eliminated, can avoid behind the silicide implanted dopant, diffusing into the method for the in-problem formation shallow junction of knot technology again.
The method of the formation shallow junction that the present invention proposes is after forming metal silicide layer on the silicon substrate, injects by ion impurity is injected into below the metal silicide, allows the peak depth of Impurity Distribution just in time be positioned at the following 3-10nm place of metal silicide, sees Fig. 2; By the high-temperature quick thermal annealing activator impurity and carry out certain diffusion, finish the formation of shallow junction then.In heat activation, can ignore the influence of silicide self so to a great extent.Because injection has had certain degree of depth, in heat treatment subsequently, downward diffusion just needn't consider that emphasis is the activation of impurity too much for impurity, so both can improve the concentration of doping, can guarantee the degree of depth of tying again in addition.Comparatively speaking in the technology of present main flow, annealing then will take into account the requirement of the concentration and the degree of depth after injecting.This is because impurity has been injected into certain degree of depth in the present invention, though not resembling in traditional technology impurity has activated and has distributed, but in forming silicide process, the one, the impurity that is heated once again can spread again, the 2nd, it is different that the distribution in silicon is followed in the distribution of impurity in silicide, thereby the problem that distributes again of the impurity that also will consider to eject from silicide.In brief, this method is exactly to form shallow junction again after forming silicide.Another advantage of this method is to have saved oxide as injecting this procedure of mask, directly does mask with silicide.
Concrete operations step of the present invention is as follows:
1, on silicon substrate, form low-resistance silicide earlier, specifically can adopt following method:
(1) with the hydrofluoric acid cleaning silicon wafer surface of diluting;
(2) form the required metal of silicide by the PVD method in the deposit of silicon chip surface full wafer, as Co (cobalt)/Ti (titanium);
(3) adopt the rapid thermal annealing method, form the high resistance silicide down lower temperature such as 500-600 ℃, as CoSi, etc.;
(4),, eroded as Co, Ti etc. with unwanted and unreacted metal;
(5) by the rapid thermal annealing of higher temperature,, form low-resistance silicide, as CoSi as 800-900 ℃
2
2, with low resistance silication thing such as CoSi
2For injecting mask, finish the injection of source/drain junction and grid required dosage, the peak value that makes impurities concentration distribution is 3-10nm below silicide just in time;
3, adopt high-temperature quick thermal annealing (RTP) mode, form shallow junction.
Should be generally 900-1000 ℃ more than 900 ℃ in the annealing temperature after the injection.Can use up-to-date rapid thermal annealing (RTP) mode at present, as SPIKE annealing (instantaneous spike annealing) and IMPULSE annealing (pulse annealing), these annealing way can both guarantee that the electricity of impurity activates and distributed depth.Owing to the time of annealing is very short, can not destroy the quality of silicide simultaneously.The P type injects can use B (boron) or BF
2(boron difluoride), dosage is 10
15/ cm
2-5 * 10
15/ cm
2, energy is at 30-50keV; The N type injects then will use As (arsenic) or P (phosphorus), and dosage is 10
15/ cm
2-5 * 10
15/ cm
2, energy is at 50-100keV.
The present invention has been because the annealing of reinjecting after silicide forms has guaranteed the reliability of shallow junction, and characteristics such as it is easy to control to have a junction depth, ties the doping content height, and the distribution of impurity concentration is more stable.This method also has the characteristics of good reproducibility owing to be to inject the back rapid thermal annealing with respect to the mode of diffusion impurity from silicide.Relative in addition main flow technology has also reduced the oxidation step thing and has done the operation of injecting mask.
Description of drawings
Fig. 1 is that unsmooth interface that silicide forms can cause the diagram of leaking electricity.
Fig. 2 is after this method intermediate ion injects, and the peak value of impurity concentration is in the following diagram of silicide.
Number in the figure: 1 is silicon substrate, and 2 is silicide, and 3 is shallow junction, and 4 is foreign atom.
Embodiment
Implementation step of the present invention is as follows:
1. with the hydrofluoric acid cleaning silicon wafer surface of diluting
2. the method by PVD forms the required metal of silicide in the deposit of silicon chip surface full wafer, as Co (cobalt)/Ti (titanium)
3. adopt the method for rapid thermal annealing,,, form high-resistance silicide, as CoSi as 550 degree at lower temperature
4. with unwanted and unreacted metal,, eroded as Co or Ti metal.
5. by the rapid thermal annealing of higher temperature,, form low-resistance silicide, as CoSi as 850 degree
2
6. be to inject mask with the silicide, as CoSi
2, finish the injection of source/drain junction and grid dosage, the peak value of impurity concentration is just in time below silicide, as about 5nm
7. use modes such as SPIKE annealing or IMPULSE annealing to anneal, form shallow junction.
Make the good reliability of shallow junction by said method, knot doping content height, impurities concentration distribution is more stable.
Claims (4)
1, forms the method for shallow junction in a kind of integrated circuit fabrication process, it is characterized in that, after surface of silicon forms metal silicide, the method of injecting by ion is injected into impurity below the metal silicide, make the impurities concentration distribution peak value be positioned at 3-10nm place under the metal silicide, by high-temperature quick thermal annealing, hot activation forms shallow junction then.
2, the method for formation shallow junction according to claim 1 is characterized in that the impurity that injects adopts As or P, and dosage is 10
15/ cm
2-5 * 10
15/ cm
2, energy is at 50-100keV.
3, the method for formation shallow junction according to claim 1 is characterized in that the impurity that injects can be with B or BF
2, dosage is 10
15/ cm
2-5 * 10
15/ cm
2, energy is at 30-50keV.
4, the method for formation shallow junction according to claim 1, the rapid thermal annealing after it is characterized in that injecting can adopt instantaneous spike annealing or pulse annealing, and annealing temperature is 900-1000 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02112148 CN1190825C (en) | 2002-06-20 | 2002-06-20 | Method for forming shallow junction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02112148 CN1190825C (en) | 2002-06-20 | 2002-06-20 | Method for forming shallow junction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1385880A CN1385880A (en) | 2002-12-18 |
| CN1190825C true CN1190825C (en) | 2005-02-23 |
Family
ID=4741910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02112148 Expired - Fee Related CN1190825C (en) | 2002-06-20 | 2002-06-20 | Method for forming shallow junction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1190825C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9076730B2 (en) * | 2012-12-12 | 2015-07-07 | Fudan University | Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making |
-
2002
- 2002-06-20 CN CN 02112148 patent/CN1190825C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1385880A (en) | 2002-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6444550B1 (en) | Laser tailoring retrograde channel profile in surfaces | |
| CN1720607A (en) | Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers | |
| CN1077723C (en) | Method for forming semiconductor device having shallow junction and low sheet resistance | |
| KR100397370B1 (en) | Method for fabricating a integrated circuit having a shallow junction | |
| KR19980070332A (en) | Method for forming a very shallow junction in a silicon device | |
| CN102938375B (en) | Field effect transistor and forming method thereof | |
| JPS60501927A (en) | Shallow junction semiconductor devices | |
| JPH05145027A (en) | Method of controlling defect formation in manufacture of silicon integrated circuit, method of controlling quality of oxide film and defect formation and method of forming double diffusion integrated circuit device cell and integrated circuit mosfet cell | |
| CN1190825C (en) | Method for forming shallow junction | |
| JP2008510300A (en) | Ultra shallow junction formation method | |
| CN1469442A (en) | Method for forming high voltage junction in semiconductor device | |
| CN104347370A (en) | Method for improving negative bias temperature stability of grid of PMOS device | |
| CN1319127C (en) | Method for semultaneous forming silicide and shallow junction | |
| CN103199107B (en) | Semiconductor device and manufacture method | |
| CN104992966B (en) | A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget | |
| CN112038237B (en) | Manufacturing method of trench MOSFET | |
| CN102446769B (en) | Method used for reducing resistance of polysilicon gate in carbon auxiliary injection technological process | |
| CN106169506B (en) | DDD MOS device structure and its manufacturing method | |
| CN1134051C (en) | Method for generating extended super-shallow source-drain region by combining amorphous pre-injection of Ge with low energy injection | |
| CN102117751B (en) | Method for realizing trench double diffused metal oxide semiconductor (DMOS) with small line width | |
| JPH0677247A (en) | Formation of semiconductor device | |
| CN109671772A (en) | A kind of manufacturing method of power semiconductor and its collecting zone | |
| CN112038236B (en) | Manufacturing method of trench MOSFET | |
| TW200405478A (en) | Method for fabricating semiconductor device | |
| CN102412270A (en) | IGBT (insulated gate bipolar transistor) structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG (GROUP) CO., LTD.; SHANGHAI IC R Free format text: FORMER OWNER: SHANGHAI HUAHONG (GROUP) CO., LTD. Effective date: 20060901 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20060901 Address after: 201203 No. 177 blue wave road, Zhangjiang hi tech park, Shanghai, Pudong New Area Co-patentee after: Shanghai integrated circuit research and Development Center Co., Ltd. Patentee after: Shanghai Huahong (Group) Co., Ltd. Address before: 18, Huaihai Road, Shanghai, No. 200020, building 918 Patentee before: Shanghai Huahong (Group) Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050223 Termination date: 20140620 |
|
| EXPY | Termination of patent right or utility model |