CN102593173A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN102593173A CN102593173A CN2011100205366A CN201110020536A CN102593173A CN 102593173 A CN102593173 A CN 102593173A CN 2011100205366 A CN2011100205366 A CN 2011100205366A CN 201110020536 A CN201110020536 A CN 201110020536A CN 102593173 A CN102593173 A CN 102593173A
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- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 title abstract description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 166
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 82
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 68
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 68
- 150000002500 ions Chemical class 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000002019 doping agent Substances 0.000 claims description 49
- 238000000137 annealing Methods 0.000 claims description 18
- 238000009825 accumulation Methods 0.000 claims description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000004151 rapid thermal annealing Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims description 5
- 229910005883 NiSi Inorganic materials 0.000 claims description 5
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 5
- 239000005864 Sulphur Substances 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 210000004483 pasc Anatomy 0.000 claims description 5
- 239000010953 base metal Substances 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
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- 230000008021 deposition Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011435 rock Substances 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- LMHKOBXLQXJSOU-UHFFFAOYSA-N [Co].[Ni].[Pt] Chemical compound [Co].[Ni].[Pt] LMHKOBXLQXJSOU-UHFFFAOYSA-N 0.000 description 1
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- 230000004888 barrier function Effects 0.000 description 1
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- 238000010894 electron beam technology Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- XIKYYQJBTPYKSG-UHFFFAOYSA-N nickel Chemical compound [Ni].[Ni] XIKYYQJBTPYKSG-UHFFFAOYSA-N 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a novel MOSFET device and a realization method thereof, the novel MOSFET device comprises a silicon-containing substrate, a channel region positioned in the substrate, source and drain regions positioned at two sides of the channel region, a grid structure positioned on the channel region and isolation side walls positioned at two sides of the grid structure, wherein the source and drain regions are provided with nickel-based metal silicide, and the novel MOSFET device is characterized in that: doping ions for inhibiting nickel metal diffusion are arranged in the nickel-based metal silicide; and the interface of the nickel-based metal silicide/the channel region is also provided with an ion-doped gathering region which is positioned below the isolation side wall and does not enter the channel region. The doping ions distributed in the nickel-based metal silicide and gathered at the interface of the nickel-based metal silicide/the channel can prevent the nickel-based metal silicide from transversely growing, so that source-drain punch-through or grid leakage current can be prevented, the reliability of the device is improved, and the yield of the product is further improved.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacturing approach thereof, particularly relate to a kind of New-type CMOS structure and manufacturing approach thereof that is applicable to the cross growth of control nickel based metal silicide.
Background technology
IC integrated level constantly increases needs device size lasting scaled, however electrical work voltage remain unchanged sometimes, make actual MOS device internal electric field intensity constantly increase.High electric field brings a series of integrity problems, makes device performance degeneration.
Parasitic series resistance between the MOSFET source-drain area can make equivalent operating voltage descend.In order to reduce contact resistivity and source-drain series resistance, deep-submicron small size MOSFET is normal adopt highly doped source leak and on source-drain area, cover simultaneously metal silicide particularly the nickel based metal silicide as contact.Be depicted as traditional highly doped source drain MOSFET like accompanying drawing 1; Substrate 10 is marked off a plurality of active areas that wherein include channel region 14 by shallow trench isolation from (STI) 20; The cap rock 60 at grid structure 50 and top thereof is formed on the substrate 10, and grid structure 40 both sides are formed with isolation side walls 70, is formed with source-drain area 30 in the substrate 10 of side wall 70 both sides; Source-drain area is except can be whole highly doped; Also can be part light dope structure (LDD), metal silicide 40 is formed on the source-drain area 30, and metal silicide 40 is generally the nickel based metal silicide.Wherein, substrate 10 can be body silicon, also comprises the silicon-on-insulator (SOI) of silicon substrate 11, oxygen buried layer 12 and thin silicone layer 13, can also be compound semiconductor materials such as SiGe for example.
It should be noted that in Fig. 1 and the subsequent drawings that for the purpose of the signal, the STI 20 between body silicon substrate 10 and the SOI substrate (11,12 and 13) is merely schematic isolation for ease, is not both actual adjacent or contacts.
But this traditional highly doped source drain MOSFET with nickel based metal silicide also comes with some shortcomings.As shown in Figure 2; In its manufacture process; Need earlier stringer metal on the basic structure that comprises grid on substrate, the substrate, gate isolation side wall, be generally nickel based metal, high annealing makes the pasc reaction formation metal silicide in metal and the substrate then.When this high annealing, sheet metal not only directly with substrate in pasc reaction, also walk around the gate isolation side wall that is generally nitride and diffuse laterally in the substrate, the therefore nickel based metal silicide cross growth of formation shown in dotted ellipse among Fig. 3.This cross growth does not occur over just gate isolation side wall below, also possibly occur in the substrate of grid below in the channel region.Accompanying drawing 4A and 4B are the transmission electron microscope profile that the device of nickel based metal silicide cross growth has taken place; Dotted line shown in the accompanying drawing 4A is the nickel based metal silicide of source-drain area; It is thus clear that its almost soon UNICOM be one, the nickel based metal silicide of cross growth for having taken place in accompanying drawing 4B arrow indication.
When device dimensions shrink when the inferior 50nm; The cross growth of this nickel based metal silicide (or claiming laterally to invade) will make that gate leakage current heightens; Device reliability descends, and when substrate is SOI, because the thin silicone layer itself on the oxygen buried layer is just less, causes electrical short thereby make the source leakage to link to each other because of the cross growth of nickel based metal silicide; These all will cause significant problem, make product yield decline cost rise.
In order to address this problem, people adopt double annealing to form the nickel based metal silicide usually.
At first, as shown in Figure 5, plated metal thin layer on basic structure.On the substrate with STI 20 10 (also can be the SOI substrate that comprises thick silicon 11, oxygen buried layer 12 and thin silicone layer 13), form grid 50, cap rock 60, grid curb wall 70 successively, ion injects also annealing and activates and form highly doped source and leak 30.The thin metal layer 80 of deposition Ni or Ni-Pt on whole basic structure.Carry out first process annealing subsequently, annealing temperature is about 300 ℃.
After first process annealing, as shown in Figure 6, with substrate 10 directly nickel based metal thin layer 80 parts that also promptly are arranged in source and drain areas of contact can react with the silicon of substrate and form rich nickel nickel based metal silicide mutually.Under this about 300 ℃ low temperature thermal oxidation, the thin metal layer on the grid curb wall 70 is unlikely walked around isolation side walls and is diffused laterally in the substrate.
Then, as shown in Figure 7, divest unreacted metal thin layer 80.Under about 450 to 500 ℃ temperature, carry out second high annealing, make the nickel based metal silicide of rich nickel phase be converted into and have low resistivity nickel-base metal silicide 40, omit living resistance, improve response device speed so that reduce the source.Can know by accompanying drawing 7; The cross growth of nickel based metal silicide is inhibited owing to adopt the different annealing of two Buwen's degree to a certain extent; But process complexity promotes, and certain nickel based metal silicide cross growth still can take place when second high annealing.
Generally speaking; Unnecessary Ni diffusion in the self-aligned silicide technology on the isolation nitride side wall is very fast; The cross growth of nickel based metal silicide takes place easily, causes gate leakage current increase, device stability reduction and source to be leaked break-through possibly take place, particularly for the SOI device.Therefore, need a kind of manufacturing approach that in making novel semi-conductor device process, can effectively reduce the cross growth of nickel based metal silicide.
Summary of the invention
From the above mentioned, the object of the present invention is to provide the preparation method of a kind of effective minimizing nickel based metal silicide cross growth.
The invention provides a kind of semiconductor device; Comprise siliceous substrate, be arranged in said substrate channel region, be positioned at the source-drain area of said channel region both sides, the isolation side walls that is positioned at the grid structure on the said channel region and is positioned at said grid structure both sides; Have the nickel based metal silicide on the said source-drain area, it is characterized in that: in said nickel based metal silicide, have the dopant ion that can suppress the nickel metal diffusing.
Wherein, the accumulation regions that also has said dopant ion at the interface of said nickel based metal silicide and said channel region, said accumulation regions are positioned at the isolation side walls below and do not get into said channel region, and this dopant ion accumulation regions also can suppress the nickel metal diffusing.
Wherein, said dopant ion can suppress the diffusion of nickel metal, is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur, and the dosage of dopant ion is 1 * 10
13Cm
-2To 8 * 10
15Cm
-2
Wherein, on said source-drain area, formed the nickel based metal silicide.Wherein, said substrate is body silicon or silicon-on-insulator (SOI).
Wherein, said source-drain area is that leak in the highly doped source with LDD structure.
Wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
The present invention also provides a kind of manufacturing approach of semiconductor device, comprising:
On siliceous substrate, form grid structure;
The LDD district is leaked in the formation source after carrying out the source leakage implantation annealing first time, and the substrate that leak between the LDD district in the source becomes channel region;
Form isolation side walls in said grid structure both sides;
High-doped zone is leaked in the formation source after carrying out the source leakage implantation annealing second time;
The dopant ion that can suppress the nickel metal diffusing tilts to be injected in the substrate of isolation side walls below;
Nickel deposited Base Metal layer on said substrate, said grid structure and said isolation side walls;
Rapid thermal annealing, so that the nickel based metal layer of said isolation side walls both sides and the pasc reaction in the said substrate form the nickel based metal silicide, simultaneously, said dopant ion is distributed in the said nickel based metal silicide;
Divest unreacted said nickel based metal layer.
Wherein, during rapid thermal annealing, in the accumulation regions that also forms dopant ion at the interface of said nickel based metal silicide/channel region, said accumulation regions is positioned at said isolation side walls below and does not get into said channel region.
Wherein, said dopant ion is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur, and the dosage of said dopant ion is 1 * 10
13Cm
-2To 8 * 10
15Cm
-2
Wherein, said siliceous substrate is body silicon or silicon-on-insulator (SOI).
Wherein, it is under room temperature or low temperature, to carry out that said dopant ion tilts to inject, and particularly, it is under 0 ℃ to-250 ℃, to carry out that said dopant ion tilts to inject.
Wherein, the inclination of said dopant ion is infused in the dopant ion distributed area that forms pocket-like or halation shape in the substrate below the said isolation side walls, and said dopant ion distributed area does not get into said channel region.Wherein, the silicon in the said dopant ion distributed area the rapid thermal annealing stage by full consumption.
Wherein, said source-drain area is the highly doped source-drain area with LDD structure.
Wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
Novel MOS FET according to the present invention's manufacturing; The accumulation regions that is distributed in the dopant ion that does not still get into grid control lower channel district under the isolation side walls can stop the cross growth of nickel based metal silicide; Therefore break-through or gate leakage current are leaked in the source that can prevent; Thereby the raising device reliability has further improved the product yield.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Fig. 1 has shown the generalized section of the highly doped source drain MOSFET of prior art;
Fig. 2, Fig. 3 have shown the generalized section of the nickel based metal silicide cross growth of prior art;
Fig. 4 A, Fig. 4 B have shown the transmission electron microscope picture of the nickel based metal silicide cross growth of prior art;
Fig. 5 to Fig. 7 has shown that the double annealing method of prior art suppresses the generalized section of nickel based metal silicide cross growth; And
Fig. 8 to Figure 12 has shown according to the present invention, in the traditional heavy-doped source drain MOSFET process of preparation, controls the method for nickel based metal silicide cross growth.
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention, the novel semi-conductor device architecture and the manufacturing approach thereof that can effectively reduce the cross growth of nickel based metal silicide are disclosed.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score or the like can be used for modifying various device architectures.These are modified is not space, order or the hierarchical relationship of hint institute modification device architecture unless stated otherwise.
Fig. 8 to Figure 12 is according to the present invention, in the traditional heavy-doped source drain MOSFET of preparation, and the method for Controlling Source drain region nickel based metal silicide cross growth.
At first, form foundation structure.Be illustrated in figure 8 as the generalized section of foundation structure.Has shallow trench isolation deposition gate dielectric layer 310 on the substrate 100 of (STI) 200; Wherein substrate 100 can be body silicon, silicon-on-insulator (SOI) or other siliceous compound semiconductor substrate; For example SiGe, SiC or the like, and the combination of these materials; Gate dielectric layer 310 can be silica, the silicon oxynitride of low k, also can be high k material, for example hafnium oxide etc.Deposition grid layer 300 on gate dielectric layer 310; The material of grid layer 300 can be polysilicon (poly Si), amorphous silicon (α-Si); Also can be metal or alloy and nitride thereof; For example Al, Ti, Ta, TiN, TaN or the like, in addition when grid layer 300 be particularly silicon dioxide of oxide during as the dummy gate of back grid technique, also can be the lamination or the mixture of these combinations of substances.Sedimentary cover 400 on grid layer 300, and its material is nitride normally, and for example silicon nitride (SiN) is used for the hard mask layer of etching after a while.Adopt photo etched mask etching technics commonly used to form the gate stack structure that overlaps by gate dielectric layer 310, grid layer 300 and cap rock 400.With the gate stack structure is mask, carries out the source and leaks low dosage injection for the first time, and the LDD district is leaked in annealing formation source.Subsequently, deposit insulating barrier and etching on total stay isolation side walls 500 in the both sides of gate stack structure, and the material of isolation side walls 500 can be nitride or nitrogen oxide.With gate stack structure and isolation side walls 500 is mask, carries out the source and leaks high dose injection for the second time, and high-doped zone is leaked in annealing formation source, thereby constitutes the highly doped source-drain area 600 with LDD structure as shown in Figure 8, so that further reduce the source ohmic leakage.Nature also can only carry out a source and leak the ion injection, forms the highly doped source-drain area 600 with LDD structure.
Secondly, carrying out angle-tilt ion injects.As shown in Figure 9; (and be wired to the obtuse angle between source-drain area 600 to the channel region with high inclination-angle; The angle at obtuse angle depends on the position in the dopant ion distributed area that will form, and the distributed area is the closer to channel region, and angle is big more) ion that carries out pocket-like or halation shape injects; The dopant ion that also promptly injects injects the substrate of isolation side walls 500 belows sideling with high inclination-angle, sees from profile to be similar to from the side oblique pocket or to form the halation shape.Dopant ion is the ion that can hinder Ni diffusion, for example any one and the combination thereof of carbon C, nitrogen N, oxygen O, fluorine F or sulphur S, and other anyly can play the ions that suppress the Ni diffusion.The dosage that angle-tilt ion is injected can be 1 * 10
13Cm
-2To 8 * 10
15Cm
-2, implantation temperature can be room temperature or low temperature, and particularly, low temperature is infused under 0 ℃ to-250 ℃ and carries out, and therefore is also referred to as cold injection.It is shown in figure 10 that angle-tilt ion is injected the result who obtains; Be formed with the distributed area 700 of dopant ion in the place that isolation side walls does not protrude in channel region for 500 times, with the shade ellipse representation, particularly; The distributed area 700 of dopant ion is positioned at gate isolation side wall 500 belows; And can not get into channel region, promptly be positioned at grid layer 300 both sides yet, preferably press close to or be positioned at the outside of isolation side walls 500.Look from profile and be similar to the pocket or the halation of isolation side walls below, both sides in the distributed area 700 of this dopant ion, so the angle-tilt ion injection is also referred to as pocket-like or halation shape ion injects.
Subsequently, shown in figure 11, also be nickel deposited Base Metal thin layer 800 on substrate 100, STI 200, gate stack structure and the source-drain area 600 in total.The material of thin metal layer 800 can be nickel (Ni), nickel platinum alloy (Ni-Pt, wherein Pt content is smaller or equal to 8%), nickel cobalt (alloy) (Ni-Co, wherein Co content is smaller or equal to 10%) or nickel platinum cobalt ternary-alloy.
Then, carry out self-aligned silicide technology (SALICIDE) through rapid thermal annealing.Shown in figure 12, (RTP, annealing time are generally 1 microsecond to 100 second, and the energy density of employed laser, ion beam, electron beam or incoherent wideband light source is about 1 to 100J/cm under about 450-550 ℃, to carry out rapid thermal annealing
2), the pasc reaction in the nickel based metal thin layer of deposition 800 and the source-drain area 600 and generate corresponding nickel based metal silicide divests that part of of unreacted nickel based metal thin layer 800, in the source-drain area 600 of substrate 100, stays nickel based metal silicide 900.In rapid thermal annealing process; The silicon area that includes dopant ion is by full consumption, and also promptly, the ion part of the suppressed nickel diffusion in the dopant ion distributed area 700 is distributed in the formed nickel based metal silicide 900; Another part accumulates in nickel based metal silicide 900/ silicon raceway groove at the interface; Thereby form the accumulation regions 910 of dopant ion, the accumulation regions 910 of this dopant ion is arranged in the substrate of isolation side walls 500 belows, but does not get into channel region; Also, preferably press close to or be positioned at the outside of isolation side walls 500 promptly in the both sides of grid structure.The dopant ion and the dopant ion accumulation regions 910 that are distributed in the nickel based metal silicide 900 all can suppress the cross growth of nickel based metal silicide, so the cross growth of nickel based metal silicide can be controlled.Nickel based metal silicide 900 can be NiSi according to thin metal layer 800 materials difference accordingly, NiPtSi, NiCoSi, NiPtCoSi.
Novel MOS FET device architecture according to aforesaid manufacturing approach of the present invention forms is shown in figure 12.Has shallow trench isolation in the substrate 100 from (STI) 200; Be formed with highly doped source-drain area 600 in the active area in the substrate 100 between the STI 200, growth has nickel based metal silicide 900 on the doped source drain region 600; The gate stack structure that forms on the substrate 100 is between source-drain area 500, and gate stack structure comprises gate dielectric layer 310, grid layer 300 and cap rock 400, and the gate stack structure both sides have isolation side walls 500; Channel region is arranged in substrate 100, between the source-drain area 600 of gate stack structure both sides; The accumulation regions that has dopant ion at the interface 910 between the silicon of nickel based metal silicide 900 and highly doped source-drain area 600; The accumulation regions 910 of dopant ion is arranged in the highly doped source-drain area 600 of isolation side walls 500 belows; And not getting into the channel region under the gate stack structure control, also is the outside that isolation side walls 500 is pressed close to or be positioned to the accumulation regions 910 of dopant ion.
Afterwards, similar with traditional MOSFET technology, can deposit and the planarization interlayer dielectric layer, etching forms contact through hole, deposition contact bed course and Metal Contact material.When grid layer 300 is the used dummy gate of back grid technique, after forming interlayer dielectric layer, form contact through hole before, can also first etching removal dummy gate, deposit high k gate dielectric material and metal gate material and planarization subsequently successively.
Novel MOS FET according to the present invention's manufacturing; Be distributed in the nickel based metal silicide and can stop the cross growth of nickel based metal silicide with the dopant ion accumulation regions that accumulates in nickel based metal silicide/silicon channel interface place; Therefore break-through or gate leakage current are leaked in the source that can prevent; Thereby the raising device reliability has further improved the product yield.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (18)
1. semiconductor device, comprise siliceous substrate, be arranged in said substrate channel region,
Be positioned at the source-drain area of said channel region both sides, the isolation side walls that is positioned at the grid structure on the said channel region and is positioned at said grid structure both sides, said source-drain area has the nickel based metal silicide, it is characterized in that:
Has the dopant ion that can suppress the nickel metal diffusing in the said nickel based metal silicide.
2. semiconductor device as claimed in claim 1; Wherein, The accumulation regions that also has said dopant ion at the interface of said nickel based metal silicide and said channel region, the accumulation regions of said dopant ion are positioned at said isolation side walls below and do not get into said channel region.
3. semiconductor device as claimed in claim 1, wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
4. semiconductor device as claimed in claim 1, wherein, said dopant ion is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.
5. semiconductor device as claimed in claim 1, wherein, the dosage of said dopant ion is 1 * 10
13Cm
-2To 8 * 10
15Cm
-2
6. semiconductor device as claimed in claim 1, wherein, said siliceous substrate is body silicon or silicon-on-insulator (SOI).
7. semiconductor device as claimed in claim 1, wherein, said source-drain area is the highly doped source-drain area with LDD structure.
8. the manufacturing approach of a semiconductor device comprises:
On siliceous substrate, form grid structure;
Carry out the source leakage and inject leakage LDD district, after annealing formation source for the first time, the substrate that leak between the LDD district in the source becomes channel region;
Form isolation side walls in said grid structure both sides;
Carry out the source leakage and inject after annealing formation source leakage high-doped zone for the second time;
The dopant ion that can suppress the nickel metal diffusing tilts to be injected in the substrate of isolation side walls below;
Nickel deposited Base Metal layer on said substrate, said grid structure and said isolation side walls;
Rapid thermal annealing, so that the nickel based metal layer of said isolation side walls both sides and the pasc reaction in the said substrate form the nickel based metal silicide, simultaneously, said dopant ion is distributed in the said nickel based metal silicide;
Divest unreacted said nickel based metal layer.
9. the manufacturing approach of semiconductor device as claimed in claim 8; Wherein, During rapid thermal annealing, in the accumulation regions that also forms dopant ion at the interface of said nickel based metal silicide/channel region, the accumulation regions of said dopant ion is positioned at said isolation side walls below and does not get into said channel region.
10. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said dopant ion is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.
11. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, the dosage of said dopant ion is 1 * 10
13Cm
-2To 8 * 10
15Cm
-2
12. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said siliceous substrate is body silicon or silicon-on-insulator (SOI).
13. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said dopant ion tilts to be injected to the room temperature injection or low temperature injects.
14. the manufacturing approach of semiconductor device as claimed in claim 13, wherein, it is under 0 ℃ to-250 ℃, to carry out that said low temperature injects.
15. the manufacturing approach of semiconductor device as claimed in claim 8; Wherein, The inclination of said dopant ion is infused in the dopant ion distributed area that forms pocket-like or halation shape in the substrate below the said isolation side walls, and said dopant ion distributed area does not get into said channel region.
16. the manufacturing approach of semiconductor device as claimed in claim 15, wherein, the silicon in the said dopant ion distributed area the rapid thermal annealing stage by full consumption.
17. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said source-drain area is that leak in the highly doped source with LDD structure.
18. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
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