CN102593173B - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN102593173B CN102593173B CN201110020536.6A CN201110020536A CN102593173B CN 102593173 B CN102593173 B CN 102593173B CN 201110020536 A CN201110020536 A CN 201110020536A CN 102593173 B CN102593173 B CN 102593173B
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Abstract
The invention discloses a kind of Novel MOS FET device and its implementation, comprise siliceous substrate, be arranged in the channel region of substrate, be positioned at both sides, channel region source-drain area, be positioned at the grid structure on channel region and be positioned at the isolation side walls of grid structure both sides, source-drain area has nickel based metal silicide, it is characterized in that: in nickel based metal silicide, have the Doped ions suppressing the diffusion of nickel metal; The interface of nickel based metal silicide/channel region also has the accumulation regions of Doped ions, and accumulation regions to be positioned at below isolation side walls and not to enter channel region.Be distributed in inside nickel based metal silicide and can stop the cross growth of nickel based metal silicide with the Doped ions being gathered in nickel based metal silicide/channel interface place, therefore Punchthrough or gate leakage current can be prevented, thus raising device reliability, further increase product yield.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of the New-type CMOS structure and the manufacture method thereof that are applicable to control the cross growth of nickel based metal silicide.
Background technology
IC integrated level constantly increases needs device size continued scale-down, but electrical work voltage remains unchanged sometimes, and actual MOS device electric field intensity inside high is constantly increased.High electric field brings a series of integrity problem, makes device performance degeneration.
Parasitic series resistance between MOSFET source-drain area can make equivalent operation voltage drop.In order to reduce contact resistivity and source-drain series resistance, deep-submicron small size MOSFET often adopt highly doped source and drain and simultaneously on source-drain area covering metal silicide particularly nickel based metal silicide be used as contact.Be traditional highly doped source drain MOSFET as shown in Figure 1, substrate 10 is marked off the multiple active areas wherein including channel region 14 from (STI) 20 by shallow trench isolation, the cap rock 60 at grid structure 50 and top thereof is formed over the substrate 10, grid structure 40 both sides are formed with isolation side walls 70, source-drain area 30 is formed in the substrate 10 of side wall 70 both sides, source-drain area is except can be overall highly doped, also can be part light-dope structure (LDD), metal silicide 40 is formed on source-drain area 30, and metal silicide 40 is generally nickel based metal silicide.Wherein, substrate 10 can be body silicon, and may also be the silicon-on-insulator (SOI) comprising silicon substrate 11, oxygen buried layer 12 and thin silicone layer 13, can also be the compound semiconductor materials such as such as SiGe.
It should be noted that in Fig. 1 and subsequent drawings, conveniently for the purpose of signal, the STI 20 between body silicon substrate 10 and SOI substrate (11,12 and 13) is only schematic isolation, and not both is actual adjacent or contact.
But this highly doped source drain MOSFET of tradition with nickel based metal silicide also comes with some shortcomings.As shown in Figure 2, in its manufacture process, need first stringer metal in the basic structure comprising the grid on substrate, substrate, gate isolation side wall, be generally nickel based metal, then high annealing makes the pasc reaction in metal and substrate form metal silicide.When this high annealing, the pasc reaction of sheet metal not only directly and in substrate, also walks around the gate isolation side wall being generally nitride and diffuses laterally in substrate, therefore form the nickel based metal silicide cross growth as shown in dotted ellipse in Fig. 3.This cross growth does not occur over just below gate isolation side wall, also may to occur in the substrate below grid in channel region.Accompanying drawing 4A and 4B is the transmission electron microscope profile of the device that there occurs the cross growth of nickel based metal silicide, dotted line shown in accompanying drawing 4A is the nickel based metal silicide of source-drain area, visible its almost soon UNICOM be integrated, accompanying drawing 4B arrow indication is the nickel based metal silicide that cross growth has occurred.
When device dimensions shrink is to sub-50nm, the cross growth (or claiming laterally to invade) of this nickel based metal silicide will make gate leakage current increase, device reliability declines, when substrate is SOI because the thin silicone layer on oxygen buried layer is inherently less, source and drain is made to be connected because of the cross growth of nickel based metal silicide thus to cause electrical short, these all will cause significant problem, make product yield decline cost increase.
In order to address this problem, people adopt double annealing to form nickel based metal silicide usually.
First, as shown in Figure 5, plated metal thin layer in basic structure.The substrate 10 (also can be the SOI substrate comprising thick silicon 11, oxygen buried layer 12 and thin silicone layer 13) with STI 20 forms grid 50, cap rock 60, grid curb wall 70 successively, and ion implantation also annealing activates the highly doped source and drain 30 of formation.Whole basic structure deposits the thin metal layer 80 of Ni or Ni-Pt.Perform the first process annealing subsequently, annealing temperature is about 300 DEG C.
After first process annealing, as shown in Figure 6, nickel based metal thin layer 80 part being also namely arranged in source and drain areas directly contacted with substrate 10 can react with the silicon of substrate and form the nickel based metal silicide of rich nickel phase.Under this low temperature thermal oxidation of about 300 DEG C, the thin metal layer on grid curb wall 70 is unlikely walked around isolation side walls and is diffused laterally in substrate.
Then, as shown in Figure 7, unreacted thin metal layer 80 is divested.At the temperature of about 450 to 500 DEG C, carrying out the second high annealing, making the nickel based metal silicidation transformation of rich nickel phase for having low resistivity nickel-base metal silicide 40, to reduce source and drain dead resistance, improve response device speed.From accompanying drawing 7, the cross growth of nickel based metal silicide is inhibited to a certain extent owing to adopting the different annealing of two Buwen's degree, but process complexity promotes, and certain nickel based metal silicide cross growth still can occur when the second high annealing.
Generally speaking, unnecessary Ni diffusion in self-alignment silicide technology on isolation nitride side wall is very fast, the cross growth of nickel based metal silicide easily occurs, and causes gate leakage current increase, device stability reduces and source and drain break-through may occur, particularly for SOI device.Therefore, a kind of manufacture method that effectively can reduce the cross growth of nickel based metal silicide in manufacture semiconductor device process is needed.
Summary of the invention
From the above mentioned, the object of the present invention is to provide the preparation method of a kind of effective minimizing nickel based metal silicide cross growth.
The invention provides a kind of semiconductor device, comprise siliceous substrate, be arranged in the channel region of described substrate, be positioned at the source-drain area of both sides, described channel region, be positioned at the grid structure on described channel region and be positioned at the isolation side walls of described grid structure both sides, described source-drain area has nickel based metal silicide, it is characterized in that: in described nickel based metal silicide, there is the Doped ions that nickel metal can be suppressed to spread.
Wherein, the interface of described nickel based metal silicide and described channel region also has the accumulation regions of described Doped ions, and described accumulation regions to be positioned at below isolation side walls and not to enter described channel region, and this Doped ions accumulation regions also can suppress nickel metal to spread.
Wherein, described Doped ions can suppress the diffusion of nickel metal, and be any one and combination of carbon, nitrogen, oxygen, fluorine, sulphur, the dosage of Doped ions is 1 × 10
13cm
-2to 8 × 10
15cm
-2.
Wherein, described source-drain area defines nickel based metal silicide.Wherein, described substrate is body silicon or silicon-on-insulator (SOI).
Wherein, described source-drain area is the highly doped source and drain with LDD structure.
Wherein, described nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
Present invention also offers a kind of manufacture method of semiconductor device, comprising:
Siliceous substrate forms grid structure;
Form source and drain LDD district after carrying out source and drain first time implantation annealing, the substrate between source and drain LDD district becomes channel region;
Isolation side walls is formed in described grid structure both sides;
Source and drain high-doped zone is formed after carrying out source and drain second time implantation annealing;
The Doped ions that nickel metal can be suppressed to spread tilts to be injected in the substrate below isolation side walls;
Nickel deposited base metal layer in described substrate, described grid structure and described isolation side walls;
Rapid thermal annealing, to make the pasc reaction in the nickel based metal layer of described isolation side walls both sides and described substrate form nickel based metal silicide, meanwhile, described Doped ions is distributed in described nickel based metal silicide;
Divest unreacted described nickel based metal layer.
Wherein, during rapid thermal annealing, also form the accumulation regions of Doped ions in the interface of described nickel based metal silicide/channel region, described accumulation regions to be positioned at below described isolation side walls and not to enter described channel region.
Wherein, described Doped ions is any one and combination of carbon, nitrogen, oxygen, fluorine, sulphur, and the dosage of described Doped ions is 1 × 10
13cm
-2to 8 × 10
15cm
-2.
Wherein, described siliceous substrate is body silicon or silicon-on-insulator (SOI).
Wherein, described Doped ions inclination injection carries out under room temperature or low temperature, and particularly, described Doped ions inclination injection carries out at 0 DEG C to-250 DEG C.
Wherein, the inclination of described Doped ions is infused in the Doped ions distributed area forming pocket-like or halation shape in the substrate below described isolation side walls, and described Doped ions distributed area does not enter described channel region.Wherein, the silicon in described Doped ions distributed area was totally consumed in the rapid thermal annealing stage.
Wherein, described source-drain area is the highly doped source-drain area with LDD structure.
Wherein, described nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
According to the Novel MOS FET that the present invention manufactures, the accumulation regions still not entering the Doped ions in grid control lower channel district under being distributed in isolation side walls can stop the cross growth of nickel based metal silicide, therefore Punchthrough or gate leakage current can be prevented, thus raising device reliability, further increase product yield.
Object of the present invention, and in these other unlisted objects, met in the scope of the application's independent claims.Embodiments of the invention limit in the independent claim, and specific features limits in dependent claims thereto.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 shows the generalized section of the highly doped source drain MOSFET of prior art;
Fig. 2, Fig. 3 show the generalized section of the nickel based metal silicide cross growth of prior art;
Fig. 4 A, Fig. 4 B show the transmission electron microscope picture of the nickel based metal silicide cross growth of prior art;
Fig. 5 to Fig. 7 shows the generalized section of the double annealing method suppression nickel based metal silicide cross growth of prior art; And
Fig. 8 to Figure 12 shows according to the present invention, in the heavy-doped source drain MOSFET process that preparation is traditional, controls the method for nickel based metal silicide cross growth.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose the semiconductor device structure and manufacture method thereof that effectively can reduce the cross growth of nickel based metal silicide.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture.These modify unless stated otherwise the space of not hint institute modification device architecture, order or hierarchical relationship.
Fig. 8 to Figure 12 is according to the present invention, in the heavy-doped source drain MOSFET that preparation is traditional, controls the method for source-drain area nickel based metal silicide cross growth.
First, basis of formation structure.Be illustrated in figure 8 the generalized section of foundation structure.There is shallow trench isolation from deposition of gate dielectric layer 310 on the substrate 100 of (STI) 200, wherein substrate 100 can be body silicon, silicon-on-insulator (SOI) or other siliceous compound semiconductor substrate, such as SiGe, SiC etc., and the combination of these materials; Gate dielectric layer 310 can be silica, the silicon oxynitride of low k, also can be high-g value, such as hafnium oxide etc.Depositing layers 300 on gate dielectric layer 310, the material of grid layer 300 can be polysilicon (poly Si), amorphous silicon (α-Si), also can be metal or alloy and nitride thereof, such as Al, Ti, Ta, TiN, TaN etc., being even oxide particularly silicon dioxide when grid layer 300 is used as the dummy gate of rear grid technique, also can be lamination or the mixture of these combinations of substances.Sedimentary cover 400 on grid layer 300, its material normally nitride, such as silicon nitride (SiN), for the hard mask layer etched after a while.Conventional photo etched mask etching technics is adopted to form the gate stack structure overlapped by gate dielectric layer 310, grid layer 300 and cap rock 400.Take gate stack structure as mask, carry out source and drain first time low dosage and inject, annealing forms source and drain LDD district.Subsequently, deposit isolated insulation layer over the entire structure and etch, leave isolation side walls 500 in the both sides of gate stack structure, the material of isolation side walls 500 can be nitride or nitrogen oxide.With gate stack structure and isolation side walls 500 for mask, carry out source and drain second time High dose implantation, annealing forms source and drain high-doped zone, thus forms the highly doped source-drain area 600 with LDD structure as shown in Figure 8, to reduce source and drain resistance further.Nature, also can only carry out a source and drain ion implantation, forms the highly doped source-drain area 600 with LDD structure.
Secondly, angle-tilt ion injection is carried out.As shown in Figure 9, (and obtuse angle is wired between source-drain area 600 to channel region with high inclination-angle, the angle at obtuse angle depends on the position in the Doped ions distributed area that will be formed, distributed area is the closer to channel region, angle is larger) carry out the ion implantation of pocket-like or halation shape, also the Doped ions namely injected injects the substrate below isolation side walls 500 sideling with high inclination-angle, is similar to oblique pocket or formation halation shape from the side viewed from profile.Doped ions is the ion that Ni can be hindered to spread, any one and the combination of such as carbon C, nitrogen N, oxygen O, fluorine F or sulphur S, and other anyly can play the ions suppressing Ni diffusion.The dosage that angle-tilt ion is injected can be 1 × 10
13cm
-2to 8 × 10
15cm
-2, implantation temperature can be room temperature or low temperature, and particularly, low temperature carries out at being infused in 0 DEG C to-250 DEG C, therefore also referred to as cold injection.Angle-tilt ion injects the result that obtains as shown in Figure 10, the distributed area 700 of Doped ions is formed in the place that isolation side walls does not protrude from channel region for 500 times, represent with shaded oval, particularly, the distributed area 700 of Doped ions is positioned at below gate isolation side wall 500, and can not channel region be entered, be also namely positioned at grid layer 300 both sides, preferably press close to or be positioned at the outside of isolation side walls 500.Look from profile and be similar to pocket below the isolation side walls of both sides or halation in the distributed area 700 of this Doped ions, therefore angle-tilt ion is injected also referred to as pocket-like or halation shape ion implantation.
Subsequently, as shown in figure 11, in total also i.e. nickel deposited Base Metal thin layer 800 on substrate 100, STI 200, gate stack structure and source-drain area 600.The material of thin metal layer 800 can be nickel (Ni), nickel platinum alloy (Ni-Pt, wherein Pt content is less than or equal to 8%), nickel cobalt (alloy) (Ni-Co, wherein Co content is less than or equal to 10%) or nickel platinum cobalt ternary-alloy.
Then, self-alignment silicide technology (SALICIDE) is performed by rapid thermal annealing.As shown in figure 12, (RTP, annealing time is generally 1 microsecond to 100 second, and the energy density of the laser used, ion beam, electron beam or non-coherent broad band light source is about 1 to 100J/cm at about 450-550 DEG C, to carry out rapid thermal annealing
2), the nickel based metal thin layer 800 of deposition generates corresponding nickel based metal silicide to the pasc reaction in source-drain area 600, divests the part of unreacted nickel based metal thin layer 800, in the source-drain area 600 of substrate 100, leaves nickel based metal silicide 900.In rapid thermal annealing process, the silicon area including Doped ions is totally consumed, also be, an ion part for suppressed nickel diffusion in Doped ions distributed area 700 is distributed in formed nickel based metal silicide 900, another part is gathered in the interface of nickel based metal silicide 900/ silicon raceway groove, thus form the accumulation regions 910 of Doped ions, the accumulation regions 910 of this Doped ions is arranged in the substrate below isolation side walls 500, but do not enter channel region, also namely in the both sides of grid structure, preferably press close to or be positioned at the outside of isolation side walls 500.Be distributed in Doped ions in nickel based metal silicide 900 and Doped ions accumulation regions 910 all can suppress the cross growth of nickel based metal silicide, therefore the cross growth of nickel based metal silicide can be controlled.Nickel based metal silicide 900 can be NiSi, NiPtSi, NiCoSi, NiPtCoSi accordingly according to thin metal layer 800 material difference.
The Novel MOS FET device structure formed according to manufacture method as above of the present invention as shown in figure 12.There is shallow trench isolation from (STI) 200 in substrate 100; Be formed with highly doped source-drain area 600 in active area in substrate 100 between STI 200, on doped source drain region 600, growth has nickel based metal silicide 900; The gate stack structure that substrate 100 is formed is between source-drain area 500, and gate stack structure comprises gate dielectric layer 310, grid layer 300 and cap rock 400, and gate stack structure both sides have isolation side walls 500; Channel region is arranged in substrate 100, between the source-drain area 600 of gate stack structure both sides; Interface between the silicon of nickel based metal silicide 900 and highly doped source-drain area 600 has the accumulation regions 910 of Doped ions, the accumulation regions 910 of Doped ions is arranged in the highly doped source-drain area 600 below isolation side walls 500, and the channel region do not entered under gate stack structure control, also namely the accumulation regions 910 of Doped ions is pressed close to or is positioned at the outside of isolation side walls 500.
Afterwards, similar with traditional MOSFET technique, can deposit and planarization interlayer dielectric layer, etching forms contact through hole, Deposit contact bed course and metallic contact material.When grid layer 300 is rear grid technique dummy gate used, form contact through hole after formation interlayer dielectric layer before, removal dummy gate be can also first etch, high k gate dielectric material and metal gate material deposited subsequently successively and planarization.
According to the Novel MOS FET that the present invention manufactures, be distributed in nickel based metal silicide and can stop the cross growth of nickel based metal silicide with the Doped ions accumulation regions being gathered in nickel based metal Silicide/Si channel interface place, therefore Punchthrough or gate leakage current can be prevented, thus raising device reliability, further increase product yield.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (17)
1. a semiconductor device, comprise siliceous substrate, be arranged in the channel region of described substrate,
Be positioned at both sides, described channel region by substrate adulterate form source-drain area, be positioned at the grid structure on described channel region and be positioned at the isolation side walls of described grid structure both sides, described source-drain area has nickel based metal silicide, it is characterized in that:
In described nickel based metal silicide, there is the Doped ions that nickel metal can be suppressed to spread; The interface of described nickel based metal silicide and described channel region also has the accumulation regions of described Doped ions, the accumulation regions of described Doped ions to be positioned at below described isolation side walls and not to enter described channel region, and the accumulation regions of described Doped ions is pressed close to the outside of described isolation side walls, is in the inner side of isolation side walls.
2. semiconductor device as claimed in claim 1, wherein, described nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
3. semiconductor device as claimed in claim 1, wherein, described Doped ions is any one and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.
4. semiconductor device as claimed in claim 1, wherein, the dosage of described Doped ions is 1 × 10
13cm
-2to 8 × 10
15cm
-2.
5. semiconductor device as claimed in claim 1, wherein, described siliceous substrate is body silicon or silicon-on-insulator (SOI).
6. semiconductor device as claimed in claim 1, wherein, described source-drain area is the highly doped source-drain area with LDD structure.
7. a manufacture method for semiconductor device, comprising:
Siliceous substrate forms grid structure;
Carry out source and drain first time and inject after annealing formation source and drain LDD district, the substrate between source and drain LDD district becomes channel region;
Isolation side walls is formed in described grid structure both sides;
Carry out source and drain second time and inject after annealing formation source and drain high-doped zone;
The Doped ions that nickel metal can be suppressed to spread tilts to be injected in the substrate below isolation side walls, and the distributed area of described Doped ions is only positioned at the below of described isolation side walls;
Nickel deposited base metal layer in described substrate, described grid structure and described isolation side walls;
Rapid thermal annealing, nickel based metal silicide is formed to make the pasc reaction in the nickel based metal layer of described isolation side walls both sides and described substrate, simultaneously, described Doped ions is distributed in described nickel based metal silicide, and described nickel based metal silicide extends across the outside of described isolation side walls towards described channel region;
Divest unreacted described nickel based metal layer.
8. the manufacture method of semiconductor device as claimed in claim 7, wherein, during rapid thermal annealing, also form the accumulation regions of Doped ions in the interface of described nickel based metal silicide/channel region, the accumulation regions of described Doped ions to be positioned at below described isolation side walls and not to enter described channel region.
9. the manufacture method of semiconductor device as claimed in claim 7, wherein, described Doped ions is any one and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.
10. the manufacture method of semiconductor device as claimed in claim 7, wherein, the dosage of described Doped ions is 1 × 10
13cm
-2to 8 × 10
15cm
-2.
The manufacture method of 11. semiconductor device as claimed in claim 7, wherein, described siliceous substrate is body silicon or silicon-on-insulator (SOI).
The manufacture method of 12. semiconductor device as claimed in claim 7, wherein, described Doped ions tilts to be injected to room temperature and injects or low temperature injection.
The manufacture method of 13. semiconductor device as claimed in claim 12, wherein, it is carry out at 0 DEG C to-250 DEG C that described low temperature injects.
The manufacture method of 14. semiconductor device as claimed in claim 7, wherein, the inclination of described Doped ions is infused in the Doped ions distributed area forming pocket-like or halation shape in the substrate below described isolation side walls, and described Doped ions distributed area does not enter described channel region.
The manufacture method of 15. semiconductor device as claimed in claim 14, wherein, the silicon in described Doped ions distributed area was totally consumed in the rapid thermal annealing stage.
The manufacture method of 16. semiconductor device as claimed in claim 7, wherein, described source-drain area is the highly doped source and drain with LDD structure.
The manufacture method of 17. semiconductor device as claimed in claim 7, wherein, described nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.
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| CN105742166A (en) * | 2016-03-29 | 2016-07-06 | 上海华力微电子有限公司 | Method for lowering leakage current of device |
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| US20070001223A1 (en) * | 2005-07-01 | 2007-01-04 | Boyd Diane C | Ultrathin-body schottky contact MOSFET |
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