CN1316569C - 低温的掺杂后活化工艺 - Google Patents

低温的掺杂后活化工艺 Download PDF

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Publication number
CN1316569C
CN1316569C CNB028211650A CN02821165A CN1316569C CN 1316569 C CN1316569 C CN 1316569C CN B028211650 A CNB028211650 A CN B028211650A CN 02821165 A CN02821165 A CN 02821165A CN 1316569 C CN1316569 C CN 1316569C
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China
Prior art keywords
source
drain regions
substrate
drain
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB028211650A
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English (en)
Chinese (zh)
Other versions
CN1575507A (zh
Inventor
B·于
R·B·奥格莱
E·N·佩顿
C·E·塔贝里
奇·相
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
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Publication of CN1575507A publication Critical patent/CN1575507A/zh
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Publication of CN1316569C publication Critical patent/CN1316569C/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
CNB028211650A 2001-10-25 2002-10-11 低温的掺杂后活化工艺 Expired - Lifetime CN1316569C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/983,625 US6902966B2 (en) 2001-10-25 2001-10-25 Low-temperature post-dopant activation process
US09/983,625 2001-10-25

Publications (2)

Publication Number Publication Date
CN1575507A CN1575507A (zh) 2005-02-02
CN1316569C true CN1316569C (zh) 2007-05-16

Family

ID=25530028

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028211650A Expired - Lifetime CN1316569C (zh) 2001-10-25 2002-10-11 低温的掺杂后活化工艺

Country Status (6)

Country Link
US (1) US6902966B2 (enExample)
EP (1) EP1444725A1 (enExample)
JP (1) JP2005523573A (enExample)
KR (1) KR100920262B1 (enExample)
CN (1) CN1316569C (enExample)
WO (1) WO2003036701A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7422968B2 (en) * 2004-07-29 2008-09-09 Texas Instruments Incorporated Method for manufacturing a semiconductor device having silicided regions
US7018888B2 (en) * 2004-07-30 2006-03-28 Texas Instruments Incorporated Method for manufacturing improved sidewall structures for use in semiconductor devices
KR101113533B1 (ko) * 2006-03-08 2012-02-29 어플라이드 머티어리얼스, 인코포레이티드 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법
JP5309454B2 (ja) * 2006-10-11 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US7943512B2 (en) * 2007-12-13 2011-05-17 United Microelectronics Corp. Method for fabricating metal silicide
US7842590B2 (en) * 2008-04-28 2010-11-30 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate including laser annealing
US8922189B2 (en) * 2008-11-18 2014-12-30 Texas Instruments Incorporated Controlled on-time buck PFC
CN102104006A (zh) * 2011-01-17 2011-06-22 复旦大学 一种场效应晶体管的制备方法
CN104025269B (zh) * 2012-11-12 2017-09-08 深圳市柔宇科技有限公司 一种自对准金属氧化物薄膜晶体管器件的制造方法
KR20160058499A (ko) 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937315A (en) * 1997-11-07 1999-08-10 Advanced Micro Devices, Inc. Self-aligned silicide gate technology for advanced submicron MOS devices
US6159856A (en) * 1996-12-26 2000-12-12 Sony Corporation Method of manufacturing a semiconductor device with a silicide layer
US6287925B1 (en) * 2000-02-24 2001-09-11 Advanced Micro Devices, Inc. Formation of highly conductive junctions by rapid thermal anneal and laser thermal process
US6291278B1 (en) * 1999-05-03 2001-09-18 Advanced Micro Devices, Inc. Method of forming transistors with self aligned damascene gate contact

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3504336B2 (ja) * 1994-06-15 2004-03-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6300659B1 (en) * 1994-09-30 2001-10-09 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor and fabrication method for same
JP4130237B2 (ja) * 1995-01-28 2008-08-06 株式会社半導体エネルギー研究所 結晶性珪素膜の作製方法及び半導体装置の作製方法
US5977559A (en) * 1995-09-29 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor having a catalyst element in its active regions
TW317643B (enExample) * 1996-02-23 1997-10-11 Handotai Energy Kenkyusho Kk
US6387803B2 (en) * 1997-01-29 2002-05-14 Ultratech Stepper, Inc. Method for forming a silicide region on a silicon body
US6066547A (en) * 1997-06-20 2000-05-23 Sharp Laboratories Of America, Inc. Thin-film transistor polycrystalline film formation by nickel induced, rapid thermal annealing method
JP4318768B2 (ja) * 1997-07-23 2009-08-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6037204A (en) * 1998-08-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Silicon and arsenic double implanted pre-amorphization process for salicide technology
US6251757B1 (en) * 2000-02-24 2001-06-26 Advanced Micro Devices, Inc. Formation of highly activated shallow abrupt junction by thermal budget engineering
US6274488B1 (en) * 2000-04-12 2001-08-14 Ultratech Stepper, Inc. Method of forming a silicide region in a Si substrate and a device having same
US6420218B1 (en) * 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6365446B1 (en) * 2000-07-03 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process
US6399450B1 (en) * 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
TW509984B (en) * 2000-07-24 2002-11-11 United Microelectronics Corp Manufacture method of metal silicide
US6365476B1 (en) * 2000-10-27 2002-04-02 Ultratech Stepper, Inc. Laser thermal process for fabricating field-effect transistors
US6403434B1 (en) * 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159856A (en) * 1996-12-26 2000-12-12 Sony Corporation Method of manufacturing a semiconductor device with a silicide layer
US5937315A (en) * 1997-11-07 1999-08-10 Advanced Micro Devices, Inc. Self-aligned silicide gate technology for advanced submicron MOS devices
US6291278B1 (en) * 1999-05-03 2001-09-18 Advanced Micro Devices, Inc. Method of forming transistors with self aligned damascene gate contact
US6287925B1 (en) * 2000-02-24 2001-09-11 Advanced Micro Devices, Inc. Formation of highly conductive junctions by rapid thermal anneal and laser thermal process

Also Published As

Publication number Publication date
US20030082880A1 (en) 2003-05-01
CN1575507A (zh) 2005-02-02
WO2003036701A1 (en) 2003-05-01
KR20040047967A (ko) 2004-06-05
KR100920262B1 (ko) 2009-10-05
EP1444725A1 (en) 2004-08-11
JP2005523573A (ja) 2005-08-04
US6902966B2 (en) 2005-06-07

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Granted publication date: 20070516