CN1312957A - 表面具有与集成电路电绝缘的周边区域的集成电路模块和包括该模块的混合连接卡 - Google Patents

表面具有与集成电路电绝缘的周边区域的集成电路模块和包括该模块的混合连接卡 Download PDF

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CN1312957A
CN1312957A CN 99809474 CN99809474A CN1312957A CN 1312957 A CN1312957 A CN 1312957A CN 99809474 CN99809474 CN 99809474 CN 99809474 A CN99809474 A CN 99809474A CN 1312957 A CN1312957 A CN 1312957A
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integrated circuit
bonding pad
basement membrane
cavity
module
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克里斯托弗·弗莱陶特
贝努特·西维诺特
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Schlumberger SA
Axalto SA
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10719—Land grid array [LGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

本发明涉及一种集成电路模块(1),它包括一个基膜(2),基膜的第一表面(2.1)上有一个集成电路(3)和一些内部连接区(4),基膜的第二表面(2.2)上有一些外部连接区(5),所述内部连接区和外部连接区与集成电路相连,所述基膜(2)的第二表面(2.2)上包括至少一个与集成电路(2)电绝缘的周边区域(8),所述周边区域(8)相对于内部连接区(4)中的至少一个连接区延伸。本发明还涉及一种包括这种模块的混合连接卡。

Description

表面具有与集成电路电绝缘的周边区域的集成电路模块和 包括该模块的混合连接卡
本发明涉及一种集成电路模块，以及包括这种模块的混合连接卡。这类模块可以通过卡外连接区的接触连接与一个读出器连接，也可以通过磁性耦合、无线电耦合或光耦合的非接触连接与一个读出器相连。
集成电路模块通常包括一个基膜(film support)，基膜的第一表面上有一个集成电路和一些内部连接区，基膜的第二表面上有一些外部连接区，外部连接区延伸到第二表面的周围，所述内部连接区和外部连接区与集成电路相连。
将这种模块连到一个混合连接卡上，该卡包括一个里面埋一天线的卡体。将该集成电路模块粘到卡体的一个空腔内，使得内部连接区垂直于天线端子延伸。内部连接区通过导电胶固定到天线端子上，所述导电胶装在卡体内的一些沿垂直于天线端子延伸的孔中，这些孔到达所述空腔。
在将导电胶填入卡体孔中以后，通过将模块压到空腔中就可以使模块在卡体空腔中得到定位。为了使导电胶和内部连接区之间有足够的接触，从而使内部连接区和天线端子之间具有良好的电连接，通常要填放大量的导电胶，这样会使胶溢出孔。因此，在粘结时，因为对模块施加压力，所以多出的胶会挤出空腔，这些胶又进入空腔边缘和基膜边缘之间。因而导电胶就会在内部连接区和外部连接区之间引起短路连接，使卡报废。
本发明的目的旨在提供一种可以在模块粘结时防止形成这种短路连接的设备。
为了实现上述目的，本发明提供的集成电路模块包括一个基膜，基膜的第一表面上有一个集成电路和一些内部连接区，基膜的第二表面上有一些外部连接区，所述内部连接区和外部连接区与集成电路相连，所述基膜第二表面上包括至少一个与集成电路电绝缘的周边区域，该周边区域相对于内部连接区中的至少一个连接区延伸。
这样，当将模块固定到卡体中的集成电路上时，即使导电胶又进入空腔边缘和基膜边缘之间，胶也只会到达与集成电路绝缘的基膜第二表面中的一个周边区。因而限制了短路现象的出现。
最好所述周边区有一个金属层，其厚度与外部连接区的相同。
通常通过在基膜第二表面上涂敷一个导电胶片，用酸对该胶片进行腐蚀后得到该外部连接区，这样就得到了不同的外部连接区。在这种实施方法中，根据最初的导电胶片切割周边区域。所以该模块的制造很简单，与集成电路电绝缘的周边区域的布置花费的成本也不高。
至少其中一个内部连接区最好具有一个空腔。该空腔可以安放多余的导电胶。
该空腔最好为螺旋形。最好使空腔定好位置，以便使该空腔处于与导电胶接触的内部连接区的周围。这样既可以保证与天线端子保持良好的接触，同时也可以保证得到足够的接受容积来接受多余的导电胶。
本发明还涉及一种包括至少具有上述一种特征的集成电路模块的混合连接卡。
通过下面结合非限定的具体实施方案将会更清楚地理解本发明的其它特征和优点。
描述将结合附图进行，其中：
图1是本发明集成电路模块从外部连接区看到的示意图；
图2是该集成电路模块的示意图；
图3是本发明混合连接卡的横向剖面图。
现在参见附图，本发明的集成电路模块1包括一个基膜2。基膜2的第一表面2.1上有一个集成电路3和两个内部连接区4，基膜的第二表面2.2上有一些外部连接区5。用公知方法通过导体6将集成电路3与所述内部连接区4和外部连接区5相连，集成电路埋在导体6周围的少量树脂7中。
根据本发明，两个由与外部连接区5相同导电胶制成的带子与外部连接区分隔开，这两个带子(bande)在基膜第二表面2.2上延伸。每一个带子8均相对于一个内部连接区4延伸。带子8与外部连接区5分隔开，并与集成电路进行电绝缘。
每一个内部连接区4都有一个螺旋形空腔9。
具体请参见图3，本发明的混合连接卡包括一个里面埋有天线11的卡体。卡体10包括一个用于接受上述模块1的空腔12。
一些孔13与天线11的端子垂直延伸，使其到达空腔12。孔13中含有导电胶14。
用丙烯酸氰型胶(colle 15 de type cyanoacrylate)15将模块1固定到空腔12中，以便模块1的每个内部连接区4的空腔9相对于孔13的孔口延伸。装在孔13中的导电胶14保证使天线11的端子和内部连接区4之间具有良好的电连接。
可以理解的是，带子8形成了内部连接区5和基膜周围之间的绝缘区，从而几乎不会出现有许多胶进入外部连接区的现象。
此外，将多余的导电胶14装入内部连接区4的空腔9中。因而空腔9可以限制胶的流动，这样就可以防止过多的胶通过毛细作用流入空腔12的边缘和基膜2的边缘之间，从而也就不会到达外部连接区。
当然，本发明并不限于上述实施方案，对上述实施方案进行各种变换不超出权利要求书限定的本发明范围。
具体地说，虽然集成电路周围的电绝缘区域是用金属带8表示的，但也可以使该区域中的基膜的第二表面裸露。例如可以使周边区域由一个基本沿第二表面整个周围延伸的裸带构成。
虽然空腔9是用螺旋形表示的，但也可以制成延伸到连接区4外周附近的圆弧形空腔，或所有其它合适形状的空腔。

Claims (8)

1．一种集成电路模块(1)，它包括一个基膜(2)，基膜的第一表面(2.1)上有一个集成电路(3)和一些内部连接区(4)，基膜的第二表面(2.2)上有一些外部连接区(5)，所述内部连接区和外部连接区与集成电路相连，其特征在于所述基膜(2)的第二表面(2.2)上包括至少一个与集成电路(2)电绝缘的周边区域(8)，所述周边区域相对于内部连接区(4)中的至少一个连接区延伸。
2．根据权利要求1所述的集成电路模块，其特征在于所述周边区(8)有一个金属层，其厚度与外部连接区的相同。
3．根据权利要求1或2所述的集成电路模块，其特征在于至少其中一个内部连接区(4)具有空腔(9)。
4．根据权利要求2所述的集成电路模块，其特征在于所述空腔(9)为螺旋形。
5．一种混合连接卡，包括一个卡体(10)，在该卡体中埋有一个天线(11)和一个集成电路模块(1)，该集成电路模块包括一个基膜(2)，基膜的第一表面(2.1)上有一个集成电路(3)和一些内部连接区(4)，基膜的第二表面(2.2)上有一些外部连接区(5)，将集成电路模块设置在卡体的一个空腔(12)中，以便使内部连接区(4)垂直于天线(11)的端子延伸，所述内部连接区(4)通过装在孔(13)中的导电胶(14)与天线(11)的端子连接，所述孔(13)在卡体内部连接区(4)和天线(11)端子之间延伸，其特征在于所述基膜(2)第二表面(2.2)上包括至少一个与集成电路电绝缘的周边区域(8)，所述周边区域相对于内部连接区(4)中的至少一个连接区延伸。
6．根据权利要求5所述的混合连接卡，其特征在于所述周边区(8)有一个金属层，其厚度与外部连接区(5)的相同。
7．根据权利要求5或6所述的混合连接卡，其特征在于至少其中一个内部连接区(4)具有用于接受过量导电胶(14)的空腔(9)。
8．根据权利要求7所述的混合连接卡，其特征在于所述空腔(9)为相对于对应的孔(13)延伸的螺旋形，该孔用于接受导电胶(14)。
CN 99809474 1998-06-23 1999-06-16 表面具有与集成电路电绝缘的周边区域的集成电路模块和包括该模块的混合连接卡 Pending CN1312957A (zh)

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Application Number Priority Date Filing Date Title
FR9807912A FR2780201B1 (fr) 1998-06-23 1998-06-23 Module a circuit integre ayant une face comportant une zone peripherique isolee electriquement du circuit integre, et carte a connexion mixte comportant un tel module
FR98/07912 1998-06-23

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CN1312957A true CN1312957A (zh) 2001-09-12

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EP (1) EP1099254A1 (zh)
JP (1) JP2002519849A (zh)
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AU (1) AU4268999A (zh)
FR (1) FR2780201B1 (zh)
WO (1) WO1999067822A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934676A (zh) * 2015-06-23 2015-09-23 西安空间无线电技术研究所 一种毫米波频段波导-微带过渡结构的实现方法

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Publication number Priority date Publication date Assignee Title
JP5403903B2 (ja) 2007-12-04 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置、その製造方法、および当該半導体装置を用いた信号送受信方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2505091A1 (fr) * 1981-04-30 1982-11-05 Cii Honeywell Bull Dispositif de protection des circuits electroniques tels que des circuits integres a l'encontre des charges electrostatiques
US4483067A (en) * 1981-09-11 1984-11-20 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, for example, by this method
FR2664076A1 (fr) * 1990-03-28 1992-01-03 Schlumberger Ind Sa Procede de fabrication d'une carte a memoire electronique.
FR2716281B1 (fr) * 1994-02-14 1996-05-03 Gemplus Card Int Procédé de fabrication d'une carte sans contact.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934676A (zh) * 2015-06-23 2015-09-23 西安空间无线电技术研究所 一种毫米波频段波导-微带过渡结构的实现方法
CN104934676B (zh) * 2015-06-23 2018-03-09 西安空间无线电技术研究所 一种毫米波频段波导‑微带过渡结构的实现方法

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FR2780201B1 (fr) 2001-09-21
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AU4268999A (en) 2000-01-10
FR2780201A1 (fr) 1999-12-24

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