CN1309032C - Structure and making method of thin film transistor - Google Patents
Structure and making method of thin film transistor Download PDFInfo
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- CN1309032C CN1309032C CNB2004100066217A CN200410006621A CN1309032C CN 1309032 C CN1309032 C CN 1309032C CN B2004100066217 A CNB2004100066217 A CN B2004100066217A CN 200410006621 A CN200410006621 A CN 200410006621A CN 1309032 C CN1309032 C CN 1309032C
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- 239000010409 thin film Substances 0.000 title claims description 48
- 238000000034 method Methods 0.000 title abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 16
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 claims description 7
- 230000008025 crystallization Effects 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 3
- 238000012986 modification Methods 0.000 claims description 3
- 229910052754 neon Inorganic materials 0.000 claims description 3
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 238000005984 hydrogenation reaction Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The present invention discloses a structure of a film transistor and a manufacturing method thereof. The method comprises the following steps: firstly, a substrate is provided, wherein a grid electrode is formed on the substrate, and a grid electrode dielectric layer covers the grid electrode and the substrate; secondly, an ion injection step is carried out to the grid electrode dielectric layer; finally, a semiconductor layer is formed on the grid electrode dielectric layer after injection.
Description
Technical field
The present invention is relevant for a kind of thin-film transistor (thin-film transistor; TFT) structure and manufacture method particularly are the thin-film transistor structure and the manufacture method of microstructure (microcrystalline) about a kind of active region.
Background technology
Thin-film transistor is a LCD active element (active element) commonly used, use by thin-film transistor, make during the data of image write (address period), make the semiconductor layer of thin-film transistor become low resistance state (ON state), image data (image data) is passed on the angle that writes in the electric capacity and then change liquid crystal; And during keeping (sustain period), can make semiconductor layer become high resistance state (OFF state), and image data stored on this electric capacity is kept certain.
The common thin-film transistor structure that is applied to film transistor plane indicator as shown in Figure 1, its manufacturing process is as described below.On substrate 10, have a transistor area, in transistor area, form the first metal layer, utilize the first road photoengraving carving technology the first metal layer to be defined as the gate line 12 of landscape configuration.It is then square thereon that depositing insulating layer 14, semiconductor layer (are often referred to amorphous silicon layer in regular turn, amorphous silicon layer) 16, the n type doped silicon layer 18 and second metal level 20, and carry out the second road photoengraving carving technology, the pattern of amorphous silicon layer 16, n type doped silicon layer 18 and second metal level 20 in the definition transistor, until the surface that exposes insulating barrier 14, and outside transistor area, make second metal level 20 ad-hoc location on substrate 10 form the holding wire (not shown) of vertical configuration.Then, carry out the 3rd road photoengraving carving technology, in transistor area, will define a raceway groove (channel) 19 in second metal level 20 and the n type doped silicon layer 18, and the surface that makes amorphous silicon layer 16 is exposed in the raceway groove 19, uses amorphous silicon layer 16 and second metal level 20 further defined to form source electrode and drain electrode.
For the charge carrier that increases amorphous silicon film transistor translational speed, now developed the thin-film transistor of a kind of silicon (μ c-Si:H) as the active region semiconductor layer with hydrogenation microstructure (hydrogenated microcrystalline) at the active region semiconductor layer.The technology of this kind hydrogenation microstructure has the advantage that easy and existing production line is integrated, and the also more general amorphous silicon of movement of electrons speed is fast in this external its structure.But this kind hydrogenation microstructure technology is because formed silicon layer has bigger and more complete crystalline texture at the top, and also therefore, this kind hydrogenation microstructure technology generally is useful in the thin-film transistor of top grid (top-gate) structure.
The channel region of the thin-film transistor of bottom grid (bottom-gate) structure is the interface of semiconductor layer adjoins gate dielectric layer.And the formed silicon structure of this technology, especially the interface of adjoins gate dielectric layer is a structure near amorphous silicon in the bottom, and is also therefore slower in channel region electronics translational speed, and then influences the usefulness of thin-film transistor.
Summary of the invention
In view of this, in order to address the above problem, the object of the present invention is to provide a kind of method of manufacturing thin film transistor, it carries out an ion implantation technology on the gate dielectric of bottom gate configuration thin-film transistor, the surface state that changes the gate dielectric laminar surface by ion implantation technology is for example: surface energy, molecule arranging structure, or polarity (polarization), form the face that connects of arranging consistent (aligned), also therefore when the semiconductor layer of follow-up formation microstructure, can form at the face that connects of channel region and have neat crystallization arrangement and the bigger semiconductor structure of crystalline particle, and then increase electronics translational speed therein, improve the usefulness of thin-film transistor.
For reaching above-mentioned purpose, the invention provides a kind of method of manufacturing thin film transistor, comprise the following steps: at first, a substrate is provided, wherein be formed with a grid on the substrate, and the grid dielectric layer covers utmost point and a substrate.Next, gate dielectric is carried out an ion implantation step, and form semi-conductor layer on the gate dielectric behind this ion implantation step of experience.
For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor, comprise: a substrate, a gate dielectric are on substrate, wherein gate dielectric has close silicon face, semi-conductor layer is positioned on the gate dielectric, wherein semiconductor layer is nearly crystalloid structure in the part of adjoins gate dielectric layer, and another part is nearly non-crystal structure.
For reaching above-mentioned purpose, the invention provides a kind of method of manufacturing thin film transistor, comprise the following steps: to provide a substrate; Form a grid on this substrate; Form a gate dielectric and cover this grid and this substrate; This gate dielectric is carried out a surface modification step; Form semi-conductor layer on this gate dielectric; Form a doping semiconductor layer on this semiconductor layer and this gate dielectric; Graphical this doping semiconductor layer is to expose for the semiconductor layer on this grid; And form a conductive layer on this doping semiconductor layer.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 shows existing method of manufacturing thin film transistor;
Fig. 2 A～2E shows preferred embodiment of the present invention method of manufacturing thin film transistor;
Fig. 3 A and 3B show the partial enlarged drawing of check gate dielectric surface state method;
Fig. 4 A, Fig. 4 B, Fig. 4 C, Fig. 4 D show the partial enlarged drawing of semiconductor layer of the present invention.
Description of reference numerals
Prior art
Substrate～10; Gate line～12;
Insulating barrier～14; Semiconductor layer～16;
N type doped silicon layer～18; Raceway groove～19;
Metal level～20;
The technology of the present invention:
Substrate～200 grids～202;
Gate dielectric～204; Ion implantation step～206;
Semiconductor layer～208; SiH
3Or SiH
2Molecule～210;
Channel region～212; Doping semiconductor layer～220;
Conductive layer～222; Liquid crystal layer～302;
Strip liquid crystal molecule～304.
Embodiment
Embodiment
At first, shown in Fig. 2 A, with a deposition process, sputtering method for example, form a grid layer on a substrate 200, its substrate 200 is preferably a glass substrate, and its grid layer is preferably a metal level, and it can be made up of tantalum (Ta), tungsten (W), molybdenum (Mo), titanium (Ti), chromium (Cr), aluminium (Al) or its alloy.Afterwards, with general photoengraving carving method, graphical grid layer is to form a grid 202 on substrate 200.
Next, shown in Fig. 2 B, with a deposition process, chemical gaseous phase depositing process (chemicalvapor deposition) for example, form a gate dielectric 204 cover gate 202 and substrate 200, its gate dielectric 204 is preferably selects the group of forming from following molecule: nitrogen oxide and its combination of the oxide of the oxide of the oxide of the oxide of tantalum, the oxide of tungsten, molybdenum, titanyl compound, chromium, the oxide of aluminium, silicon, the nitride of silicon, silicon.
Afterwards, shown in Fig. 2 C, gate dielectric 204 is carried out an ion implantation step 206, to change the surface state on gate dielectric 204 surfaces, for example: surface energy, molecule arranging structure, or polarity (polarization), form the face that connects of arranging consistent (aligned).Its ion implantation step 206 can once single angle inject, or different angles are injected for several times.In brief, it can be changed an angle and carry out ion injection 206 again after a single direction inject.For the element discord gate dielectric 204 that makes injection produces chemical reaction, the atom of its injection is preferably the atom of inert gas, for example: helium, neon, argon, krypton or xenon.These ion implantation step 206 main purposes are the states that change gate dielectric 204 surfaces, and it can use different elements, inject energy, implant angle and doping repeats test, and in after check the state on gate dielectric 206 surfaces.
The method of its check, can be to form a liquid crystal layer 302 on gate dielectric 204, strip liquid crystal molecule 304 by microscopic examination liquid crystal layer 302 is a vertical arrangement, partial enlarged drawing as shown in Figure 3A, or horizontally, partial enlarged drawing shown in Fig. 3 B, whether the surface state of check gate dielectric 204 changes.For example: if strip liquid crystal molecule 304 was a vertical arrangement before its ion injected 206, ion injects 206 back strip liquid crystal molecules 304 and changes into horizontally, can learn the reversing on its gate dielectric 204 surfaces, make the liquid crystal molecule 304 on it change to tendency horizontally from the tendency vertical arrangement.Be noted that at this, the step of its ion injection 206 can be after forming gate dielectric 204, carrying out ion in the settling chamber injects, or behind the external vacuum breaker in settling chamber, carry out ion and inject 206, its purpose is to find the optimum condition of surface state of a gate dielectric 204 to carry out the deposition of follow-up active region semiconductor layer 208.
The person of connecing shown in Fig. 2 D, with a plasma chemical vapor deposition (PECVD) for example, forms semi-conductor layer 208 on gate dielectric 204.Its semiconductor layer 208 can be silicon or germanium, is preferably and feeds silane (SiH in the settling chamber
4) and hydrogen, be that guiding enters the settling chamber and is aided with plasma reaction with Ar, in reative cell with silane (SiH
4) be decomposed into the SiH that has electric charge
3And SiH
2Be deposited on the gate dielectric.In layer more preferably (the layer by layer) mode of piling up forms, to reach the purpose of controlled micro crystallization.Inject 206 steps via above-mentioned ion, change the surface state of gate dielectric 204, make this step form semiconductor 208, in long brilliant process, the SiH of the strip on gate dielectric 204 surfaces
3Or SiH
2Molecule 210, is changed into the major axis tendency and is parallel to gate dielectric 204 surfaces perpendicular to gate dielectric 204 surfaces by script major axis tendency.In brief, the state of gate dielectric laminar surface 204 via the ion implantation step after, tendency attracts SiH
3And SiH
2The silicon atom of molecule 210.
Shown in Fig. 4 A and 4B, in the crystal grain-growth process, if the SiH of gate dielectric laminar surface 204
3And SiH
2Molecule 210 major axis tendency deposits perpendicular to gate dielectric 204 surfaces, as the formed semiconductor layer 208 of inculating crystal layer (seeding layer), can form near non-crystalline structure at the channel region 212 near gate dielectric 204 surfaces.Shown in Fig. 4 C and 4D, the major axis tendency is parallel to the SiH of gate dielectric laminar surface
3And SiH
2Molecule 210 can form than near crystalloid (crystalline) and the big structure of lattice at the channel region 212 near gate dielectric 204 surfaces as the formed semiconductor layer 208 of inculating crystal layer (seeding layer), and electronics rate travel is faster arranged.
Next, shown in Fig. 2 E, dopant deposition semiconductor layer 220 and conductive layer 222 in regular turn in semiconductor layer 208 tops, and carry out the photoengraving carving technology, the pattern of definition doping semiconductor layer 220 and conductive layer 222, and outside transistor area, make conductive layer 222 ad-hoc location on substrate form the holding wire (not shown) of vertical configuration.Then, carry out the photoengraving carving technology, in transistor area, will define a raceway groove 224 (channel) in conductive layer 22 and the doping semiconductor layer 220, so that the surface of semiconductor layer 208 is exposed in the raceway groove 224, use that semiconductor layer 208 and conductive layer 222 are further defined formation source electrode and drain electrode.
The features and advantages of the present invention
The invention is characterized in structure and manufacture method that a kind of thin-film transistor is provided, it carries out an ion implantation technology on the gate dielectric of bottom gate configuration thin-film transistor, change the surface state of gate dielectric laminar surface by ion implantation technology, for example: surface energy, molecule arranging structure, or polarity (polarization), form the face that connects of arranging consistent (aligned), also therefore when the semiconductor layer of follow-up formation microstructure, can form at the face that connects of channel region and have neat crystallization arrangement and the bigger semiconductor structure of crystalline particle, and then increase electronics translational speed therein, the usefulness of promoting thin-film transistor.
Though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is when being as the criterion so that appended claim is determined.
Claims (24)
1. a method of manufacturing thin film transistor comprises the following steps:
One substrate is provided, wherein is formed with a grid on this substrate, and a gate dielectric is on this grid and this substrate;
This gate dielectric is carried out an ion implantation step; And
Form semi-conductor layer on this gate dielectric behind this ion implantation step of experience.
2. method of manufacturing thin film transistor as claimed in claim 1, wherein this gate dielectric is selected the group of forming from following molecule: nitrogen oxide and its combination of the oxide of the oxide of the oxide of the oxide of tantalum, the oxide of tungsten, molybdenum, titanyl compound, chromium, the oxide of aluminium, silicon, the nitride of silicon, silicon.
3. method of manufacturing thin film transistor as claimed in claim 1, wherein this ion implantation step is for to inject with same angle.
4. method of manufacturing thin film transistor as claimed in claim 1, wherein the injection atom of this ion implantation step is the atom of inert gas.
5. method of manufacturing thin film transistor as claimed in claim 4, wherein the atom of this inert gas is selected the group that free following atom is formed: helium, neon, argon, krypton and xenon.
6. method of manufacturing thin film transistor as claimed in claim 1, wherein this semiconductor layer is the structure of controlled micro crystallization.
7. method of manufacturing thin film transistor as claimed in claim 6, wherein the structure of this controlled micro crystallization near this gate dielectric laminar surface is being approaching crystalloid structure, another part is near non-crystalline structure.
8. method of manufacturing thin film transistor as claimed in claim 1, wherein this semiconductor layer is with silane SiH in a reative cell
4Be decomposed into the SiH that has electric charge
3And SiH
2Be deposited on the gate dielectric and form.
9. method of manufacturing thin film transistor as claimed in claim 8, wherein this SiH
3Or SiH
2Molecule is a strip, and the major axis tendency of its strip is parallel to this gate dielectric laminar surface in the deposition process.
10. method of manufacturing thin film transistor as claimed in claim 1, also comprise and form this semiconductor layer of doping semiconductor layer cover part, wherein this semiconductor layer exposes a channel region and is positioned on this grid, and forms a conductive layer on this doping semiconductor layer and this substrate.
11. a method of manufacturing thin film transistor comprises the following steps:
One substrate is provided;
Form a grid on this substrate;
Form a gate dielectric and cover this grid and this substrate;
This gate dielectric is carried out a surface modification step;
Form semi-conductor layer on this gate dielectric;
Form a doping semiconductor layer on this semiconductor layer and this gate dielectric;
Graphical this doping semiconductor layer is to expose for the semiconductor layer on this grid; And
Form a conductive layer on this doping semiconductor layer.
12. method of manufacturing thin film transistor as claimed in claim 11, wherein this substrate is a glass substrate.
13. method of manufacturing thin film transistor as claimed in claim 11, wherein this grid layer is a metal.
14. method of manufacturing thin film transistor as claimed in claim 13, wherein this metal is selected from following group: tantalum, tungsten, molybdenum, titanium, chromium, aluminium and its alloy.
15. method of manufacturing thin film transistor as claimed in claim 11, wherein this gate dielectric is selected the group of forming from following molecule: nitrogen oxide and its combination of the oxide of the oxide of the oxide of the oxide of tantalum, the oxide of tungsten, molybdenum, titanyl compound, chromium, the oxide of aluminium, silicon, the nitride of silicon, silicon.
16. method of manufacturing thin film transistor as claimed in claim 11, wherein this surface modification step is that ion injects this gate dielectric.
17. method of manufacturing thin film transistor as claimed in claim 11, wherein the injection atom of this ion implantation step is the atom of inert gas.
18. method of manufacturing thin film transistor as claimed in claim 17, wherein the atom of this inert gas is selected the group of forming from following atom: helium, neon, argon, krypton and xenon.
19. method of manufacturing thin film transistor as claimed in claim 11, wherein this semiconductor layer is the structure of controlled micro crystallization.
20. method of manufacturing thin film transistor as claimed in claim 19, wherein the structure of this controlled micro crystallization near this gate dielectric laminar surface is being approaching crystalloid structure.
21. method of manufacturing thin film transistor as claimed in claim 11, wherein this semiconductor layer is with silane SiH in a reative cell
4Be decomposed into the SiH that has electric charge
3And SiH
2Be deposited on the gate dielectric and form.
22. method of manufacturing thin film transistor as claimed in claim 21, wherein this SiH
3Or SiH
2Molecule is a strip, and the major axis tendency of its strip is parallel to this gate dielectric laminar surface in the deposition process.
23. a thin-film transistor comprises:
One substrate;
One gate dielectric is on this substrate, and wherein this gate dielectric has close silicon face; And
Semi-conductor layer is positioned on this gate dielectric, and wherein this semiconductor layer is nearly crystalloid structure in the part in abutting connection with this gate dielectric, and another part is nearly non-crystal structure.
24. thin-film transistor as claimed in claim 23, wherein this gate dielectric is selected the group of forming from following molecule: nitrogen oxide and its combination of the oxide of the oxide of the oxide of the oxide of tantalum, the oxide of tungsten, molybdenum, titanyl compound, chromium, the oxide of aluminium, silicon, the nitride of silicon, silicon.
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|---|---|---|---|
| CNB2004100066217A CN1309032C (en) | 2004-02-25 | 2004-02-25 | Structure and making method of thin film transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100066217A CN1309032C (en) | 2004-02-25 | 2004-02-25 | Structure and making method of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1560908A CN1560908A (en) | 2005-01-05 |
| CN1309032C true CN1309032C (en) | 2007-04-04 |
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ID=34439822
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| CNB2004100066217A Expired - Fee Related CN1309032C (en) | 2004-02-25 | 2004-02-25 | Structure and making method of thin film transistor |
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| CN103531639B (en) | 2013-10-22 | 2016-09-07 | 合肥京东方光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte, display device |
| CN104752231B (en) * | 2015-03-27 | 2016-02-24 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method, array base palte and preparation method, display unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834342A (en) * | 1997-06-30 | 1998-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned silicidation of TFT source-drain region |
-
2004
- 2004-02-25 CN CNB2004100066217A patent/CN1309032C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834342A (en) * | 1997-06-30 | 1998-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned silicidation of TFT source-drain region |
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| CN1560908A (en) | 2005-01-05 |
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