CN1308819C - 改值转储随选系统与方法 - Google Patents
改值转储随选系统与方法 Download PDFInfo
- Publication number
- CN1308819C CN1308819C CNB018227910A CN01822791A CN1308819C CN 1308819 C CN1308819 C CN 1308819C CN B018227910 A CNB018227910 A CN B018227910A CN 01822791 A CN01822791 A CN 01822791A CN 1308819 C CN1308819 C CN 1308819C
- Authority
- CN
- China
- Prior art keywords
- simulation
- hardware
- logic
- simulated
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Debugging And Monitoring (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2001/025558 WO2003017099A1 (en) | 2001-08-14 | 2001-08-14 | Vcd-on-demand system and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1491385A CN1491385A (zh) | 2004-04-21 |
CN1308819C true CN1308819C (zh) | 2007-04-04 |
Family
ID=21742775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB018227910A Expired - Fee Related CN1308819C (zh) | 2001-08-14 | 2001-08-14 | 改值转储随选系统与方法 |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1417577A4 (xx) |
JP (1) | JP4102752B2 (xx) |
KR (1) | KR100928134B1 (xx) |
CN (1) | CN1308819C (xx) |
CA (1) | CA2420027C (xx) |
IL (3) | IL160392A0 (xx) |
WO (1) | WO2003017099A1 (xx) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007528553A (ja) * | 2004-03-09 | 2007-10-11 | セヤン ヤン | 検証性能と検証效率性を高める動的検証−基盤方式の検証装置及びこれを用いた検証方法論 |
JP2007305137A (ja) * | 2006-05-12 | 2007-11-22 | Samsung Electronics Co Ltd | 分配された同時的シミュレーション |
US9715325B1 (en) | 2012-06-21 | 2017-07-25 | Open Text Corporation | Activity stream based interaction |
JP5926807B2 (ja) * | 2012-09-06 | 2016-05-25 | 株式会社日立製作所 | 協調シミュレーション用計算機システム、組込みシステムの検証システム及び組込みシステムの検証方法 |
US9208008B2 (en) | 2013-07-24 | 2015-12-08 | Qualcomm Incorporated | Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience |
KR101660580B1 (ko) | 2014-04-02 | 2016-09-28 | 프레스티지 바이오파마 피티이. 엘티디. | 항체의 당 함량 조절을 통한 항체의 제조 방법 |
CN109426518B (zh) * | 2017-08-29 | 2021-02-19 | 杭州旗捷科技有限公司 | 单核处理器设备的并行写码方法、电子设备、存储介质 |
CN109710536B (zh) * | 2018-12-29 | 2022-03-18 | 湖北航天技术研究院总体设计所 | 一种自动提取fpga软件验证结果仿真波形的系统及方法 |
CN109740250B (zh) * | 2018-12-29 | 2022-03-18 | 湖北航天技术研究院总体设计所 | 基于uvm的fpga软件验证结果仿真波形的获取方法和系统 |
CN111125975B (zh) * | 2019-12-09 | 2024-06-14 | 上海思尔芯技术股份有限公司 | 一种fpga时分复用多路数据传输的方法、存储介质及终端 |
CN112486076B (zh) * | 2020-12-08 | 2022-02-15 | 长光卫星技术有限公司 | 一种多fpga间时钟同步与复位同步系统 |
CN113342697B (zh) * | 2021-07-19 | 2022-08-26 | 英韧科技(上海)有限公司 | 闪存转换层仿真测试系统及方法 |
US20240070345A1 (en) * | 2022-08-30 | 2024-02-29 | Rockwell Automation Technologies, Inc. | Parallel emulation for controls testing |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6083269A (en) * | 1997-08-19 | 2000-07-04 | Lsi Logic Corporation | Digital integrated circuit design system and methodology with hardware |
US6161283A (en) * | 1997-06-30 | 2000-12-19 | Sumitomo Wiring Systems, Ldt. | Connector for circuit board and method for producing a connector |
US6249891B1 (en) * | 1998-07-02 | 2001-06-19 | Advantest Corp. | High speed test pattern evaluation apparatus |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6061283A (en) * | 1998-10-23 | 2000-05-09 | Advantest Corp. | Semiconductor integrated circuit evaluation system |
US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
-
2001
- 2001-08-14 CA CA2420027A patent/CA2420027C/en not_active Expired - Fee Related
- 2001-08-14 IL IL16039201A patent/IL160392A0/xx unknown
- 2001-08-14 WO PCT/US2001/025558 patent/WO2003017099A1/en active Application Filing
- 2001-08-14 KR KR1020037002218A patent/KR100928134B1/ko not_active IP Right Cessation
- 2001-08-14 CN CNB018227910A patent/CN1308819C/zh not_active Expired - Fee Related
- 2001-08-14 EP EP01965946A patent/EP1417577A4/en not_active Withdrawn
- 2001-08-14 JP JP2003521942A patent/JP4102752B2/ja not_active Expired - Fee Related
- 2001-08-14 IL IL15448101A patent/IL154481A0/xx active IP Right Grant
-
2003
- 2003-02-16 IL IL154481A patent/IL154481A/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6161283A (en) * | 1997-06-30 | 2000-12-19 | Sumitomo Wiring Systems, Ldt. | Connector for circuit board and method for producing a connector |
US6083269A (en) * | 1997-08-19 | 2000-07-04 | Lsi Logic Corporation | Digital integrated circuit design system and methodology with hardware |
US6249891B1 (en) * | 1998-07-02 | 2001-06-19 | Advantest Corp. | High speed test pattern evaluation apparatus |
Also Published As
Publication number | Publication date |
---|---|
EP1417577A4 (en) | 2009-08-26 |
JP2005500618A (ja) | 2005-01-06 |
KR100928134B1 (ko) | 2009-11-25 |
JP4102752B2 (ja) | 2008-06-18 |
CN1491385A (zh) | 2004-04-21 |
IL154481A (en) | 2008-03-20 |
IL154481A0 (en) | 2003-09-17 |
CA2420027C (en) | 2012-01-03 |
CA2420027A1 (en) | 2003-02-27 |
KR20040028598A (ko) | 2004-04-03 |
EP1417577A1 (en) | 2004-05-12 |
WO2003017099A1 (en) | 2003-02-27 |
IL160392A0 (en) | 2004-07-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1491394A (zh) | 时序不灵敏及无假信号逻辑系统和方法 | |
Gajski et al. | Specification and design of embedded hardware-software systems | |
CN1308819C (zh) | 改值转储随选系统与方法 | |
Raghunathan et al. | High-level power analysis and optimization | |
Martin et al. | ESL design and verification: a prescription for electronic system level methodology | |
Khailany et al. | A modular digital VLSI flow for high-productivity SoC design | |
Thomas et al. | Industrial uses of the system architect’s workbench | |
Bell et al. | Computer Engineering: A DEC View of Hardware Systems Design | |
Erbas et al. | A framework for system-level modeling and simulation of embedded systems architectures | |
EP1349092A2 (en) | A hardware acceleration system for logic simulation | |
US8977994B1 (en) | Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints | |
CN1885295A (zh) | 使用逻辑单元建置集成电路 | |
KR20040023699A (ko) | 동작 프로세서 시스템 및 방법 | |
Bouden-Romdhane et al. | Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis | |
Jia et al. | A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC | |
Cadambi et al. | A fast, inexpensive and scalable hardware acceleration technique for functional simulation | |
Madariaga et al. | Review of electronic design automation tools for high-level synthesis | |
Bergamaschi et al. | A system for production use of high-level synthesis | |
Xiu et al. | Early research experience with OpenAccess Gear: An open source development environment for physical design | |
Ducroux et al. | Fast and accurate power annotated simulation: Application to a many-core architecture | |
Rau et al. | Embedded computing: New directions in architecture and automation | |
Hsiung et al. | Perfecto: A SystemC-based performance evaluation framework for dynamically partially reconfigurable systems | |
Miramond et al. | OveRSoC: a framework for the exploration of RTOS for RSoC platforms | |
Nellans et al. | ASIM-An asynchronous architectural level simulator | |
Chang | VLSI datapath choices: Cell-based versus full-custom |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: CADENCE DESIGN SYSTEMS INC. (US) Free format text: FORMER OWNER: WELYXITE APPEARANCE CO., LTD. Effective date: 20130301 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130301 Address after: American California Patentee after: Cadence Design Systems Inc. (US) Address before: American California Patentee before: Verisity Design Inc. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070404 Termination date: 20140814 |
|
EXPY | Termination of patent right or utility model |