CA2420027A1 - Vcd-on-demand system and method - Google Patents
Vcd-on-demand system and method Download PDFInfo
- Publication number
- CA2420027A1 CA2420027A1 CA002420027A CA2420027A CA2420027A1 CA 2420027 A1 CA2420027 A1 CA 2420027A1 CA 002420027 A CA002420027 A CA 002420027A CA 2420027 A CA2420027 A CA 2420027A CA 2420027 A1 CA2420027 A1 CA 2420027A1
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- CA
- Canada
- Prior art keywords
- simulation
- logic
- simulation time
- vcd
- design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
The disclosed technology is called VCD on demand. In a typical system, the EDA
tool incorporating the VCD on-demand technology has the following high level attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD
file generation, and (3) On-demand software regeneration for a selected simulation target range and design review without simulation rerun. Each of these attributes will be discussed in greater detail below. When the user selects a simulation range (item 105), the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, called the simulation target range (item 135), within the simulation session range for a more focused analysis. The RCC
System dumps the hardware state information (i.e., primary outputs) of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range (item 105) without having to rerun the entire simulation from the very beginning of the simulation session range.
tool incorporating the VCD on-demand technology has the following high level attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD
file generation, and (3) On-demand software regeneration for a selected simulation target range and design review without simulation rerun. Each of these attributes will be discussed in greater detail below. When the user selects a simulation range (item 105), the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, called the simulation target range (item 135), within the simulation session range for a more focused analysis. The RCC
System dumps the hardware state information (i.e., primary outputs) of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range (item 105) without having to rerun the entire simulation from the very beginning of the simulation session range.
Claims (20)
1. A method of creating a value change dump (VCD) file for a modeled design on demand, comprising steps:
selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
generating a VCD file of the modeled design for the selected simulation target range; and accessing the VCD file directly from simulation time t1 to debug the modeled design.
selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
generating a VCD file of the modeled design for the selected simulation target range; and accessing the VCD file directly from simulation time t1 to debug the modeled design.
2. The method of claim 1, further comprising steps:
providing primary inputs to the modeled design for evaluation; and recording a simulation history for the simulation session range.
providing primary inputs to the modeled design for evaluation; and recording a simulation history for the simulation session range.
The method of claim 2, further comprising steps:
processing the simulation history; and evaluating in the modeled design the processed simulation history from simulation time t0 to simulation time t2.
processing the simulation history; and evaluating in the modeled design the processed simulation history from simulation time t0 to simulation time t2.
4. The method of claim 3, wherein the step of generating the VCD file further comprises:
generating evaluated results from the modeled design based on the processed simulation history; and saving the evaluated results during the simulation target range into the VCD
file.
generating evaluated results from the modeled design based on the processed simulation history; and saving the evaluated results during the simulation target range into the VCD
file.
5. The method of claim 4, wherein the step of recording further comprises steps:
compressing the primary inputs; and recording the compressed primary inputs as the simulation history.
compressing the primary inputs; and recording the compressed primary inputs as the simulation history.
The method of claim 4, wherein the processing step further comprises:
decompressing the compressed primary inputs; and providing the decompressed primary inputs as the processed simulation history to the modeled design for evaluation
decompressing the compressed primary inputs; and providing the decompressed primary inputs as the processed simulation history to the modeled design for evaluation
7. The method of claim 4, wherein the recording step includes the step of:
recording the primary inputs as the simulation history.
recording the primary inputs as the simulation history.
8. The method of claim 1, further comprising steps:
saving state information of the modeled design at simulation time t0 in a first file; and saving state information of the modeled design at simulation time t3 in a second file.
saving state information of the modeled design at simulation time t0 in a first file; and saving state information of the modeled design at simulation time t3 in a second file.
9. An electronic design automation system for verifying a user design, comprising:
a computing system including a central processing unit and memory for modeling the user design in software;
an internal bus system coupled to the computing system;
reconfigurable hardware logic coupled to the internal bus system and for modeling at least a portion of the user design in hardware;
control logic coupled to the internal bus system for controlling the delivery of data between the reconfigurable hardware logic and the computing system; and VCD on-demand logic for recording a simulation history for a selected simulation session range and dumping state information from the hardware model into a VCD file for a selected simulation target range, where the simulation target range is within the simulation session range.
a computing system including a central processing unit and memory for modeling the user design in software;
an internal bus system coupled to the computing system;
reconfigurable hardware logic coupled to the internal bus system and for modeling at least a portion of the user design in hardware;
control logic coupled to the internal bus system for controlling the delivery of data between the reconfigurable hardware logic and the computing system; and VCD on-demand logic for recording a simulation history for a selected simulation session range and dumping state information from the hardware model into a VCD file for a selected simulation target range, where the simulation target range is within the simulation session range.
10. The electronic design automation system of claim 9, wherein the VCD on-demand logic further comprises:
first range selection logic for selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
second range selection logic for selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
dump logic for generating a VCD file of the hardware-modeled design for the selected simulation target range;
and access logic for accessing the VCD file directly from simulation time t1 to debug the user design.
first range selection logic for selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
second range selection logic for selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
dump logic for generating a VCD file of the hardware-modeled design for the selected simulation target range;
and access logic for accessing the VCD file directly from simulation time t1 to debug the user design.
11. The electronic design automation system of claim 10, wherein the VCD on-demand logic further comprises:
test bench process for providing primary inputs to the hardware-modeled design for evaluation; and recording logic in the computing system for recording a simulation history for the simulation session range.
test bench process for providing primary inputs to the hardware-modeled design for evaluation; and recording logic in the computing system for recording a simulation history for the simulation session range.
12. The electronic design automation system of claim 11, wherein the VCD on-demand logic further comprises:
process logic in the computing system for processing the simulation history;
and evaluation logic in the reconfigurable hardware logic for evaluating in the hardware-modeled design the processed simulation history from simulation time t0 to simulation time t2.
process logic in the computing system for processing the simulation history;
and evaluation logic in the reconfigurable hardware logic for evaluating in the hardware-modeled design the processed simulation history from simulation time t0 to simulation time t2.
13. The electronic design automation system of claim 12, wherein the dump logic dumps the evaluated results from the hardware-modeled design based on the processed simulation history during the simulation target range into the VCD file.
14. The electronic design automation system of claim 13, wherein the recording logic further comprises:
compression logic for compressing the primary inputs; and write logic for writing the compressed primary inputs as the simulation history.
compression logic for compressing the primary inputs; and write logic for writing the compressed primary inputs as the simulation history.
15. The electronic design automation system of claim 14, wherein the process logic further comprises:
decompression logic for decompressing the compressed primary inputs; and data transfer logic for delivering the decompressed primary inputs as the processed simulation history to the hardware-modeled design for evaluation.
decompression logic for decompressing the compressed primary inputs; and data transfer logic for delivering the decompressed primary inputs as the processed simulation history to the hardware-modeled design for evaluation.
16. The electronic design automation system of claim 13, wherein the recording logic further comprises:
write logic for writing the primary inputs as the simulation history.
write logic for writing the primary inputs as the simulation history.
17. The electronic design automation system of claim 9, further comprising:
state save logic for saving state information of the hardware-modeled design at simulation time t0 in a first file and saving state information of the hardware-modeled design at simulation time t3 in a second file.
state save logic for saving state information of the hardware-modeled design at simulation time t0 in a first file and saving state information of the hardware-modeled design at simulation time t3 in a second file.
18. A VCD on-demand system for providing evaluated information for a selected simulation target range of simulation times, the evaluation occurring in modeled design, comprising:
first logic fox selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
second logic selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
generation logic for generating a VCD file of the evaluated information for the selected simulation target range; and access logic for accessing the VCD file directly from simulation time t1 to debug the modeled design.
first logic fox selecting a simulation session range which begins at a simulation time t0 and ends at a simulation time t3;
second logic selecting a simulation target range which begins at a simulation time t1 and ends at a simulation time t2, wherein the simulation time t1 is greater than or equal to simulation time t0 and simulation time t2 is less than or equal to simulation time t3;
generation logic for generating a VCD file of the evaluated information for the selected simulation target range; and access logic for accessing the VCD file directly from simulation time t1 to debug the modeled design.
19. The VCD on-demand system of claim 18, further comprising:
compression logic for receiving and compressing primary input data for the duration of the simulation session range; and decompression logic for decompressing the compressed primary input data and delivering the decompressed primary input data into the modeled design for evaluation.
compression logic for receiving and compressing primary input data for the duration of the simulation session range; and decompression logic for decompressing the compressed primary input data and delivering the decompressed primary input data into the modeled design for evaluation.
20. The VCD on-demand system of claim 19, wherein the generation logic further comprises:
dump logic for dumping evaluated information to the VCD file, the evaluated information generated by the evaluation of the decompressed primary inputs by the modeled design.
dump logic for dumping evaluated information to the VCD file, the evaluated information generated by the evaluation of the decompressed primary inputs by the modeled design.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2001/025558 WO2003017099A1 (en) | 2001-08-14 | 2001-08-14 | Vcd-on-demand system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2420027A1 true CA2420027A1 (en) | 2003-02-27 |
| CA2420027C CA2420027C (en) | 2012-01-03 |
Family
ID=21742775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2420027A Expired - Fee Related CA2420027C (en) | 2001-08-14 | 2001-08-14 | Vcd-on-demand system and method |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP1417577A4 (en) |
| JP (1) | JP4102752B2 (en) |
| KR (1) | KR100928134B1 (en) |
| CN (1) | CN1308819C (en) |
| CA (1) | CA2420027C (en) |
| IL (3) | IL154481A0 (en) |
| WO (1) | WO2003017099A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005093575A1 (en) * | 2004-03-09 | 2005-10-06 | Seiyang Yang | Dynamic-verification-based verification apparatus achieving high verification performance and verification efficency and the verification methodology using the same |
| JP2007305137A (en) * | 2006-05-12 | 2007-11-22 | Samsung Electronics Co Ltd | Distributed simultaneous simulation |
| WO2014038030A1 (en) * | 2012-09-06 | 2014-03-13 | 株式会社日立製作所 | Co-simulation computer system, verification system for embedded systems, and verification method for embedded systems |
| US9208008B2 (en) | 2013-07-24 | 2015-12-08 | Qualcomm Incorporated | Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience |
| KR101660580B1 (en) | 2014-04-02 | 2016-09-28 | 프레스티지 바이오파마 피티이. 엘티디. | A method for preparing an antibody by controlling a sugar content of the antibody |
| CN109426518B (en) * | 2017-08-29 | 2021-02-19 | 杭州旗捷科技有限公司 | Parallel code writing method of single-core processor device, electronic device and storage medium |
| CN109740250B (en) * | 2018-12-29 | 2022-03-18 | 湖北航天技术研究院总体设计所 | Method and system for acquiring simulation waveform of FPGA software verification result based on UVM |
| CN109710536B (en) * | 2018-12-29 | 2022-03-18 | 湖北航天技术研究院总体设计所 | System and method for automatically extracting simulation waveform of FPGA software verification result |
| CN112486076B (en) * | 2020-12-08 | 2022-02-15 | 长光卫星技术有限公司 | Clock synchronization and reset synchronization system among multiple FPGAs |
| CN113342697B (en) * | 2021-07-19 | 2022-08-26 | 英韧科技(上海)有限公司 | Simulation test system and method for flash translation layer |
| US20240070345A1 (en) * | 2022-08-30 | 2024-02-29 | Rockwell Automation Technologies, Inc. | Parallel emulation for controls testing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
| JP3506202B2 (en) * | 1997-06-30 | 2004-03-15 | 住友電装株式会社 | Board connector |
| US6083269A (en) * | 1997-08-19 | 2000-07-04 | Lsi Logic Corporation | Digital integrated circuit design system and methodology with hardware |
| US6249891B1 (en) * | 1998-07-02 | 2001-06-19 | Advantest Corp. | High speed test pattern evaluation apparatus |
| US6061283A (en) * | 1998-10-23 | 2000-05-09 | Advantest Corp. | Semiconductor integrated circuit evaluation system |
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
-
2001
- 2001-08-14 KR KR1020037002218A patent/KR100928134B1/en not_active IP Right Cessation
- 2001-08-14 IL IL15448101A patent/IL154481A0/en active IP Right Grant
- 2001-08-14 EP EP01965946A patent/EP1417577A4/en not_active Withdrawn
- 2001-08-14 WO PCT/US2001/025558 patent/WO2003017099A1/en active Application Filing
- 2001-08-14 JP JP2003521942A patent/JP4102752B2/en not_active Expired - Fee Related
- 2001-08-14 IL IL16039201A patent/IL160392A0/en unknown
- 2001-08-14 CN CNB018227910A patent/CN1308819C/en not_active Expired - Fee Related
- 2001-08-14 CA CA2420027A patent/CA2420027C/en not_active Expired - Fee Related
-
2003
- 2003-02-16 IL IL154481A patent/IL154481A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005500618A (en) | 2005-01-06 |
| JP4102752B2 (en) | 2008-06-18 |
| IL154481A (en) | 2008-03-20 |
| CN1491385A (en) | 2004-04-21 |
| IL154481A0 (en) | 2003-09-17 |
| EP1417577A4 (en) | 2009-08-26 |
| WO2003017099A1 (en) | 2003-02-27 |
| EP1417577A1 (en) | 2004-05-12 |
| CN1308819C (en) | 2007-04-04 |
| KR20040028598A (en) | 2004-04-03 |
| IL160392A0 (en) | 2004-07-25 |
| CA2420027C (en) | 2012-01-03 |
| KR100928134B1 (en) | 2009-11-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20140814 |