EP1417577A4 - Vcd-on-demand system and method - Google Patents

Vcd-on-demand system and method

Info

Publication number
EP1417577A4
EP1417577A4 EP01965946A EP01965946A EP1417577A4 EP 1417577 A4 EP1417577 A4 EP 1417577A4 EP 01965946 A EP01965946 A EP 01965946A EP 01965946 A EP01965946 A EP 01965946A EP 1417577 A4 EP1417577 A4 EP 1417577A4
Authority
EP
European Patent Office
Prior art keywords
vcd
demand system
demand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01965946A
Other languages
German (de)
French (fr)
Other versions
EP1417577A1 (en
Inventor
Ping-Sheng Tseng
Yogesh Kumar Goel
Quincy Kun-Hsu Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Verisity Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Design Inc filed Critical Verisity Design Inc
Publication of EP1417577A1 publication Critical patent/EP1417577A1/en
Publication of EP1417577A4 publication Critical patent/EP1417577A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Debugging And Monitoring (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
EP01965946A 2001-08-14 2001-08-14 Vcd-on-demand system and method Withdrawn EP1417577A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/025558 WO2003017099A1 (en) 2001-08-14 2001-08-14 Vcd-on-demand system and method

Publications (2)

Publication Number Publication Date
EP1417577A1 EP1417577A1 (en) 2004-05-12
EP1417577A4 true EP1417577A4 (en) 2009-08-26

Family

ID=21742775

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01965946A Withdrawn EP1417577A4 (en) 2001-08-14 2001-08-14 Vcd-on-demand system and method

Country Status (7)

Country Link
EP (1) EP1417577A4 (en)
JP (1) JP4102752B2 (en)
KR (1) KR100928134B1 (en)
CN (1) CN1308819C (en)
CA (1) CA2420027C (en)
IL (3) IL154481A0 (en)
WO (1) WO2003017099A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005093575A1 (en) * 2004-03-09 2005-10-06 Seiyang Yang Dynamic-verification-based verification apparatus achieving high verification performance and verification efficency and the verification methodology using the same
JP2007305137A (en) * 2006-05-12 2007-11-22 Samsung Electronics Co Ltd Distributed simultaneous simulation
JP5926807B2 (en) * 2012-09-06 2016-05-25 株式会社日立製作所 Computer system for co-simulation, verification system for embedded system, and verification method for embedded system
US9208008B2 (en) 2013-07-24 2015-12-08 Qualcomm Incorporated Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience
KR101660580B1 (en) 2014-04-02 2016-09-28 프레스티지 바이오파마 피티이. 엘티디. A method for preparing an antibody by controlling a sugar content of the antibody
CN109426518B (en) * 2017-08-29 2021-02-19 杭州旗捷科技有限公司 Parallel code writing method of single-core processor device, electronic device and storage medium
CN109740250B (en) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 Method and system for acquiring simulation waveform of FPGA software verification result based on UVM
CN109710536B (en) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 System and method for automatically extracting simulation waveform of FPGA software verification result
CN112486076B (en) * 2020-12-08 2022-02-15 长光卫星技术有限公司 Clock synchronization and reset synchronization system among multiple FPGAs
CN113342697B (en) * 2021-07-19 2022-08-26 英韧科技(上海)有限公司 Simulation test system and method for flash translation layer
US20240070345A1 (en) * 2022-08-30 2024-02-29 Rockwell Automation Technologies, Inc. Parallel emulation for controls testing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
DE10053207A1 (en) * 1999-10-28 2001-05-03 Advantest Corp Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3506202B2 (en) * 1997-06-30 2004-03-15 住友電装株式会社 Board connector
US6083269A (en) * 1997-08-19 2000-07-04 Lsi Logic Corporation Digital integrated circuit design system and methodology with hardware
US6249891B1 (en) 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus
US6061283A (en) * 1998-10-23 2000-05-09 Advantest Corp. Semiconductor integrated circuit evaluation system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
DE10053207A1 (en) * 1999-10-28 2001-05-03 Advantest Corp Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO03017099A1 *

Also Published As

Publication number Publication date
KR100928134B1 (en) 2009-11-25
IL154481A (en) 2008-03-20
IL160392A0 (en) 2004-07-25
KR20040028598A (en) 2004-04-03
JP2005500618A (en) 2005-01-06
WO2003017099A1 (en) 2003-02-27
IL154481A0 (en) 2003-09-17
JP4102752B2 (en) 2008-06-18
CA2420027A1 (en) 2003-02-27
EP1417577A1 (en) 2004-05-12
CN1491385A (en) 2004-04-21
CN1308819C (en) 2007-04-04
CA2420027C (en) 2012-01-03

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20030224

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AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: VERISITY DESIGN, INC.

A4 Supplementary search report drawn up and despatched

Effective date: 20090729

17Q First examination report despatched

Effective date: 20100302

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CADENCE DESIGN SYSTEMS, INC.

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Effective date: 20150303