CN1302559C

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Info

Publication number: CN1302559C
Application number: CNB2004100300676A
Authority: CN
Inventors: 圆井干将; 吉村充弘
Original assignee: Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 2003-03-31
Filing date: 2004-03-18
Publication date: 2007-02-28
Anticipated expiration: 2024-03-18
Also published as: JP4731796B2; JP2004303948A; CN1534796A

Abstract

To solve the problem that a pattern becomes nonuniform in a portion in which no electrode is provided on a guard ring provided around an actual operating area, because charge concentration occurs in the vicinity of the guard ring. A MOSFET comprises the actual operating area 5 in which the cells 6 of many MOS transistors are disposed, a source electrode 7 provided on the actual operating area 5 and connected to the source region 18 of each cell 6, and a source pad electrode connected to the source electrode 7. The MOSFET also comprises a gate pad electrode 1 connected to the gate electrode 16 of each cell 6, and the guard ring 22 provided around the source regions 18. In the portion in which the guard ring 22 is not covered with the gate electrodes 16, the source electrode 7 is expanded so that the ring 22 may not be covered with the gate electrodes 16.

Description

Mos field effect transistor

Technical field

The present invention relates to MOSFET, particularly relate to and prevent that the peripheral part pattern is inhomogeneous, the MOSFET of withstand voltage unsettled phenomenon.

Background technology

Be included in general family, electronic equipment is popularized significantly, and therefore Switching Power Supply, is used in nearly all electronic equipment owing to small-sized and low-loss.Thus, the variation of electronic equipment recently becomes increasingly complex to the requirement of power supply, and particularly the singualtion of Switching Power Supply is considered to the final problem of power supply.For the basic skills of the miniaturization of reaching Switching Power Supply comprises: the high frequencyization of switching frequency, loss reduction, product quantity reduce and functionalization.To carry out commercialization practically by these methods, the critical point that must reduce cost by strictness, condition is to should be the mode that is fit to mass production for this reason.

Fig. 5 shows the top figure of existing MOSFET.Power MOSFET comprises: the unit 6 of grid bonding pad electrode 1, grid connection electrode 4, actual act zone 5, MOS transistor, source electrode 7.

Grid bonding pad electrode 1 is connected with gate electrode, is carried out the taking-up of electrode by bonding wire.

Grid connection electrode 4 is connected with the gate electrode of each unit 6, and is configured in the entire circumference in actual act zone 5.

In actual act zone 5, be arranged with the unit 6 of a plurality of MOS transistor that constitute power MOSFET.

Source electrode 7 is set on the actual act zone 5, and is connected with the source region of each unit 6.

Around actual act zone 5, guard ring described later is set, and suppresses the expansion of depletion layer to chip terminal.

Source piece electrode 9 is connected on the source electrode 7, be the acquisition current capacity, and ultrasonic wave press-fits the large diameter bonding wires such as aluminum steel of diameter 150un, carries out the taking-up of electrode.

Fig. 4 shows the cross-section structure of each unit 6 of channel-type.In the power MOSFET of N passage, at N ⁺Be provided with by N on the N-type semiconductor N substrate 11 ^-The drain region 12 that the type epitaxial loayer constitutes, and P type channel layer 13 is set thereon.12 make raceway grooves 14 from channel layer 13 to the drain region, and cover the inwall of raceway grooves 14, the gate electrode 16 that is made of the polysilicon of filling in the raceway groove 14 is set, form each unit 6 by gate oxidation films 15.

Channel layer 13 surfaces at adjacency raceway groove 14 form N ⁺

Type source region

18, and 13 surfaces of the channel layer between the source region 18 of two adjacent unit form P ⁺Type body contact region 19.Further on

channel layer

13,18 form passage area 17 along raceway groove 14 from the source region.Cover by interlayer dielectric 20 on the raceway groove 14, and the source electrode 7 that contacts with source region 18 and body contact region 19 of setting.At the surface protection film 21 that covers whole setting of chip peristome is set, forms grid bonding pad electrode, source piece electrode (not shown).A plurality of said units 6 are arranged on the actual act zone 5 of Fig. 5.Specifically, be a unit by little square expression.

Patent documentation 1: the spy opens the 2002-314079 communique

Improve existing MOS transistor for switching speed, and grid connection electrode 4 is configured in the entire circumference in actual act zone 5.

But as shown in Figure 6, in slight MOS transistor, owing to not too influence switching speed, so only the part is provided with

grid connection electrode

4A, 4B.

As shown in Figure 7, withstand voltage for improving around actual act zone 5, be provided with P ⁺Type guard ring 22.Owing to covering on the guard ring 22, grid bonding pad electrode 1 and

grid connection electrode

4A, 4B be provided with, therefore, and can be because of not being applied to that voltage on grid connection electrode 4A, the 4B makes depletion layer 23 expansions and causing concentrating of electric charge at the edge of guard ring 22.

Owing to do not apply voltage, so depletion layer can not expanded, owing to the depletion layer 23 inhomogeneous charge concentration that cause, so withstand voltage instability, reliability also is affected around the guard ring 22 of not covering

gate connection electrode

4A, 4B but as shown in Figure 8.

Summary of the invention

Mos field effect transistor of the present invention, on the guard ring that around the source region, is provided with electrode is not set, can prevents from nearby to cause charge concentration, can prevent that pattern is inhomogeneous at guard ring, it comprises: the actual act zone, and it arranges a plurality of MOS transistor unit; Source electrode, it is set at this actual act zone, and is connected with the source region of each unit of described MOS transistor; The source piece electrode, it is connected with described source electrode; Guard ring, it is set at around the described actual act zone; The grid connection electrode, it is arranged to cover the part on the described guard ring, and the gate electrode and the grid bonding pad electrode that is arranged on outside the described actual act zone that connect each unit of described MOS transistor, wherein, make the expansion of described source electrode, and cover not the other parts on the described guard ring that is covered by described grid connection electrode by described source electrode.

Description of drawings

Fig. 1 is the plane graph of explanation MOSFET of the present invention;

Fig. 2 is the A-A profile of Fig. 1 of explanation MOSFET of the present invention;

Fig. 3 is the B-B profile of Fig. 1 of explanation MOSFET of the present invention;

Fig. 4 is the profile of the cell mesh of explanation the present invention and existing MOSFET;

Fig. 5 is the plane graph of the existing MOSFET of explanation;

Fig. 6 is the plane graph of another embodiment of the existing MOSFET of explanation;

Fig. 7 is the A-A profile of Fig. 6 of the existing MOSFET of explanation;

Fig. 8 is the B-B profile of Fig. 6 of the existing MOSFET of explanation.

Embodiment

Describe the embodiment of the invention in detail with reference to Fig. 1～Fig. 4.

Fig. 1 is that the plane graph of power MOSFET of the present invention and the part of existing MOSFET same structure are used same-sign.

Power MOSFET comprises: grid bonding pad electrode 1; Grid connection electrode 4, it is connected on the grid bonding pad electrode 1; Actual act zone 5, it arranges a plurality of MOS transistor unit 6; Source electrode 7; Source piece electrode 9, it is connected on the source electrode 7.

In actual act zone 5, arrange a plurality of MOS transistor unit 6 that constitutes power MOSFET.Around actual act zone 5, guard ring 22 is set, suppresses the expansion of depletion layer to chip terminal.

Fig. 4 shows the cross-section structure of the channel-type unit 6 that the present invention uses.At N ⁺Be provided with by N on the N-type semiconductor N substrate 11 ^-The drain region 12 that the type epitaxial loayer constitutes, and P type channel layer 13 is set thereon.Make raceway groove 14 from channel layer 13 until drain region 12, and the inwall of raceway groove 14 is covered by gate oxidation films 15, the gate electrode 16 that is formed by the polysilicon of filling in the raceway groove 14 is set, form each unit 6.

Channel layer 13 surfaces at adjacency raceway groove 14 form N ⁺

Type source region

channel layer

13,18 form passage area 17 along raceway groove 14 from the source region.Cover by interlayer dielectric 20 on the raceway groove 14, and the source electrode 7 that contacts with source region 18 and body contact region 19 of setting.At the surface protection film 21 that covers whole setting of chip peristome is set, forms grid bonding pad electrode and source piece electrode (not shown).A plurality of these unit 6 are arranged on the actual act zone 5 of Fig. 5.Specifically, be a unit by little square expression.

The gate electrode 16 of grid bonding pad electrode 1 and each unit 6 is connected, and utilizes bonding wire to carry out the taking-up of electrode.The size of this grid bonding pad electrode 1 adopts the press fit engagement required enough sizes that go between.

The gate electrode 16 of

grid connection electrode

4A, 4B and each unit 6 is connected and is set on the guard ring 22 of the both sides that are positioned at actual act zone 5.

Source electrode 7 is set on the actual act zone 5, and is connected setting with the source region of each unit 6.

Source piece electrode 9 is identical with grid bonding pad electrode 1, uses 2～3 bonding wires and carries out hot pressing dress etc., carries out the taking-up of electrode.

Bonding wire is the metal fine of Au of diameter 40um etc., and hot pressing is contained on grid bonding pad electrode 1 and the source piece electrode 9 separately.

The invention is characterized in, in the prior art, the grid connection electrode that connects grid bonding pad electrode 1 and gate electrode 16 is set in place on the guard ring 22 of the entire circumference in actual act zone 5, but, in the present invention, only

grid connection electrode

4A, 4B are set in place in the both sides in actual act zone 5 promptly guard ring 22 tops on the both sides of adjacency as shown in the figure.The part that the grid connection electrode is not set that is positioned on the guard ring 22 on every side of actual act zone 5 is passed through expansion source electrode 7, by source electrode 7 coverings of this expansion.

Fig. 2 is the profile of periphery in actual act zone 5 of the grid connection electrode 4A of the MOSFET of being provided with of the present invention.In this part, guard ring 22 tops are covered by grid connection electrode 4A.Thereby the voltage that applies on the grid bonding pad electrode 1 also is applied on grid connection electrode 4A, the 4B, utilizes this voltage depletion layer 23 expansions.Thus, can not cause the concentrating of electric charge of guard ring 22 peripheries, make VDD withstand voltage stable.

Fig. 3 is the figure of periphery in the actual act zone 5 of expression MOSFET of the present invention, is the profile of the part that do not covered by

grid connection electrode

4A, 4B on the guard ring 22.In this part, as previously mentioned, source electrode 7 is enlarged, cover guard ring 22 by source electrode 7.

Thereby identical with Fig. 2, the voltage that is applied to source piece electrode 9 is applied to source electrode 7, makes depletion layer 23 expansions by this voltage, does not nearby produce the inhomogeneous of pattern at guard ring 22, and it is stable that VDSS is withstand voltage, and reliability improves.And the enlarged areas of source electrode 7 can reduce conducting resistance.

Among the MOSFET of the present invention, the part of the not covering gate connection electrode on guard ring makes the source electrode expansion, covers guard ring by source electrode.Therefore, enlarge depletion layer by the voltage that is applied to source electrode, it is inhomogeneous nearby can not to produce pattern at guard ring, and it is stable that VDSS is withstand voltage, and reliability improves.

In addition, owing in the part that the grid connection electrode is not set source electrode is set, the corresponding area that increases source electrode so conducting resistance is reduced, can reduce power consumption.

Claims

1, a kind of mos field effect transistor is characterized in that, comprising: the actual act zone, and it arranges a plurality of MOS transistor unit; Source electrode, it is set at described actual act zone, and is connected with the source region of each unit of described MOS transistor; The source piece electrode, it is connected with described source electrode; Guard ring, it is set at around the described actual act zone; The grid connection electrode, it is arranged to cover the part on the described guard ring, the gate electrode and the grid bonding pad electrode that is arranged on outside the described actual act zone that connect each unit of described MOS transistor, wherein, expand described source electrode, cover not the other parts on the described guard ring that is covered by described grid connection electrode by described source electrode.

2, mos field effect transistor as claimed in claim 1 is characterized in that, described grid connection electrode is located on the guard ring of the both sides that are positioned at the actual act zone that is provided with grid bonding pad electrode.

3, mos field effect transistor as claimed in claim 1 is characterized in that, described MOS transistor is as switch element.