JP2004303948A - Mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a pattern becomes nonuniform in a portion in which no electrode is provided on a guard ring provided around an actual operating area, because charge concentration occurs in the vicinity of the guard ring. <P>SOLUTION: A MOSFET comprises the actual operating area 5 in which the cells 6 of many MOS transistors are disposed, a source electrode 7 provided on the actual operating area 5 and connected to the source region 18 of each cell 6, and a source pad electrode connected to the source electrode 7. The MOSFET also comprises a gate pad electrode 1 connected to the gate electrode 16 of each cell 6, and the guard ring 22 provided around the source regions 18. In the portion in which the guard ring 22 is not covered with the gate electrodes 16, the source electrode 7 is expanded so that the ring 22 may not be covered with the gate electrodes 16. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a MOSFET, and more particularly to a MOSFET in which a pattern is not uniform in a peripheral portion and a breakdown voltage is prevented from becoming unstable.
[0002]
[Prior art]
2. Description of the Related Art Electronic devices including ordinary households have become very popular, and switching power supplies are used in almost all electronic devices because of their small size and low loss. For this reason, the recent diversification of electronic devices has made the requirements for power supplies more and more complicated. In particular, the one-chip switching power supply is considered to be the ultimate task for power supplies. Basic means for achieving a reduction in the size of a switching power supply include a higher switching frequency, a reduction in loss, a reduction in the number of components, and functionalization. In order to actually commercialize the product by these means, it is necessary to go through a strict barrier to cost reduction, which requires a method suitable for mass production.
[0003]
FIG. 5 shows a top view of a conventional MOSFET. The power MOSFET includes a gate pad electrode 1, a gate connection electrode 4, an actual operation area 5, a MOS transistor cell 6, and a source electrode 7.
[0004]
The gate pad electrode 1 is connected to the gate electrode, and the electrode is taken out by a bonding wire.
[0005]
The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is disposed all around the actual operation area 5.
[0006]
In the actual operation area 5, a large number of MOS transistor cells 6 constituting a power MOSFET are arranged therein.
[0007]
The source electrode 7 is provided on the actual operation region 5 and connected to the source region of each cell 6.
[0008]
A guard ring, which will be described later, is provided around the actual operation region 5 to suppress the spread of the depletion layer to the end of the chip.
[0009]
The source pad electrode 9 is connected to the source electrode 7, and in order to increase current capacity, a bonding wire having a large diameter such as an aluminum wire having a diameter of 150 μm is ultrasonically pressed to take out the electrode.
[0010]
FIG. 4 shows a sectional structure of each of the trench type cells 6. In an N-channel power MOSFET, a drain region 12 made of an N ⁻ -type epitaxial layer is provided on an N ⁺ -type semiconductor substrate 11, and a P-type channel layer 13 is provided thereon. A trench 14 extending from the channel layer 13 to the drain region 12 is formed, an inner wall of the trench 14 is covered with a gate oxide film 15, and a gate electrode 16 made of polysilicon filled in the trench 14 is provided to form each cell 6. .
[0011]
An N ⁺ type source region 18 is formed on the surface of the channel layer 13 adjacent to the trench 14, and a P ⁺ type body contact region 19 is formed on the surface of the channel layer 13 between the source regions 18 of two adjacent cells. You. Further, a channel region 17 is formed in the channel layer 13 from the source region 18 along the trench 14. The trench 14 is covered with an interlayer insulating film 20, and a source electrode 7 that contacts the source region 18 and the body contact region 19 is provided. An opening is provided in the surface protection film 21 provided so as to cover the entire surface of the chip, and a gate pad electrode and a source pad electrode (not shown) are formed. Many such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.
[0012]
[Patent Document 1]
JP, 2002-314079, A
[Problems to be solved by the invention]
In the conventional MOS transistor, the gate connection electrode 4 is arranged all around the actual operation area 5 in order to increase the switching speed.
[0014]
However, as shown in FIG. 6, since the pico MOS transistor does not significantly affect the switching speed, the gate connection electrodes 4A and 4B are provided only in part.
[0015]
As shown in FIG. 7, a P ⁺ -type guard ring 22 is provided around the actual operation area 5 to increase the breakdown voltage. Since the gate pad electrode 1 and the gate connection electrodes 4A and 4B are provided so as to cover the guard ring 22, the depletion layer 23 is expanded by the voltage applied to the gate connection electrodes 4A and 4B, and the charge is applied to the edge of the guard ring 22. Concentration does not occur.
[0016]
However, as shown in FIG. 8, since no voltage is applied around the guard ring 22 where the gate connection electrodes 4A and 4B are not covered, the depletion layer does not spread, and the depletion layer 23 becomes non-uniform and the concentration of electric charges occurs. , The breakdown voltage becomes unstable and the reliability is affected.
[0017]
[Means for Solving the Problems]
According to the present invention, when no electrode is provided on the guard ring provided around the source region, charge concentration occurs near the guard ring to prevent the pattern from becoming non-uniform. An actual operating area in which transistor cells are arranged, a source electrode provided on the actual operating area and connected to a source area of each cell of the MOS transistor, a source pad electrode connected to the source electrode, and an actual operating area. And a gate connection electrode provided to partially cover the guard ring and connecting a gate electrode and a gate pad electrode of each cell of the MOS transistor. It is characterized in that the portion of the guard ring that is not covered by the gate electrode is extended and covered by the source electrode.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS.
[0019]
FIG. 1 is a plan view of a power MOSFET of the present invention, and the same components as those of a conventional MOSFET are denoted by the same reference numerals.
[0020]
The power MOSFET includes a gate pad electrode 1, a gate connection electrode 4 connected to the gate pad electrode 1, an actual operation region 5 in which a number of MOS transistor cells 6 are arranged, a source electrode 7, and a source electrode 7. And a source pad electrode 9 connected to the source pad.
[0021]
In the actual operation area 5, a large number of MOS transistor cells 6 constituting a power MOSFET are arranged therein. A guard ring 22 is provided around the actual operation area 5 to prevent the depletion layer from spreading to the end of the chip.
[0022]
FIG. 4 shows a sectional structure of a trench type cell 6 used in the present invention. A drain region 12 made of an N ⁻ type epitaxial layer is provided on an N ⁺ type semiconductor substrate 11, and a P type channel layer 13 is provided thereon. A trench 14 extending from the channel layer 13 to the drain region 12 is formed, an inner wall of the trench 14 is covered with a gate oxide film 15, and a gate electrode 16 made of polysilicon filled in the trench 14 is provided to form each cell 6. .
[0023]
An N ⁺ type source region 18 is formed on the surface of the channel layer 13 adjacent to the trench 14, and a P ⁺ type body contact region 19 is formed on the surface of the channel layer 13 between the source regions 18 of two adjacent cells. You. Further, a channel region 17 is formed in the channel layer 13 from the source region 18 along the trench 14. The trench 14 is covered with an interlayer insulating film 20, and a source electrode 7 that contacts the source region 18 and the body contact region 19 is provided. An opening is provided in the surface protection film 21 provided so as to cover the entire surface of the chip, and a gate pad electrode and a source pad electrode (not shown) are formed. Many such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.
[0024]
The gate pad electrode 1 is connected to the gate electrode 16 of each cell 6, and the electrode is taken out by a bonding wire. The size of the gate pad electrode 1 is set to a size necessary and sufficient for the bonding wire to be crimped.
[0025]
The gate connection electrodes 4A and 4B are connected to the gate electrode 16 of each cell 6 and are provided on guard rings 22 on two sides of the actual operation area 5.
[0026]
The source electrode 7 is provided on the actual operation region 5 and connected to the source region of each cell 6.
[0027]
For the source pad electrode 9, the same bonding wire as that of the gate pad electrode 1 is used and two or three bonding wires are used, and the electrodes are taken out by thermocompression bonding.
[0028]
The bonding wire is a thin metal wire such as Au having a diameter of 40 μm and is thermocompression-bonded to the gate pad electrode 1 and the source pad electrode 9, respectively.
[0029]
A feature of the present invention is that a gate connection electrode connecting the gate pad electrode 1 and the gate electrode 16 is provided on the guard ring 22 around the entire actual operation area 5 in the related art. The electrodes 4A and 4B are provided only on the two sides of the actual operation area 5, that is, on the guard ring 22 on two adjacent sides as shown in the drawing. The portion of the guard ring 22 around the actual operation region 5 where the gate connection electrode is not provided extends the source electrode 7 and is covered by the extended source electrode 7.
[0030]
FIG. 2 is a cross-sectional view of the periphery of the actual operation region 5 provided with the gate connection electrode 4A of the MOSFET of the present invention. In this portion, the upper part of the guard ring 22 is covered with the gate connection electrode 4A. Therefore, the voltage applied to the gate pad electrode 1 is also applied to the gate connection electrodes 4A and 4B, and the depletion layer 23 is expanded by the voltage. Therefore, no charge is collected around the guard ring 22, and the VDD withstand voltage is stabilized.
[0031]
FIG. 3 is a cross-sectional view of the periphery of a portion where the gate connection electrode 4A of the actual operation region 5 of the MOSFET of the present invention is not covered with the gate connection electrode 4 on the guard ring 22. In this portion, as described above, the source electrode 7 is expanded so that the source electrode 7 covers the guard ring 22.
[0032]
Therefore, similarly to FIG. 2, the voltage applied to the source pad electrode 9 is applied to the source electrode 7, and the depletion layer 23 is expanded by the voltage. Reliability is improved. Moreover, the area of the source electrode 7 is increased, and the on-resistance can be reduced.
[0033]
【The invention's effect】
In the MOSFET of the present invention, the source electrode is extended to a portion on the guard ring where the gate connection electrode is not covered, so that the source electrode covers the guard ring. Therefore, the depletion layer is expanded by the voltage applied to the source electrode, the pattern does not become uneven near the guard ring, the VDSS breakdown voltage is stabilized, and the reliability is improved.
[0034]
In addition, since the source electrode is provided in a portion where the gate connection electrode is not provided, the area of the source electrode can be increased accordingly, so that the on-resistance is reduced and the power loss can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a MOSFET of the present invention.
FIG. 2 is a sectional view taken along the line AA of FIG. 1 for explaining the MOSFET of the present invention.
FIG. 3 is a sectional view taken along the line BB of FIG. 1 for explaining the MOSFET of the present invention.
FIG. 4 is a cross-sectional view of a cell portion for explaining the present invention and a conventional MOSFET.
FIG. 5 is a plan view illustrating a conventional MOSFET.
FIG. 6 is a plan view illustrating another embodiment of a conventional MOSFET.
FIG. 7 is a sectional view taken along the line AA of FIG. 6, illustrating a conventional MOSFET.
FIG. 8 is a sectional view taken along the line BB of FIG. 6 illustrating a conventional MOSFET.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Gate pad electrode 4A Gate connection electrode 4B Gate connection electrode 5 Actual operation area 6 Cell 7 Source electrode 16 Gate electrode 22 Guard ring

Claims (3)

An actual operation area in which a large number of MOS transistor cells are arranged;
A source electrode provided on the actual operation region and connected to a source region of each cell of the MOS transistor;
A source pad electrode connected to the source electrode,
A guard ring provided around the actual operation area,
A gate connection electrode provided to partially cover the guard ring and connecting a gate electrode and a gate pad electrode of each cell of the MOS transistor;
A MOSFET, wherein the source electrode is extended so that a portion of the guard ring on which the gate electrode is not covered is covered with the source electrode. 2. The MOSFET according to claim 1, wherein the gate connection electrodes are provided on guard rings on two sides of an actual operation area where a gate pad electrode is provided. 2. The MOSFET according to claim 1, wherein said MOS transistor is used as a switching element.

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