CN1286158C - Method of manufacturing semiconductor device and electronic device - Google Patents

Method of manufacturing semiconductor device and electronic device Download PDF

Info

Publication number
CN1286158C
CN1286158C CNB2004100386304A CN200410038630A CN1286158C CN 1286158 C CN1286158 C CN 1286158C CN B2004100386304 A CNB2004100386304 A CN B2004100386304A CN 200410038630 A CN200410038630 A CN 200410038630A CN 1286158 C CN1286158 C CN 1286158C
Authority
CN
China
Prior art keywords
semiconductor
resin
semiconductor packages
semiconductor chip
carrier substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004100386304A
Other languages
Chinese (zh)
Other versions
CN1542932A (en
Inventor
青栁哲理
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1542932A publication Critical patent/CN1542932A/en
Application granted granted Critical
Publication of CN1286158C publication Critical patent/CN1286158C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Acoustics & Sound (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

To adjust the arranging position of resin between semiconductor packages easily without causing any deterioration in the arrangement precision of the semiconductor packages. Before semiconductor packages PK1 and PK2 are connected electrically through bump electrodes 13, resin 15 is placed on a semiconductor chip 3 such that at least a part of the semiconductor chip 3 is exposed, and then the semiconductor packages PK1 and PK2 are connected electrically through bump electrodes 13 while sustaining the resin 15 arranged on the semiconductor chip 3 in the state of stage A or stage B.

Description

The manufacture method of semiconductor device and the manufacture method of electronic equipment
Technical field
The present invention relates to the manufacture method of semiconductor device and the manufacture method of electronic equipment, be particularly useful for the manufacture method of the stepped construction of semiconductor packages.
Background technology
In the semiconductor packages in the past, for example disclosed as patent documentation 1, by encapsulating across the solder ball stacked semiconductor, the implementation space is saved.Here, potting resin between stacked semiconductor packages.
[patent documentation 1]
The spy opens the 2002-170906 communique
But in the semiconductor packages in the past, potting resin in the whole space between the stacked semiconductor packages of solder ball.Therefore, during the resin of filling between the curing semiconductor encapsulation, the moisture that comprises in the resin can not fully be removed, residual moisture still in the resin of filling between the semiconductor packages.Like this, during backflow when having stacked semiconductor packages secondary installing, the moisture gasification that comprises in the resin of filling between the semiconductor packages and expanding produces the problem of peeling off between the semiconductor packages.
In the semiconductor packages in the past, across solder ball fixedly after the semiconductor packages, potting resin between the semiconductor packages.Therefore, exist under the situation of the narrow gaps between the semiconductor packages, be difficult to be limited to potting resin on the ad-hoc location between the semiconductor packages, resin contacts with solder ball, resin is produced cause thermal damage, maybe can not consider the stress that applies between the semiconductor packages is disposed resin.
On the other hand, across solder ball fixedly before the semiconductor packages with resin fixedly between the semiconductor packages time, semiconductor packages becomes and is unable to stir any more during the backflow of solder ball.Therefore, the alignment certainly of the semiconductor packages that the surface tension when existing owing to the solder ball fusion causes is hindered, and worsens the configuration precision of semiconductor packages.
Therefore, the purpose of this invention is to provide a kind of configuration precision that does not worsen semiconductor packages, can adjust the manufacture method of semiconductor device of allocation position of the resin between the semiconductor packages and the manufacture method of electronic equipment easily.
Summary of the invention
For addressing the above problem, according to the manufacture method of the semiconductor device of a form of the present invention, it is characterized in that comprising: the operation of resin is supplied with at least a portion zone on first semiconductor chip on first semiconductor structure; Under the state of keeping flowability at above-mentioned resin, by making at least a portion of described first semiconductor structure from described resin, expose, second semiconductor package body is connected electrically in operation on above-mentioned first semiconductor structure, between opposed described first semiconductor structure and described second semiconductor package body, has the space.
Thus, after first semiconductor package is loaded onto the configuration resin, can load onto configuration second semiconductor packages at first semiconductor package, and can adjust the allocation position of the resin between first semiconductor packages and second semiconductor packages easily.Like this, under the situation of the narrow gaps between first semiconductor packages and second semiconductor packages, also can avoid soldering tin material and between first semiconductor packages and second semiconductor packages, dispose resin, or the path fled from of the moisture of guaranteeing to be used for resin is comprised, and between first semiconductor packages and second semiconductor packages, resin is set.Its result, the cause thermal damage that suppresses resin, and suppress peeling off between first semiconductor packages and second semiconductor packages, simultaneously can fix first semiconductor packages and second semiconductor packages by enough resins, carry out also can preventing under the situation of reflow treatment the position deviation between first semiconductor packages and second semiconductor packages during secondary installing.
In addition, even before first semiconductor package is loaded onto configuration second semiconductor packages, resin is configured under the situation that first semiconductor package loads onto, when on first semiconductor packages, being electrically connected second semiconductor packages, also can keep the resin flow that is provided with between first semiconductor packages and second semiconductor packages.Therefore, use under the situation of soldering tin material when being electrically connected second semiconductor packages on first semiconductor packages, the alignment certainly that the surface tension in the time of also can applying in a flexible way the scolding tin fusion causes can be loaded onto accurate configuration second semiconductor packages at first semiconductor package.
Manufacture method according to the semiconductor device of a form of the present invention is characterized in that comprising: the operation of resin is supplied with at least a portion zone on first semiconductor chip that is loaded on first semiconductor structure; Under the state of keeping flowability at above-mentioned resin, by making at least a portion of described first semiconductor chip from described resin, expose, second semiconductor package body of loading second semiconductor chip is connected electrically in operation on above-mentioned first semiconductor structure, between opposed described first semiconductor chip and described second semiconductor package body, has the space.
Thus, under the situation of the narrow gaps between first semiconductor packages and second semiconductor packages, also can avoid soldering tin material, between first semiconductor packages and second semiconductor packages, dispose resin, the path that the moisture of guaranteeing simultaneously to be used for resin is comprised is fled from, and between first semiconductor packages and second semiconductor packages, resin is set.The cause thermal damage that consequently suppresses resin, and suppress peeling off between first semiconductor packages and second semiconductor packages, can fix first semiconductor packages and second semiconductor packages by enough resins simultaneously, carry out during secondary installing also can preventing the position deviation between first semiconductor packages and second semiconductor packages under the situation of reflow treatment.
Use under the situation of soldering tin material when on first semiconductor packages, being electrically connected second semiconductor packages, also can load onto and move second semiconductor packages, the alignment certainly that the surface tension when applying in a flexible way the scolding tin fusion causes at first semiconductor package.
Manufacture method according to the semiconductor device of a form of the present invention is characterized in that comprising: operation from resin at least a portion zone that first semiconductor package that loads first semiconductor chip is loaded onto that supply with; Keep above-mentioned resin flow, and be configured in the form on above-mentioned first semiconductor chip, second semiconductor packages of having loaded second semiconductor chip is connected electrically in the operation that above-mentioned first semiconductor package is loaded onto.
Thus, under first semiconductor packages and the diverse situation of second semiconductor packages, position deviation in the time of also can preventing the secondary installing of stacked semiconductor packages, and, can suppress peeling off between first semiconductor packages and second semiconductor packages, load onto at first semiconductor package simultaneously and dispose second semiconductor packages accurately, can save the space, and can improve the connection reliability between first semiconductor packages and second semiconductor packages.
Manufacture method according to the semiconductor device of a form of the present invention is characterized in that comprising: operation from resin at least a portion zone that first semiconductor package that loads first semiconductor chip is loaded onto that supply with; Keep above-mentioned resin flow and make the end be configured in form on above-mentioned first semiconductor chip, second semiconductor packages of having loaded second semiconductor chip is connected electrically in the operation that above-mentioned first semiconductor package is loaded onto.
Can on the first same semiconductor chip, dispose a plurality of semiconductor packages thus, and load onto at first semiconductor package and to dispose second semiconductor packages accurately, position deviation when preventing the secondary installing of stacked semiconductor packages simultaneously, and can suppress peeling off between first semiconductor packages and second semiconductor packages, further dwindle erection space, and improve the connection reliability between first semiconductor packages and second semiconductor packages.
According to the manufacture method of the semiconductor device of a form of the present invention, it is characterized in that: above-mentioned first semiconductor packages and above-mentioned second semiconductor packages are electrically connected across solder ball.
Thus,, can be electrically connected first semiconductor packages and second semiconductor packages, load onto at first semiconductor package second semiconductor packages is installed effectively by carrying out reflow treatment.
Manufacture method according to the semiconductor device of a form of the present invention is characterized in that: it is A stage condition or B stage condition that above-mentioned resin is kept mobile state.
Thus, can keep resin flow at normal temperatures or pass through heating to the resin additional liquidity, the alignment certainly that the surface tension when not damaging the scolding tin fusion causes can be electrically connected second semiconductor packages on first semiconductor packages.
Manufacture method according to the semiconductor device of a form of the present invention is characterized in that also comprising: above-mentioned second semiconductor packages is electrically connected on after above-mentioned first semiconductor package loads onto, and above-mentioned resin is moved to the operation of C stage condition.
Thus, second semiconductor packages is electrically connected on and makes resin solidification after first semiconductor package is loaded onto, the alignment certainly that the surface tension when not damaging the scolding tin fusion causes, and the enough resins of energy are fixed on first semiconductor package with second semiconductor packages and load onto.
Manufacture method according to the electronic equipment of a form of the present invention is characterized in that comprising: the operation of supplying with resin at least a portion zone in first encapsulation of loading first electronic component; Keep under the mobile state at above-mentioned resin, second encapsulation of having loaded second electronic component is electrically connected on above-mentioned first operation that encapsulates.
Behind configuration resin in first encapsulation, can with second package arrangements in first encapsulation, adjust the allocation position of the resin between first encapsulation and second encapsulation easily thus.Therefore, under the situation of the narrow gaps between first encapsulation and second encapsulation, also can be to avoid soldering tin material, between first encapsulation and second encapsulation, dispose resin, or the path fled from of the moisture of guaranteeing to be used for resin is comprised, and can between first encapsulation and second encapsulation, resin be set.Its result, the cause thermal damage that can suppress resin, and can suppress peeling off between first encapsulation and second encapsulation, simultaneously can fix first encapsulation and second encapsulation by enough resins, even carry out also can preventing under the situation of reflow treatment the position deviation of first encapsulation and second between encapsulating during secondary installing.
In addition, before configuration second encapsulation in first encapsulation,, when in first encapsulation, being electrically connected second encapsulation, also can keep the resin flow that is provided with between first encapsulation and second encapsulation even resin is configured under the situation in first encapsulation.Therefore, use under the situation of soldering tin material when being electrically connected second encapsulation in first encapsulation, the alignment certainly that the surface tension in the time of also can applying in a flexible way the scolding tin fusion causes can accurately configuration second encapsulation in first encapsulation.
Description of drawings
Fig. 1 is the sectional view of schematic construction of the semiconductor device of expression first execution mode;
Fig. 2 is the sectional view of an example of manufacture method of the semiconductor device of presentation graphs 1;
Fig. 3 is the sectional view of schematic construction of the semiconductor device of expression second execution mode;
Fig. 4 is the sectional view of schematic construction of the semiconductor device of expression the 3rd execution mode;
Fig. 5 is the sectional view of schematic construction of the semiconductor device of expression the 4th execution mode;
Fig. 6 is the sectional view of schematic construction of the semiconductor device of expression the 5th execution mode.
Among the figure,
PK1, PK2, PK11, PK12, PK21, PK22, PK31, PK32, PK41, the PK42-semiconductor packages, 1,11,21,31,41,61,71,81,91,101, the 201-carrier substrate, 2a, 2b, 9,12,22a, 22c, 32a, 32c, 42a, 42c, 62a, 62b, 72,82,92a, 92c, 102a, 102c, 202a, 202c-bank face, 3,23,33a, 33b, 43,51,63,93,103a, 103b, 103c, 203a, 203b, the 203c-semiconductor chip, 4,13,24,26,36,44,46,58,64,66,73,83,94,96,106, the 206-projection electrode, 5,25,45,65,95-anisotropic conductive sheet, the 7-solder flux, 14,37,74,84,107, the 207-sealing resin, 15,38,59,67, the 97-resin, 22b, 32b, 42b, 92b, 102b, the inner distribution of 202b-, 34a, 34b, 104a, 104b, 104c, 204a, 204b, the 204c-adhesive linkage, 35a, 35b, 105a, 105b, 105c, 205a, 205b, 205c-conductivity line, the 52-electronic pads, the 53-dielectric film, the 54-stress relaxation layer, 55-disposes distribution again, 56-solder flux resist layer, the 57-peristome.
Embodiment
Semiconductor device and manufacture method thereof below with reference to the description of drawings embodiments of the present invention.
Fig. 1 is the sectional view of schematic construction of the semiconductor device of expression first execution mode of the present invention.Among Fig. 1, carrier substrate 1 is set on the semiconductor packages PK1, is formed with bank face 2a on the two sides of carrier substrate 1 respectively, 2b.And flip-chip is installed semiconductor chip 3 on the carrier substrate 1, and semiconductor chip 3 is provided with and is used for the projection electrode 4 that flip-chip is installed.And the projection electrode 4 that is provided with on the semiconductor chip 3 is got involved anisotropic conductive sheet 5 and is engaged on the bank face 2b by ACF (anisotropic conductive film).
On the other hand, carrier substrate 11 is set on the semiconductor packages PK2, forms bank face 12 on the back side of carrier substrate 11, bank face 12 is provided with projection electrode 13.On the carrier substrate 11 semiconductor chip is installed, the carrier substrate 11 usefulness sealing resins 14 that semiconductor chip has been installed are sealed.And can be mounted to the semiconductor chip that line is welded to connect on the carrier substrate 11, and also can flip-chip be installed by semiconductor chip, also can be mounted to the stepped construction of semiconductor chip.
And, go up by the bank face 2b that is provided with on the carrier substrate 1 and to engage projection electrode 13, make carrier substrate 11 be configured in form on the semiconductor chip 3, semiconductor packages PK2 is installed on semiconductor packages PK1.
Configuration resin 15 on the semiconductor chip 3, so that expose at least a portion of semiconductor chip 3, semiconductor packages PK2 is fixed on the semiconductor chip 3 across resin 15.Here, as resin 15, can use any of resin plaster or resin sheet.
Thus, the resin 15 that is provided with on semiconductor chip 3 is semiconductor packages PK1 and semiconductor packages PK2 fixedly, at semiconductor packages PK1, is provided with between the PK2 under the situation of resin 15, also can be at semiconductor packages PK1, and residual gap between the PK2.Like this, can remove semiconductor packages PK1 easily, the moisture that comprises in the resin 15 between the PK2 when carrying out the reflow treatment of projection electrode 6 during secondary installing, also can suppress semiconductor packages PK1, and the resin 15 between the PK2 expands.Its result can suppress semiconductor packages PK1, peeling off between the PK2, and can enough resins 15 fixedly semiconductor packages PK1 and semiconductor packages PK2, can prevent semiconductor packages PK1, the position deviation between the PK2.
The form that at least a portion of semiconductor chip 3 is exposed is being provided with on the semiconductor chip 3 under the situation of resin 15, before projection electrode 13 is electrically connected semiconductor packages PK1 and semiconductor packages PK2, resin 15 can be configured on the semiconductor chip 3.And be electrically connected across projection electrode 13 under the situation of semiconductor packages PK1 and semiconductor packages PK2, preferably the resin 15 of configuration on the semiconductor chip 3 maintained A stage condition (by the softening state of intensification resin) or B stage condition (state that increases by the intensification resin viscosity).
Thus, even before configuring semiconductor encapsulation PK2 on the semiconductor packages PK1, disposing on the semiconductor chip 3 under the situation of resin 15, when projection electrode 13 is electrically connected semiconductor packages PK2 on semiconductor packages PK1, can keep semiconductor packages PK1, the flowability of the resin 15 that is provided with between the PK2.Like this, when solder ball was used as projection electrode 13, the alignment certainly that the surface tension in the time of also can applying in a flexible way the scolding tin fusion causes can encapsulate PK2 by accurate configuring semiconductor on semiconductor packages PK1.
Resin 15 also can be arranged on the central portion of semiconductor chip 15.Thus, be electrically connected under the situation of semiconductor packages PK1 and semiconductor packages PK2, also the position configuration resin 15 that can leave from projection electrode 13 across projection electrode 13.Like this, the flexible influence that can suppress resin 15 involves projection electrode 13, can improve the durability of temperature cycles etc.
The resin 15 that is provided with between semiconductor chip 3 and the semiconductor packages PK2 is compared with the anisotropic conductive sheet 5 that is provided with between semiconductor chip 3 and the carrier substrate 1, and coefficient of elasticity is low for well.Thus, the impact that is applied on the semiconductor chip 3 can effectively be absorbed by resin 15.Like this, can improve the resistance to impact of semiconductor chip 3, guarantee the reliability of semiconductor chip 3, and can encapsulate PK1, PK2 by stacked semiconductor.
In addition, also can sneak into the filler of silica, aluminium oxide etc. in the resin 15.Thus, can control the viscosity of resin 15 easily, prevent the liquid sagging of resin 15, and can control the scope that exists of resin 15 easily.
Resin 15 on the semiconductor chip 3 can only be configured on the position, but also can decentralized configuration on semiconductor chip 3.Here, by with resin 15 decentralized configuration to semiconductor chip 3, the path that moisture that resin 15 comprises is fled from can be on semiconductor chip 3, guaranteed to be used for, also the moisture that comprises in the resin 15 can be reduced under the situation of the narrow gaps between semiconductor chip 3 and semiconductor packages PK2.
As carrier substrate 1,11, for example can use two sides substrate, multi-layered wiring board, stack substrate, belt substrate or film substrate etc., as carrier substrate 1,11 material can be used the compound of for example polyamide, glass epoxy resin, BT resin, aryl amide and epoxy resin or pottery etc.As projection electrode 4,6,13, can use the Cu piece that for example covers, Ni piece or solder ball etc. by Au piece, soldering tin material etc.
In addition, at the semiconductor packages PK1 that is engaged with each other across projection electrode 13, under the situation of PK2, can use the metal bond of solder joints, alloy bond etc., or use the crimping of ACF joint, NCF (non-conductive film) joint, ACP (anisotropic conductive cream) joint, NCP (non-conductive cream) joint etc. to engage.In addition, in the above-described embodiment, illustrated the method for using ACF to engage under the situation of semiconductor chip 3 is being installed at flip-chip on the carrier substrate 1 across projection electrode 4, but also can use the crimping of NCF joint, ACP joint, NCP joint etc. to engage, also can use the metal bond of scolding tin joint, alloy bond etc.
Fig. 2 is the sectional view of an example of manufacture method of the semiconductor device of presentation graphs 1.Among Fig. 2 (a), semiconductor packages PK1 goes up under the situation of stacked semiconductor packages PK2, forms solder sphere as projection electrode 13 on the bank face 12 of semiconductor packages PK2, goes up to the bank face 2b of carrier substrate 1 simultaneously and supplies with solder flux 7.By using disperser etc. with on the resin 15 semiconductor supply chips 3.Here before stacked semiconductor packages PK2 on the semiconductor packages PK1, by supplying with resin 15 to semiconductor chip 3, semiconductor packages PK1 when stacked, under the situation of the narrow gaps between the PK2 also only the specific region on semiconductor chip 3 resin 15 easily is set.
Then shown in Fig. 2 (b), semiconductor packages PK2 is installed on semiconductor packages PK1.And, make projection electrode 13 fusions by the reflow treatment of carrying out projection electrode 13, projection electrode 13 is bonded on the bank face 2b.
Here, when being bonded on projection electrode 13 on the bank face 2b, preferably resin 15 is maintained A stage condition or B stage condition.Thus, the surface tension during by projection electrode 13 fusions can be configured in projection electrode 13 oneselfs on the bank face 2b with mating, can encapsulate PK2 by accurate configuring semiconductor on semiconductor packages PK1.And, projection electrode 13 is bonded on bank face 2b when going up, cured resin 15 under the low temperature of the temperature than the backflow of projection electrode 13 time moves to C stage condition (solid state) with resin 15.
Here, by resin 15 is set on semiconductor chip 3, make at least a portion of semiconductor chip 3 expose, guarantee that the moisture that comprises in the resin 15 flees from the gap of usefulness, and across semiconductor chip 3 semiconductor packages PK1 fixed to one another, PK2 reduces the residual quantity of the moisture that comprises in the resin 15 simultaneously.
Then shown in Fig. 2 (c), on the bank face 2a that is provided with on the back side of carrier substrate 1, be formed for carrier substrate 1 is installed in projection electrode 6 on the mother substrate 8.
Then shown in Fig. 2 (d), the carrier substrate 1 that forms projection electrode 6 is installed on the mother substrate 8.And, projection electrode 6 is bonded on the bank face 9 of mother substrate 8 by the reflow treatment of carrying out projection electrode 6.
Here,, make at least a portion of semiconductor chip 3 expose,, under the state of the moisture that comprises in the resin 15 between the PK2, can carry out the reflow treatment of projection electrode 6 at the basic semiconductor packages PK1 that removes by resin 15 is set on semiconductor chip 3.Can suppress resin 15 when projection electrode 6 refluxes like this and expand, can prevent semiconductor packages PK1, PK2 peels off each other.Carry out also can keeping with resin 15 semiconductor packages PK1 fixed to one another under the situation about refluxing again of projection electrode 13 when projection electrode 6 refluxes, the former state state of PK2 prevents semiconductor packages PK1, the position deviation between the PK2.
In the above-mentioned execution mode, illustrated for semiconductor packages PK2 is installed on the semiconductor packages PK1, when on the bank face 2b of carrier substrate 1, projection electrode 13 being set, on the bank face 12 of carrier substrate 11, supply with the method for solder flux 7, but the bank face 2b of carrier substrate 1 goes up when supplying with solder flux 7 and can on the bank face 12 of carrier substrate 11 projection electrode 13 be set.And, illustrated in the above-mentioned execution mode by using disperser etc. on semiconductor chip 3, to supply with the method for paste resin 15, but also can on semiconductor chip 3, supply with flaky resin 15.Also can go up and supply with solder(ing) paste to the bank face 2b of carrier substrate 1.
Fig. 3 is the sectional view of brief configuration of the semiconductor device of expression second execution mode of the present invention.
Among Fig. 3, carrier substrate 21 is set on the semiconductor packages PK11, forms bank face 22a respectively on the two sides of carrier substrate 21,22c forms inner distribution 22b in the carrier substrate 21 simultaneously.And flip-chip is installed semiconductor chip 23 on the carrier substrate 21, is provided for the projection electrode 24 that flip-chip is installed on the semiconductor chip 23.And, get involved anisotropic conductive sheet 25 at the projection electrode 24 that is provided with on the semiconductor chip 23 and be bonded on by ACF on the bank face 22c.The bank face 22a that the back side of carrier substrate 21 is provided with is provided with and is used for carrier substrate 21 is installed in projection electrode 26 on the mother substrate.
On the other hand, carrier substrate 31 is set on the semiconductor packages PK12, forms bank face 32a on the two sides of carrier substrate 31 respectively, 32c simultaneously, is formed with inner distribution 32b in the carrier substrate 31.And, across adhesive linkage 34a positive semiconductor chip 33a being installed on the carrier substrate 31, semiconductor chip 33a is welded to connect in bank face 32c across conductivity line 35a line.In addition, avoid conductivity line 35a positive on the semiconductor chip 33a semiconductor chip 33b is installed, semiconductor chip 33b is fixed on across adhesive linkage 34b and installs on the semiconductor chip 33a, is welded to connect in bank face 32c across conductivity line 35b line simultaneously.
On the bank face 32a that is provided with on the back side of carrier substrate 31, so that carrier substrate 31 remains on form on the semiconductor chip 23, is provided with and is used for carrier substrate 31 is installed in projection electrode 36 on the carrier substrate 21.Here, make projection electrode 36 avoid the loading area ground configuration of semiconductor chip 23, for example can be at the back periphery configuration projection electrode 36 of carrier substrate 31.And the bank face 22c that is provided with on the carrier substrate 21 goes up and engages projection electrode 36, makes carrier substrate 31 be installed on the carrier substrate 21.
At semiconductor chip 33a, on the carrier substrate 31 of the installed surface side of 33b sealing resin 37 is set, sealed semiconductor chip 33a, 33b by sealing resin 37.Sealing resin 37 sealing semiconductor chips 33a, under the situation of 33b, compression molding by using the heat reactive resin of epoxy resin etc. for example etc. is carried out.
Configuration resin 38 is to expose at least a portion of semiconductor chip 23 on semiconductor chip 23, and semiconductor packages PK12 is fixed on the semiconductor chip 23 across resin 38.Here at least a portion of semiconductor chip 23 is being provided with on the semiconductor chip 23 under the situation of resin 38 with exposing, before projection electrode 36 is electrically connected semiconductor packages PK11 and semiconductor packages PK12, can dispose resin 38 on semiconductor chip 23.And the resin 38 of configuration maintains A stage condition or B stage condition for well be electrically connected under the situation of semiconductor packages PK11 and semiconductor packages PK12 semiconductor chip 23 across projection electrode 36 on.
Thus, semiconductor packages PK11 is under the situation of variety classes or different sizes with semiconductor packages PK12, also can prevent stacked semiconductor packages PK11, the position deviation during secondary installing between the PK12, and suppress semiconductor packages PK11, peeling off between the PK12, apply in a flexible way simultaneously from alignment, configuring semiconductor encapsulation PK12 on semiconductor packages PK11 can save the space accurately, and improve semiconductor packages PK11, the connection between the PK12 is by reliability.
Fig. 4 is the sectional view of brief configuration of the semiconductor device of expression the 3rd execution mode of the present invention.
Among Fig. 4, carrier substrate 41 is set on the semiconductor packages PK21, forms bank face 42a on the two sides of carrier substrate 41 respectively, 42c forms inner distribution 42b in the carrier substrate 41 simultaneously.And flip-chip is installed semiconductor chip 43 on the carrier substrate 41, and semiconductor chip 43 is provided with and is used for the projection electrode 44 that flip-chip is installed.And the projection electrode 44 that is provided with on the semiconductor chip 43 is got involved anisotropic conductive sheet 45 and is bonded on the bank face 42c by ACF.The bank face 42a that the back side of carrier substrate 41 is provided with is provided with and is used for carrier substrate 41 is installed in projection electrode 46 on the mother substrate.On the other hand, semiconductor chip 51 is set on the semiconductor packages PK22, when electronic pads 52 was set on the semiconductor chip 51, the form that electronic pads 52 is exposed was provided with dielectric film 53.And on semiconductor chip 51, expose form, the formation stress relaxation layer 54 of electronic pads 52, be formed on the distribution of configuration again 55 that extends on the stress relaxation layer 54 on the electronic pads 52.
And, dispose again and form scolder resist film 56 on the distribution 55, be formed with on the scolder resist film 56 and in stress relaxation layer 54, expose the peristome 57 that disposes distribution 55 again.And being provided on the distribution 55 semiconductor chip 51 faced down across disposing again of exposing of peristome 57 is installed in projection electrode 58 on the carrier substrate 41, so that semiconductor packages PK32 is remained on the semiconductor chip 53.
Here, projection electrode 58 is avoided the loading area configuration of semiconductor chip 43, for example disposes projection electrode 58 around semiconductor chip 51.And, on the bank face 42c that is provided with on the carrier substrate 41, engage projection electrode 58, semiconductor chip PK22 is installed on the carrier substrate 41.
In addition, configuration resin 59 is to expose at least a portion of semiconductor chip 43 on the semiconductor chip 43, and semiconductor chip PK22 is fixed on the semiconductor chip 43 across resin 59.At least a portion of semiconductor chip 43 is being provided with on the semiconductor chip 43 under the situation of resin 59 with exposing, before projection electrode 58 is electrically connected semiconductor packages PK21 and semiconductor packages PK22, can on semiconductor chip 53, disposes resin 59.And be electrically connected under the situation of semiconductor packages PK21 and semiconductor packages PK22 across projection electrode 58, preferably the resin 59 with configuration on the semiconductor chip 43 maintains A stage condition or B stage condition.
Thus, during stacked W-CSP on semiconductor packages PK21 (wafer scale-die size encapsulation), prevent stacked semiconductor packages PK21, PK22 is position deviation when secondary installing, and can suppress semiconductor packages PK21, peeling off between the PK22, the alignment certainly of applying in a flexible way simultaneously is configured in semiconductor packages PK22 accurately on the semiconductor packages PK21 and becomes possibility.Therefore, semiconductor chip 43, under 51 kind or the situation about varying in size, also not be used between the semiconductor chip 43,51 and insert carrier substrate, can on semiconductor chip 43,3 dimensions be installed by semiconductor chip 51, and realization semiconductor chip 43,51 install the time save space, and the reliability that improves 3 dimension mounted semiconductor chip 43,51 becomes possibility.
Fig. 5 is the sectional view of brief configuration of the semiconductor device of expression the 4th execution mode of the present invention.
Among Fig. 5, carrier substrate 61 is set on the semiconductor packages PK31, forms bank face 62a on the two sides of carrier substrate 61 respectively, 62b.And flip-chip is installed semiconductor chip 63 on the carrier substrate 61, and semiconductor chip 63 is provided with and is used for the projection electrode 64 that flip-chip is installed.And the projection electrode 64 that is provided with on the semiconductor chip 63 is got involved anisotropic conductive sheet 65 and is bonded on the bank face 62b by ACF.On the other hand, semiconductor packages PK32 is provided with carrier substrate 71,81 respectively on the PK33, form bank face 72,82 on the back side of carrier substrate 71,81 respectively, is respectively equipped with the projection electrode 73,83 of solder ball etc. on the bank face 72,82.Semiconductor chip is installed respectively on the carrier substrate 71,81, and the carrier substrate 71,81 that semiconductor chip is installed uses sealing resin 74,84 sealed respectively.
And, by engaging projection electrode 73,83 respectively on the bank face 62b that is provided with on the carrier substrate 61, so that carrier substrate 71,81 end is configured in the form on the semiconductor chip 63 respectively, and with a plurality of semiconductor packages PK32, PK33 is installed on the semiconductor packages PK31.
In addition, on the semiconductor chip 63 configuration resin 67 exposing at least a portion of semiconductor chip 63, semiconductor packages PK32, the end of PK33 is fixed on the semiconductor chip 63 across resin 67.Here at least a portion of semiconductor chip 63 is being provided with on the semiconductor chip 63 under the situation of resin 67 with exposing, respectively across projection electrode 73,83 are electrically connected semiconductor packages PK31 and semiconductor packages K32, before the PK33, can dispose resin 67 on semiconductor chip 63.And be electrically connected semiconductor packages PK31 and semiconductor packages PK32 across projection electrode 73,83 respectively, under the situation of PK33, preferably the resin 59 that will dispose on semiconductor chip 63 maintains A stage condition or B stage condition.
Thus, can prevent semiconductor packages PK31, PK32, the position deviation of PK33 when secondary installing, and can suppress semiconductor packages PK32, peeling off between PK33 and the semiconductor packages PK31, simultaneously, on same semiconductor chip 63, can dispose a plurality of semiconductor packages PK32, PK33, and apply in a flexible way from aliging semiconductor packages PK32, PK33 is configured on the semiconductor packages PK31 accurately becomes possibility.Therefore, can save the space, and with semiconductor packages PK32, PK33 is configured in accurately on the semiconductor packages Pk31, can improves semiconductor packages PK31, PK32, the reliability of PK33 simultaneously.
Semiconductor chip 63 and semiconductor packages PK32 are provided with respectively between the PK33 under the situation of resin 67, can be after supplying with resin 67 to semiconductor chip 63, and configuring semiconductor encapsulates PK32, PK33 respectively on semiconductor chip 63.Also can be at difference configuring semiconductor encapsulation PK32 on semiconductor chip 63, across semiconductor packages PK32, resin 67 is supplied with in the gap between the PK33 on semiconductor chip 63 behind the PK33.
Fig. 6 is the sectional view of brief configuration of the semiconductor device of expression the 5th execution mode of the present invention.
Among Fig. 6, carrier substrate 91 is set on the semiconductor packages PK41, forms bank face 92a on the two sides of carrier substrate 91 respectively, 92b forms inner distribution 92b in the carrier substrate 91 simultaneously.And flip-chip is installed semiconductor chip 93 on the carrier substrate 91, is provided for the projection electrode 94 that flip-chip is installed on the semiconductor chip 93.And the projection electrode 94 that is provided with on the semiconductor chip 93 is got involved anisotropic conductive sheet 95 and is bonded on bank face 92c by ACF.The bank face 92a that is provided with on the back side of carrier substrate 91 is provided with the projection electrode 96 that is used for carrier substrate 91 is installed to mother substrate.
On the other hand, semiconductor packages PK42 is respectively equipped with carrier substrate 101,201 on the PK43.And form bank face 102a on the back side of carrier substrate 101,201 respectively, and in the time of 202a, the surface of carrier substrate 101,201 forms bank face 102c respectively, and 202c forms inner distribution 102b respectively, 202b in the carrier substrate 101,201.
And respectively across adhesive linkage 104a, 204a positive separately installs semiconductor chip 103a on the carrier substrate 101,201, and 203a, semiconductor chip 103a, 203a are respectively across conductor wire 105a, and 205a line separately is welded to connect at bank face 102c, 202c.
In addition, semiconductor chip 103a is on the 203a, to avoid conductor wire 105a, 205a positive respectively installs semiconductor chip 103b, 203b, semiconductor chip 103b, 203b is respectively across adhesive linkage 104b, 204b is fixed in semiconductor chip 103a separately, on the 203a, simultaneously respectively across conductor wire 105b, 205b line separately is welded to connect at bank face 102c, 202c.In addition, semiconductor chip 103b is on the 203b, to avoid conductor wire 105b, the form of 205b, positive installation semiconductor chip 103c respectively, 203c, semiconductor chip 103c, 203c are respectively across adhesive linkage 104c, and 204c is fixed in semiconductor chip 103b separately, on the 203b, respectively across conductor wire 105c, 205c line respectively is welded to connect at bank face 102c, 202c simultaneously.
In addition, the bank face 102a that is provided with respectively on the back side of carrier substrate 101,201, on the 202a, carrier substrate 101,201 is supported in the form on the semiconductor chip 93 respectively, be respectively equipped with and be used for carrier substrate 101,201 is installed in projection electrode 106,206 on the carrier substrate 91 respectively.Here projection electrode 106,206 preferably is present on 4 jiaos of carrier substrate 101,201 at least, for example can arrange projection electrode 106,206 by コ word shape.
And by on the bank face 92c that is arranged at setting on the carrier substrate 91, engaging projection electrode 106 respectively, 206, make the end of carrier substrate 101,201 be configured in form on the semiconductor chip 93 respectively, carrier substrate 101,201 can be installed in respectively on the carrier substrate 91.On the carrier substrate 101,201 of the installed surface side of semiconductor chip 103a～03c, 203a～203c, sealing resin 107,207 is set respectively, by sealing resin 107,207 sealing semiconductor chips 103a～103c, 203a～203c respectively.
In addition, on the semiconductor chip 93 configuration resin 97 exposing at least a portion of semiconductor chip 93, semiconductor packages PK42, the end of PK43 is fixed on the semiconductor chip 93 across resin 97.Here, so that at least a portion of semiconductor chip 93 is being provided with on the semiconductor chip 93 under the situation of resin 97 with exposing, be electrically connected semiconductor packages PK41 and semiconductor packages PK42 across projection electrode 106,206 respectively, before the PK43, can on semiconductor chip 93, dispose resin 97.And be electrically connected semiconductor packages PK41 and semiconductor packages PK42 across projection electrode 106,206 respectively, under 43 the situation, preferably the resin 59 with configuration on the semiconductor chip 93 maintains A stage condition or B stage condition.
Thus, on same semiconductor chip 93, can dispose a plurality of semiconductor packages PK42, PK43 can dwindle erection space, and realizes different types of semiconductor chip 93, the three-dimensional of 103a～103c, 203a～203c is installed, suppress semiconductor packages PK42 simultaneously, peeling off between PK43 and the semiconductor packages PK41, and prevent semiconductor packages PK41, PK42, the position deviation of PK43 when two dimension is installed.Even with semiconductor packages PK42, PK43 is configured in before the semiconductor packages PK41, under the situation of configuration resin 97 on the semiconductor chip 93, respectively across projection electrode 106,206 with semiconductor packages PK42, when PK43 is connected electrically on the semiconductor packages PK41, can keep semiconductor packages PK41 and semiconductor packages PK42, the flowability of the resin 97 that is provided with between the PK43.Therefore, solder ball had been used separately as projection electrode at 106,206 o'clock, the surface tension in the time of can applying in a flexible way the scolding tin fusion and cause the alignment certainly of (bringing), can be on semiconductor packages PK41 configuring semiconductor encapsulation PK42 respectively accurately, PK43.
Above-mentioned semiconductor device goes for for example electronic instrument of liquid crystal indicator, portable phone, portable information terminal, video camera, digital camera, MD (Mini Disk) player etc., can realize miniaturization, the lightweight of electronic instrument, and improve the reliability of electronic instrument.
In addition, in the above-described embodiment, for example understand the method for stacked semiconductor encapsulation, but the present invention is not limited to the method for stacked semiconductor encapsulation, for example can be used for the various transducer classes etc. of optical element, Magnetic Sensor and biology sensor etc. of ceramic component, optical modulator and the optical switch etc. of stacked elastic surface wave (SAW) element etc.

Claims (5)

1. the manufacture method of a semiconductor device is characterized in that, comprising:
The operation of resin is supplied with at least a portion zone on first semiconductor chip on first semiconductor structure; With
Keep under the mobile state at above-mentioned resin, by making at least a portion of described first semiconductor structure from described resin, expose, second semiconductor package body be connected electrically in operation on above-mentioned first semiconductor structure,
Between opposed described first semiconductor structure and described second semiconductor package body, there is the space.
2. the manufacture method of a semiconductor device is characterized in that, comprising:
The operation of resin is supplied with at least a portion zone on first semiconductor chip that is loaded on first semiconductor structure; With
Keep under the mobile state at above-mentioned resin, by making at least a portion of described first semiconductor chip from described resin, expose, second semiconductor package body of loading second semiconductor chip be connected electrically in operation on above-mentioned first semiconductor structure,
Between opposed described first semiconductor chip and described second semiconductor package body, there is the space.
3. according to the manufacture method of each the described semiconductor device in the claim 1～2, it is characterized in that: above-mentioned first semiconductor structure and above-mentioned second semiconductor package body are electrically connected across solder ball.
4. according to the manufacture method of each the described semiconductor device in the claim 1～2, it is characterized in that:
It is by softening state of intensification resin or the state that increases by the intensification resin viscosity that above-mentioned resin is kept mobile state.
5. according to the manufacture method of each the described semiconductor device in the claim 1～2, it is characterized in that, also comprise:
After above-mentioned second semiconductor package body is electrically connected on above-mentioned first semiconductor structure, above-mentioned resin is moved to the operation of solid state.
CNB2004100386304A 2003-05-02 2004-04-27 Method of manufacturing semiconductor device and electronic device Expired - Fee Related CN1286158C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003127058A JP2004335604A (en) 2003-05-02 2003-05-02 Process for manufacturing semiconductor device, and process for manufacturing electronic device
JP2003127058 2003-05-02

Publications (2)

Publication Number Publication Date
CN1542932A CN1542932A (en) 2004-11-03
CN1286158C true CN1286158C (en) 2006-11-22

Family

ID=33503750

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100386304A Expired - Fee Related CN1286158C (en) 2003-05-02 2004-04-27 Method of manufacturing semiconductor device and electronic device

Country Status (2)

Country Link
JP (1) JP2004335604A (en)
CN (1) CN1286158C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4324773B2 (en) * 2003-09-24 2009-09-02 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP6010880B2 (en) * 2011-04-15 2016-10-19 株式会社ニコン POSITION INFORMATION DETECTING SENSOR, POSITION INFORMATION DETECTING SENSOR MANUFACTURING METHOD, ENCODER, MOTOR DEVICE, AND ROBOT DEVICE
CN106601636B (en) * 2016-12-21 2018-11-09 江苏长电科技股份有限公司 A kind of process of the pre-packaged metal conduction three-dimension packaging structure of attachment
JP6598811B2 (en) * 2017-03-23 2019-10-30 Ｔｏｗａ株式会社 Semiconductor package placement apparatus, manufacturing apparatus, semiconductor package placement method, and electronic component manufacturing method

Also Published As

Publication number Publication date
CN1542932A (en) 2004-11-03
JP2004335604A (en) 2004-11-25

Similar Documents

Publication Publication Date Title
CN100342538C (en) Semiconductor device, electronic apparatus and their manufacturing methods, electronic equipment
CN100349292C (en) Semiconductor device and its producing method, electronic device and electronic instrument
CN101221946B (en) Manufacture method of semiconductor package, system package module
CN1229863C (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
CN1265455C (en) Production method for conductive paste and production method for printed circuit board
CN1291467C (en) Electronic device and its manufacture method
EP1229577A2 (en) Flip chip semiconductor device in a moulded chip scale package (csp) and method of assembly
CN1695246A (en) Semiconductor package and laminated semiconductor package
CN1185698C (en) Semiconductor device and manufacture method thereof, circuit board and electronic apparatus
CN1551343A (en) Electronic component packaging structure and method for producing the same
TW200414471A (en) Semiconductor device and manufacturing method for the same
CN1453868A (en) Multi-chip package and producing method thereof
JP2009152253A (en) Semiconductor device and method of manufacturing the same
CN1542963A (en) Semiconductor device and method of manufacturing the same, electronic device, electronic instrument
US7911064B2 (en) Mounted body and method for manufacturing the same
CN2636411Y (en) Multichip packaging structure
JP2006295183A (en) Multi-package module provided with stacked packages having asymmetrically disposed die and molding
CN1531088A (en) Semiconductor device, electronic apparatus and their manufacturing methods, electronic equipment
CN1532930A (en) Semiconductor, electronic device and their producing method and electronic instrument
CN1286158C (en) Method of manufacturing semiconductor device and electronic device
CN1228839C (en) Multi-die package
CN1497713A (en) Semiconductor device and its manufacturing method
US20080179726A1 (en) Multi-chip semiconductor package and method for fabricating the same
KR100510518B1 (en) Semiconductor device and packaging method of the semiconductor device
EP2498284A2 (en) Method of fabricating a semiconductor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061122

Termination date: 20140427